| Line Number |
../DebugInfoTest/example_mips_dbg.ll
BUT NOT
../DebugInfoTest/example_mips.ll
|
Line Number |
../DebugInfoTest/example_mips.ll
BUT NOT
../DebugInfoTest/example_mips_dbg.ll
|
| 1 |
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
1 |
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 |
|* *| |
2 |
|* *| |
| 3 |
|* Global Instruction Selector for the Mips target *| |
3 |
|* Global Instruction Selector for the Mips target *| |
| 4 |
|* *| |
4 |
|* *| |
| 5 |
|* Automatically generated file, do not edit! *| |
5 |
|* Automatically generated file, do not edit! *| |
| 6 |
|* *| |
6 |
|* *| |
| 7 |
\*===----------------------------------------------------------------------===*/ |
7 |
\*===----------------------------------------------------------------------===*/ |
| 8 |
|
8 |
|
| 9 |
#ifdef GET_GLOBALISEL_PREDICATE_BITSET |
9 |
#ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 10 |
const unsigned MAX_SUBTARGET_PREDICATES = 44; |
10 |
const unsigned MAX_SUBTARGET_PREDICATES = 44; |
| 11 |
using PredicateBitset = llvm::PredicateBitsetImpl; |
11 |
using PredicateBitset = llvm::PredicateBitsetImpl; |
| 12 |
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET |
12 |
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 13 |
|
13 |
|
| 14 |
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
14 |
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 15 |
mutable MatcherState State; |
15 |
mutable MatcherState State; |
| 16 |
typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; |
16 |
typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; |
| 17 |
typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; |
17 |
typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; |
| 18 |
const ExecInfoTy ExecInfo; |
18 |
const ExecInfoTy ExecInfo; |
| 19 |
static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; |
19 |
static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; |
| 20 |
static MipsInstructionSelector::CustomRendererFn CustomRenderers[]; |
20 |
static MipsInstructionSelector::CustomRendererFn CustomRenderers[]; |
| 21 |
bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; |
21 |
bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; |
| 22 |
bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; |
22 |
bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; |
| 23 |
bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; |
23 |
bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; |
| 24 |
const int64_t *getMatchTable() const override; |
24 |
const int64_t *getMatchTable() const override; |
| 25 |
bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; |
25 |
bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; |
| 26 |
bool testSimplePredicate(unsigned PredicateID) const override; |
26 |
bool testSimplePredicate(unsigned PredicateID) const override; |
| 27 |
void runCustomAction(unsigned FnID, const MatcherState &State) const override; |
27 |
void runCustomAction(unsigned FnID, const MatcherState &State) const override; |
| 28 |
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
28 |
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 29 |
|
29 |
|
| 30 |
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
30 |
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 31 |
, State(0), |
31 |
, State(0), |
| 32 |
ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) |
32 |
ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) |
| 33 |
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
33 |
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 34 |
|
34 |
|
| 35 |
#ifdef GET_GLOBALISEL_IMPL |
35 |
#ifdef GET_GLOBALISEL_IMPL |
| 36 |
// LLT Objects. |
36 |
// LLT Objects. |
| 37 |
enum { |
37 |
enum { |
| 38 |
GILLT_s16, |
38 |
GILLT_s16, |
| 39 |
GILLT_s32, |
39 |
GILLT_s32, |
| 40 |
GILLT_s64, |
40 |
GILLT_s64, |
| 41 |
GILLT_v2s16, |
41 |
GILLT_v2s16, |
| 42 |
GILLT_v2s64, |
42 |
GILLT_v2s64, |
| 43 |
GILLT_v4s8, |
43 |
GILLT_v4s8, |
| 44 |
GILLT_v4s32, |
44 |
GILLT_v4s32, |
| 45 |
GILLT_v8s16, |
45 |
GILLT_v8s16, |
| 46 |
GILLT_v16s8, |
46 |
GILLT_v16s8, |
| 47 |
}; |
47 |
}; |
| 48 |
const static size_t NumTypeObjects = 9; |
48 |
const static size_t NumTypeObjects = 9; |
| 49 |
const static LLT TypeObjects[] = { |
49 |
const static LLT TypeObjects[] = { |
| 50 |
LLT::scalar(16), |
50 |
LLT::scalar(16), |
| 51 |
LLT::scalar(32), |
51 |
LLT::scalar(32), |
| 52 |
LLT::scalar(64), |
52 |
LLT::scalar(64), |
| 53 |
LLT::vector(ElementCount::getFixed(2), 16), |
53 |
LLT::vector(ElementCount::getFixed(2), 16), |
| 54 |
LLT::vector(ElementCount::getFixed(2), 64), |
54 |
LLT::vector(ElementCount::getFixed(2), 64), |
| 55 |
LLT::vector(ElementCount::getFixed(4), 8), |
55 |
LLT::vector(ElementCount::getFixed(4), 8), |
| 56 |
LLT::vector(ElementCount::getFixed(4), 32), |
56 |
LLT::vector(ElementCount::getFixed(4), 32), |
| 57 |
LLT::vector(ElementCount::getFixed(8), 16), |
57 |
LLT::vector(ElementCount::getFixed(8), 16), |
| 58 |
LLT::vector(ElementCount::getFixed(16), 8), |
58 |
LLT::vector(ElementCount::getFixed(16), 8), |
| 59 |
}; |
59 |
}; |
| 60 |
|
60 |
|
| 61 |
// Bits for subtarget features that participate in instruction matching. |
61 |
// Bits for subtarget features that participate in instruction matching. |
| 62 |
enum SubtargetFeatureBits : uint8_t { |
62 |
enum SubtargetFeatureBits : uint8_t { |
| 63 |
Feature_HasMips2Bit = 7, |
63 |
Feature_HasMips2Bit = 7, |
| 64 |
Feature_HasMips3Bit = 17, |
64 |
Feature_HasMips3Bit = 17, |
| 65 |
Feature_HasMips4_32Bit = 27, |
65 |
Feature_HasMips4_32Bit = 27, |
| 66 |
Feature_NotMips4_32Bit = 28, |
66 |
Feature_NotMips4_32Bit = 28, |
| 67 |
Feature_HasMips4_32r2Bit = 18, |
67 |
Feature_HasMips4_32r2Bit = 18, |
| 68 |
Feature_HasMips32Bit = 3, |
68 |
Feature_HasMips32Bit = 3, |
| 69 |
Feature_HasMips32r2Bit = 6, |
69 |
Feature_HasMips32r2Bit = 6, |
| 70 |
Feature_HasMips32r6Bit = 29, |
70 |
Feature_HasMips32r6Bit = 29, |
| 71 |
Feature_NotMips32r6Bit = 4, |
71 |
Feature_NotMips32r6Bit = 4, |
| 72 |
Feature_IsGP64bitBit = 22, |
72 |
Feature_IsGP64bitBit = 22, |
| 73 |
Feature_IsPTR64bitBit = 24, |
73 |
Feature_IsPTR64bitBit = 24, |
| 74 |
Feature_HasMips64Bit = 25, |
74 |
Feature_HasMips64Bit = 25, |
| 75 |
Feature_HasMips64r2Bit = 23, |
75 |
Feature_HasMips64r2Bit = 23, |
| 76 |
Feature_HasMips64r6Bit = 30, |
76 |
Feature_HasMips64r6Bit = 30, |
| 77 |
Feature_NotMips64r6Bit = 5, |
77 |
Feature_NotMips64r6Bit = 5, |
| 78 |
Feature_InMips16ModeBit = 31, |
78 |
Feature_InMips16ModeBit = 31, |
| 79 |
Feature_NotInMips16ModeBit = 0, |
79 |
Feature_NotInMips16ModeBit = 0, |
| 80 |
Feature_HasCnMipsBit = 26, |
80 |
Feature_HasCnMipsBit = 26, |
| 81 |
Feature_NotCnMipsBit = 8, |
81 |
Feature_NotCnMipsBit = 8, |
| 82 |
Feature_IsSym32Bit = 38, |
82 |
Feature_IsSym32Bit = 38, |
| 83 |
Feature_IsSym64Bit = 39, |
83 |
Feature_IsSym64Bit = 39, |
| 84 |
Feature_IsN64Bit = 40, |
84 |
Feature_IsN64Bit = 40, |
| 85 |
Feature_RelocNotPICBit = 9, |
85 |
Feature_RelocNotPICBit = 9, |
| 86 |
Feature_RelocPICBit = 37, |
86 |
Feature_RelocPICBit = 37, |
| 87 |
Feature_NoNaNsFPMathBit = 21, |
87 |
Feature_NoNaNsFPMathBit = 21, |
| 88 |
Feature_UseAbsBit = 14, |
88 |
Feature_UseAbsBit = 14, |
| 89 |
Feature_HasStdEncBit = 1, |
89 |
Feature_HasStdEncBit = 1, |
| 90 |
Feature_NotDSPBit = 11, |
90 |
Feature_NotDSPBit = 11, |
| 91 |
Feature_InMicroMipsBit = 35, |
91 |
Feature_InMicroMipsBit = 35, |
| 92 |
Feature_NotInMicroMipsBit = 2, |
92 |
Feature_NotInMicroMipsBit = 2, |
| 93 |
Feature_IsLEBit = 42, |
93 |
Feature_IsLEBit = 42, |
| 94 |
Feature_IsBEBit = 43, |
94 |
Feature_IsBEBit = 43, |
| 95 |
Feature_IsNotNaClBit = 19, |
95 |
Feature_IsNotNaClBit = 19, |
| 96 |
Feature_HasEVABit = 36, |
96 |
Feature_HasEVABit = 36, |
| 97 |
Feature_HasMSABit = 34, |
97 |
Feature_HasMSABit = 34, |
| 98 |
Feature_HasMadd4Bit = 20, |
98 |
Feature_HasMadd4Bit = 20, |
| 99 |
Feature_UseIndirectJumpsHazardBit = 12, |
99 |
Feature_UseIndirectJumpsHazardBit = 12, |
| 100 |
Feature_NoIndirectJumpGuardsBit = 10, |
100 |
Feature_NoIndirectJumpGuardsBit = 10, |
| 101 |
Feature_AllowFPOpFusionBit = 41, |
101 |
Feature_AllowFPOpFusionBit = 41, |
| 102 |
Feature_IsFP64bitBit = 16, |
102 |
Feature_IsFP64bitBit = 16, |
| 103 |
Feature_NotFP64bitBit = 15, |
103 |
Feature_NotFP64bitBit = 15, |
| 104 |
Feature_IsNotSoftFloatBit = 13, |
104 |
Feature_IsNotSoftFloatBit = 13, |
| 105 |
Feature_HasDSPBit = 32, |
105 |
Feature_HasDSPBit = 32, |
| 106 |
Feature_HasDSPR2Bit = 33, |
106 |
Feature_HasDSPR2Bit = 33, |
| 107 |
}; |
107 |
}; |
| 108 |
|
108 |
|
| 109 |
PredicateBitset MipsInstructionSelector:: |
109 |
PredicateBitset MipsInstructionSelector:: |
| 110 |
computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const { |
110 |
computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const { |
| 111 |
PredicateBitset Features; |
111 |
PredicateBitset Features; |
| 112 |
if (Subtarget->hasMips2()) |
112 |
if (Subtarget->hasMips2()) |
| 113 |
Features.set(Feature_HasMips2Bit); |
113 |
Features.set(Feature_HasMips2Bit); |
| 114 |
if (Subtarget->hasMips3()) |
114 |
if (Subtarget->hasMips3()) |
| 115 |
Features.set(Feature_HasMips3Bit); |
115 |
Features.set(Feature_HasMips3Bit); |
| 116 |
if (Subtarget->hasMips4_32()) |
116 |
if (Subtarget->hasMips4_32()) |
| 117 |
Features.set(Feature_HasMips4_32Bit); |
117 |
Features.set(Feature_HasMips4_32Bit); |
| 118 |
if (!Subtarget->hasMips4_32()) |
118 |
if (!Subtarget->hasMips4_32()) |
| 119 |
Features.set(Feature_NotMips4_32Bit); |
119 |
Features.set(Feature_NotMips4_32Bit); |
| 120 |
if (Subtarget->hasMips4_32r2()) |
120 |
if (Subtarget->hasMips4_32r2()) |
| 121 |
Features.set(Feature_HasMips4_32r2Bit); |
121 |
Features.set(Feature_HasMips4_32r2Bit); |
| 122 |
if (Subtarget->hasMips32()) |
122 |
if (Subtarget->hasMips32()) |
| 123 |
Features.set(Feature_HasMips32Bit); |
123 |
Features.set(Feature_HasMips32Bit); |
| 124 |
if (Subtarget->hasMips32r2()) |
124 |
if (Subtarget->hasMips32r2()) |
| 125 |
Features.set(Feature_HasMips32r2Bit); |
125 |
Features.set(Feature_HasMips32r2Bit); |
| 126 |
if (Subtarget->hasMips32r6()) |
126 |
if (Subtarget->hasMips32r6()) |
| 127 |
Features.set(Feature_HasMips32r6Bit); |
127 |
Features.set(Feature_HasMips32r6Bit); |
| 128 |
if (!Subtarget->hasMips32r6()) |
128 |
if (!Subtarget->hasMips32r6()) |
| 129 |
Features.set(Feature_NotMips32r6Bit); |
129 |
Features.set(Feature_NotMips32r6Bit); |
| 130 |
if (Subtarget->isGP64bit()) |
130 |
if (Subtarget->isGP64bit()) |
| 131 |
Features.set(Feature_IsGP64bitBit); |
131 |
Features.set(Feature_IsGP64bitBit); |
| 132 |
if (Subtarget->isABI_N64()) |
132 |
if (Subtarget->isABI_N64()) |
| 133 |
Features.set(Feature_IsPTR64bitBit); |
133 |
Features.set(Feature_IsPTR64bitBit); |
| 134 |
if (Subtarget->hasMips64()) |
134 |
if (Subtarget->hasMips64()) |
| 135 |
Features.set(Feature_HasMips64Bit); |
135 |
Features.set(Feature_HasMips64Bit); |
| 136 |
if (Subtarget->hasMips64r2()) |
136 |
if (Subtarget->hasMips64r2()) |
| 137 |
Features.set(Feature_HasMips64r2Bit); |
137 |
Features.set(Feature_HasMips64r2Bit); |
| 138 |
if (Subtarget->hasMips64r6()) |
138 |
if (Subtarget->hasMips64r6()) |
| 139 |
Features.set(Feature_HasMips64r6Bit); |
139 |
Features.set(Feature_HasMips64r6Bit); |
| 140 |
if (!Subtarget->hasMips64r6()) |
140 |
if (!Subtarget->hasMips64r6()) |
| 141 |
Features.set(Feature_NotMips64r6Bit); |
141 |
Features.set(Feature_NotMips64r6Bit); |
| 142 |
if (Subtarget->inMips16Mode()) |
142 |
if (Subtarget->inMips16Mode()) |
| 143 |
Features.set(Feature_InMips16ModeBit); |
143 |
Features.set(Feature_InMips16ModeBit); |
| 144 |
if (!Subtarget->inMips16Mode()) |
144 |
if (!Subtarget->inMips16Mode()) |
| 145 |
Features.set(Feature_NotInMips16ModeBit); |
145 |
Features.set(Feature_NotInMips16ModeBit); |
| 146 |
if (Subtarget->hasCnMips()) |
146 |
if (Subtarget->hasCnMips()) |
| 147 |
Features.set(Feature_HasCnMipsBit); |
147 |
Features.set(Feature_HasCnMipsBit); |
| 148 |
if (!Subtarget->hasCnMips()) |
148 |
if (!Subtarget->hasCnMips()) |
| 149 |
Features.set(Feature_NotCnMipsBit); |
149 |
Features.set(Feature_NotCnMipsBit); |
| 150 |
if (Subtarget->hasSym32()) |
150 |
if (Subtarget->hasSym32()) |
| 151 |
Features.set(Feature_IsSym32Bit); |
151 |
Features.set(Feature_IsSym32Bit); |
| 152 |
if (!Subtarget->hasSym32()) |
152 |
if (!Subtarget->hasSym32()) |
| 153 |
Features.set(Feature_IsSym64Bit); |
153 |
Features.set(Feature_IsSym64Bit); |
| 154 |
if (Subtarget->isABI_N64()) |
154 |
if (Subtarget->isABI_N64()) |
| 155 |
Features.set(Feature_IsN64Bit); |
155 |
Features.set(Feature_IsN64Bit); |
| 156 |
if (!TM.isPositionIndependent()) |
156 |
if (!TM.isPositionIndependent()) |
| 157 |
Features.set(Feature_RelocNotPICBit); |
157 |
Features.set(Feature_RelocNotPICBit); |
| 158 |
if (TM.isPositionIndependent()) |
158 |
if (TM.isPositionIndependent()) |
| 159 |
Features.set(Feature_RelocPICBit); |
159 |
Features.set(Feature_RelocPICBit); |
| 160 |
if (TM.Options.NoNaNsFPMath) |
160 |
if (TM.Options.NoNaNsFPMath) |
| 161 |
Features.set(Feature_NoNaNsFPMathBit); |
161 |
Features.set(Feature_NoNaNsFPMathBit); |
| 162 |
if (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath) |
162 |
if (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath) |
| 163 |
Features.set(Feature_UseAbsBit); |
163 |
Features.set(Feature_UseAbsBit); |
| 164 |
if (Subtarget->hasStandardEncoding()) |
164 |
if (Subtarget->hasStandardEncoding()) |
| 165 |
Features.set(Feature_HasStdEncBit); |
165 |
Features.set(Feature_HasStdEncBit); |
| 166 |
if (!Subtarget->hasDSP()) |
166 |
if (!Subtarget->hasDSP()) |
| 167 |
Features.set(Feature_NotDSPBit); |
167 |
Features.set(Feature_NotDSPBit); |
| 168 |
if (Subtarget->inMicroMipsMode()) |
168 |
if (Subtarget->inMicroMipsMode()) |
| 169 |
Features.set(Feature_InMicroMipsBit); |
169 |
Features.set(Feature_InMicroMipsBit); |
| 170 |
if (!Subtarget->inMicroMipsMode()) |
170 |
if (!Subtarget->inMicroMipsMode()) |
| 171 |
Features.set(Feature_NotInMicroMipsBit); |
171 |
Features.set(Feature_NotInMicroMipsBit); |
| 172 |
if (Subtarget->isLittle()) |
172 |
if (Subtarget->isLittle()) |
| 173 |
Features.set(Feature_IsLEBit); |
173 |
Features.set(Feature_IsLEBit); |
| 174 |
if (!Subtarget->isLittle()) |
174 |
if (!Subtarget->isLittle()) |
| 175 |
Features.set(Feature_IsBEBit); |
175 |
Features.set(Feature_IsBEBit); |
| 176 |
if (!Subtarget->isTargetNaCl()) |
176 |
if (!Subtarget->isTargetNaCl()) |
| 177 |
Features.set(Feature_IsNotNaClBit); |
177 |
Features.set(Feature_IsNotNaClBit); |
| 178 |
if (Subtarget->hasEVA()) |
178 |
if (Subtarget->hasEVA()) |
| 179 |
Features.set(Feature_HasEVABit); |
179 |
Features.set(Feature_HasEVABit); |
| 180 |
if (Subtarget->hasMSA()) |
180 |
if (Subtarget->hasMSA()) |
| 181 |
Features.set(Feature_HasMSABit); |
181 |
Features.set(Feature_HasMSABit); |
| 182 |
if (!Subtarget->disableMadd4()) |
182 |
if (!Subtarget->disableMadd4()) |
| 183 |
Features.set(Feature_HasMadd4Bit); |
183 |
Features.set(Feature_HasMadd4Bit); |
| 184 |
if (Subtarget->useIndirectJumpsHazard()) |
184 |
if (Subtarget->useIndirectJumpsHazard()) |
| 185 |
Features.set(Feature_UseIndirectJumpsHazardBit); |
185 |
Features.set(Feature_UseIndirectJumpsHazardBit); |
| 186 |
if (!Subtarget->useIndirectJumpsHazard()) |
186 |
if (!Subtarget->useIndirectJumpsHazard()) |
| 187 |
Features.set(Feature_NoIndirectJumpGuardsBit); |
187 |
Features.set(Feature_NoIndirectJumpGuardsBit); |
| 188 |
if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast) |
188 |
if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast) |
| 189 |
Features.set(Feature_AllowFPOpFusionBit); |
189 |
Features.set(Feature_AllowFPOpFusionBit); |
| 190 |
if (Subtarget->isFP64bit()) |
190 |
if (Subtarget->isFP64bit()) |
| 191 |
Features.set(Feature_IsFP64bitBit); |
191 |
Features.set(Feature_IsFP64bitBit); |
| 192 |
if (!Subtarget->isFP64bit()) |
192 |
if (!Subtarget->isFP64bit()) |
| 193 |
Features.set(Feature_NotFP64bitBit); |
193 |
Features.set(Feature_NotFP64bitBit); |
| 194 |
if (!Subtarget->useSoftFloat()) |
194 |
if (!Subtarget->useSoftFloat()) |
| 195 |
Features.set(Feature_IsNotSoftFloatBit); |
195 |
Features.set(Feature_IsNotSoftFloatBit); |
| 196 |
if (Subtarget->hasDSP()) |
196 |
if (Subtarget->hasDSP()) |
| 197 |
Features.set(Feature_HasDSPBit); |
197 |
Features.set(Feature_HasDSPBit); |
| 198 |
if (Subtarget->hasDSPR2()) |
198 |
if (Subtarget->hasDSPR2()) |
| 199 |
Features.set(Feature_HasDSPR2Bit); |
199 |
Features.set(Feature_HasDSPR2Bit); |
| 200 |
return Features; |
200 |
return Features; |
| 201 |
} |
201 |
} |
| 202 |
|
202 |
|
| 203 |
void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { |
203 |
void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { |
| 204 |
AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF); |
204 |
AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF); |
| 205 |
} |
205 |
} |
| 206 |
PredicateBitset MipsInstructionSelector:: |
206 |
PredicateBitset MipsInstructionSelector:: |
| 207 |
computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const { |
207 |
computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const { |
| 208 |
PredicateBitset Features; |
208 |
PredicateBitset Features; |
| 209 |
return Features; |
209 |
return Features; |
| 210 |
} |
210 |
} |
| 211 |
|
211 |
|
| 212 |
// Feature bitsets. |
212 |
// Feature bitsets. |
| 213 |
enum { |
213 |
enum { |
| 214 |
GIFBS_Invalid, |
214 |
GIFBS_Invalid, |
| 215 |
GIFBS_HasCnMips, |
215 |
GIFBS_HasCnMips, |
| 216 |
GIFBS_HasDSP, |
216 |
GIFBS_HasDSP, |
| 217 |
GIFBS_HasDSPR2, |
217 |
GIFBS_HasDSPR2, |
| 218 |
GIFBS_HasMSA, |
218 |
GIFBS_HasMSA, |
| 219 |
GIFBS_InMicroMips, |
219 |
GIFBS_InMicroMips, |
| 220 |
GIFBS_InMips16Mode, |
220 |
GIFBS_InMips16Mode, |
| 221 |
GIFBS_IsFP64bit, |
221 |
GIFBS_IsFP64bit, |
| 222 |
GIFBS_NotFP64bit, |
222 |
GIFBS_NotFP64bit, |
| 223 |
GIFBS_HasDSP_InMicroMips, |
223 |
GIFBS_HasDSP_InMicroMips, |
| 224 |
GIFBS_HasDSP_NotInMicroMips, |
224 |
GIFBS_HasDSP_NotInMicroMips, |
| 225 |
GIFBS_HasDSPR2_InMicroMips, |
225 |
GIFBS_HasDSPR2_InMicroMips, |
| 226 |
GIFBS_HasMSA_HasStdEnc, |
226 |
GIFBS_HasMSA_HasStdEnc, |
| 227 |
GIFBS_HasMSA_IsBE, |
227 |
GIFBS_HasMSA_IsBE, |
| 228 |
GIFBS_HasMSA_IsLE, |
228 |
GIFBS_HasMSA_IsLE, |
| 229 |
GIFBS_HasMips32r6_HasStdEnc, |
229 |
GIFBS_HasMips32r6_HasStdEnc, |
| 230 |
GIFBS_HasMips32r6_InMicroMips, |
230 |
GIFBS_HasMips32r6_InMicroMips, |
| 231 |
GIFBS_HasMips64r2_HasStdEnc, |
231 |
GIFBS_HasMips64r2_HasStdEnc, |
| 232 |
GIFBS_HasMips64r6_HasStdEnc, |
232 |
GIFBS_HasMips64r6_HasStdEnc, |
| 233 |
GIFBS_HasStdEnc_IsNotSoftFloat, |
233 |
GIFBS_HasStdEnc_IsNotSoftFloat, |
| 234 |
GIFBS_HasStdEnc_NotInMicroMips, |
234 |
GIFBS_HasStdEnc_NotInMicroMips, |
| 235 |
GIFBS_HasStdEnc_NotMips4_32, |
235 |
GIFBS_HasStdEnc_NotMips4_32, |
| 236 |
GIFBS_InMicroMips_IsFP64bit, |
236 |
GIFBS_InMicroMips_IsFP64bit, |
| 237 |
GIFBS_InMicroMips_IsNotSoftFloat, |
237 |
GIFBS_InMicroMips_IsNotSoftFloat, |
| 238 |
GIFBS_InMicroMips_NotFP64bit, |
238 |
GIFBS_InMicroMips_NotFP64bit, |
| 239 |
GIFBS_InMicroMips_NotMips32r6, |
239 |
GIFBS_InMicroMips_NotMips32r6, |
| 240 |
GIFBS_IsGP64bit_NotInMips16Mode, |
240 |
GIFBS_IsGP64bit_NotInMips16Mode, |
| 241 |
GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
241 |
GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
| 242 |
GIFBS_HasMSA_HasMips64_HasStdEnc, |
242 |
GIFBS_HasMSA_HasMips64_HasStdEnc, |
| 243 |
GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
243 |
GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
| 244 |
GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
244 |
GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
| 245 |
GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips, |
245 |
GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips, |
| 246 |
GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
246 |
GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 247 |
GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
247 |
GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 248 |
GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips, |
248 |
GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips, |
| 249 |
GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
249 |
GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
| 250 |
GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips, |
250 |
GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips, |
| 251 |
GIFBS_HasStdEnc_IsFP64bit_NotMips4_32, |
251 |
GIFBS_HasStdEnc_IsFP64bit_NotMips4_32, |
| 252 |
GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
252 |
GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 253 |
GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips, |
253 |
GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips, |
| 254 |
GIFBS_HasStdEnc_NotFP64bit_NotMips4_32, |
254 |
GIFBS_HasStdEnc_NotFP64bit_NotMips4_32, |
| 255 |
GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC, |
255 |
GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC, |
| 256 |
GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
256 |
GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
| 257 |
GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
257 |
GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
| 258 |
GIFBS_InMicroMips_IsNotSoftFloat_UseAbs, |
258 |
GIFBS_InMicroMips_IsNotSoftFloat_UseAbs, |
| 259 |
GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
259 |
GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
| 260 |
GIFBS_InMicroMips_NotMips32r6_RelocNotPIC, |
260 |
GIFBS_InMicroMips_NotMips32r6_RelocNotPIC, |
| 261 |
GIFBS_InMicroMips_NotMips32r6_RelocPIC, |
261 |
GIFBS_InMicroMips_NotMips32r6_RelocPIC, |
| 262 |
GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode, |
262 |
GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode, |
| 263 |
GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode, |
263 |
GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode, |
| 264 |
GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6, |
264 |
GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6, |
| 265 |
GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
265 |
GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 266 |
GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
266 |
GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
| 267 |
GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
267 |
GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 268 |
GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
268 |
GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 269 |
GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6, |
269 |
GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6, |
| 270 |
GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips, |
270 |
GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips, |
| 271 |
GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
271 |
GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
| 272 |
GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
272 |
GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
| 273 |
GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs, |
273 |
GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs, |
| 274 |
GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6, |
274 |
GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6, |
| 275 |
GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
275 |
GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
| 276 |
GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
276 |
GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
| 277 |
GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
277 |
GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 278 |
GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
278 |
GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 279 |
GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6, |
279 |
GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6, |
| 280 |
GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs, |
280 |
GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs, |
| 281 |
GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs, |
281 |
GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs, |
| 282 |
GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
282 |
GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 283 |
GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
283 |
GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 284 |
GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
284 |
GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 285 |
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
285 |
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 286 |
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
286 |
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 287 |
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
287 |
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 288 |
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
288 |
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 289 |
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
289 |
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 290 |
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
290 |
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 291 |
}; |
291 |
}; |
| 292 |
const static PredicateBitset FeatureBitsets[] { |
292 |
const static PredicateBitset FeatureBitsets[] { |
| 293 |
{}, // GIFBS_Invalid |
293 |
{}, // GIFBS_Invalid |
| 294 |
{Feature_HasCnMipsBit, }, |
294 |
{Feature_HasCnMipsBit, }, |
| 295 |
{Feature_HasDSPBit, }, |
295 |
{Feature_HasDSPBit, }, |
| 296 |
{Feature_HasDSPR2Bit, }, |
296 |
{Feature_HasDSPR2Bit, }, |
| 297 |
{Feature_HasMSABit, }, |
297 |
{Feature_HasMSABit, }, |
| 298 |
{Feature_InMicroMipsBit, }, |
298 |
{Feature_InMicroMipsBit, }, |
| 299 |
{Feature_InMips16ModeBit, }, |
299 |
{Feature_InMips16ModeBit, }, |
| 300 |
{Feature_IsFP64bitBit, }, |
300 |
{Feature_IsFP64bitBit, }, |
| 301 |
{Feature_NotFP64bitBit, }, |
301 |
{Feature_NotFP64bitBit, }, |
| 302 |
{Feature_HasDSPBit, Feature_InMicroMipsBit, }, |
302 |
{Feature_HasDSPBit, Feature_InMicroMipsBit, }, |
| 303 |
{Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, |
303 |
{Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, |
| 304 |
{Feature_HasDSPR2Bit, Feature_InMicroMipsBit, }, |
304 |
{Feature_HasDSPR2Bit, Feature_InMicroMipsBit, }, |
| 305 |
{Feature_HasMSABit, Feature_HasStdEncBit, }, |
305 |
{Feature_HasMSABit, Feature_HasStdEncBit, }, |
| 306 |
{Feature_HasMSABit, Feature_IsBEBit, }, |
306 |
{Feature_HasMSABit, Feature_IsBEBit, }, |
| 307 |
{Feature_HasMSABit, Feature_IsLEBit, }, |
307 |
{Feature_HasMSABit, Feature_IsLEBit, }, |
| 308 |
{Feature_HasMips32r6Bit, Feature_HasStdEncBit, }, |
308 |
{Feature_HasMips32r6Bit, Feature_HasStdEncBit, }, |
| 309 |
{Feature_HasMips32r6Bit, Feature_InMicroMipsBit, }, |
309 |
{Feature_HasMips32r6Bit, Feature_InMicroMipsBit, }, |
| 310 |
{Feature_HasMips64r2Bit, Feature_HasStdEncBit, }, |
310 |
{Feature_HasMips64r2Bit, Feature_HasStdEncBit, }, |
| 311 |
{Feature_HasMips64r6Bit, Feature_HasStdEncBit, }, |
311 |
{Feature_HasMips64r6Bit, Feature_HasStdEncBit, }, |
| 312 |
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, |
312 |
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, |
| 313 |
{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
313 |
{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
| 314 |
{Feature_HasStdEncBit, Feature_NotMips4_32Bit, }, |
314 |
{Feature_HasStdEncBit, Feature_NotMips4_32Bit, }, |
| 315 |
{Feature_InMicroMipsBit, Feature_IsFP64bitBit, }, |
315 |
{Feature_InMicroMipsBit, Feature_IsFP64bitBit, }, |
| 316 |
{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, |
316 |
{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, |
| 317 |
{Feature_InMicroMipsBit, Feature_NotFP64bitBit, }, |
317 |
{Feature_InMicroMipsBit, Feature_NotFP64bitBit, }, |
| 318 |
{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, |
318 |
{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, |
| 319 |
{Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, }, |
319 |
{Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, }, |
| 320 |
{Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, }, |
320 |
{Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, }, |
| 321 |
{Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, }, |
321 |
{Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, }, |
| 322 |
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, }, |
322 |
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, }, |
| 323 |
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
323 |
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
| 324 |
{Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
324 |
{Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
| 325 |
{Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
325 |
{Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
| 326 |
{Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, |
326 |
{Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, |
| 327 |
{Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
327 |
{Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
| 328 |
{Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
328 |
{Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
| 329 |
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, }, |
329 |
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, }, |
| 330 |
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, }, |
330 |
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, }, |
| 331 |
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
331 |
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 332 |
{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, }, |
332 |
{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, }, |
| 333 |
{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, }, |
333 |
{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, }, |
| 334 |
{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, }, |
334 |
{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, }, |
| 335 |
{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
335 |
{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| 336 |
{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, }, |
336 |
{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, }, |
| 337 |
{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_UseAbsBit, }, |
337 |
{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_UseAbsBit, }, |
| 338 |
{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, }, |
338 |
{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, }, |
| 339 |
{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, }, |
339 |
{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, }, |
| 340 |
{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, }, |
340 |
{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, }, |
| 341 |
{Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, }, |
341 |
{Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, }, |
| 342 |
{Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, }, |
342 |
{Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, }, |
| 343 |
{Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, }, |
343 |
{Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, }, |
| 344 |
{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
344 |
{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 345 |
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, |
345 |
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, |
| 346 |
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
346 |
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 347 |
{Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
347 |
{Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 348 |
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
348 |
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 349 |
{Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, |
349 |
{Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, |
| 350 |
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
350 |
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 351 |
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, }, |
351 |
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, }, |
| 352 |
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, }, |
352 |
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, }, |
| 353 |
{Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, }, |
353 |
{Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, }, |
| 354 |
{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
354 |
{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| 355 |
{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, }, |
355 |
{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, }, |
| 356 |
{Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
356 |
{Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 357 |
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
357 |
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 358 |
{Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, }, |
358 |
{Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, }, |
| 359 |
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, }, |
359 |
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, }, |
| 360 |
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, }, |
360 |
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, }, |
| 361 |
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
361 |
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 362 |
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
362 |
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 363 |
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
363 |
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 364 |
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
364 |
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 365 |
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
365 |
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 366 |
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
366 |
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 367 |
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
367 |
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 368 |
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
368 |
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 369 |
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
369 |
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| 370 |
}; |
370 |
}; |
| 371 |
|
371 |
|
| 372 |
// ComplexPattern predicates. |
372 |
// ComplexPattern predicates. |
| 373 |
enum { |
373 |
enum { |
| 374 |
GICP_Invalid, |
374 |
GICP_Invalid, |
| 375 |
}; |
375 |
}; |
| 376 |
// See constructor for table contents |
376 |
// See constructor for table contents |
| 377 |
|
377 |
|
| 378 |
MipsInstructionSelector::ComplexMatcherMemFn |
378 |
MipsInstructionSelector::ComplexMatcherMemFn |
| 379 |
MipsInstructionSelector::ComplexPredicateFns[] = { |
379 |
MipsInstructionSelector::ComplexPredicateFns[] = { |
| 380 |
nullptr, // GICP_Invalid |
380 |
nullptr, // GICP_Invalid |
| 381 |
}; |
381 |
}; |
| 382 |
|
382 |
|
| 383 |
// PatFrag predicates. |
383 |
// PatFrag predicates. |
| 384 |
bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const { |
384 |
bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const { |
| 385 |
const MachineFunction &MF = *MI.getParent()->getParent(); |
385 |
const MachineFunction &MF = *MI.getParent()->getParent(); |
| 386 |
const MachineRegisterInfo &MRI = MF.getRegInfo(); |
386 |
const MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 387 |
const auto &Operands = State.RecordedOperands; |
387 |
const auto &Operands = State.RecordedOperands; |
| 388 |
(void)Operands; |
388 |
(void)Operands; |
| 389 |
(void)MRI; |
389 |
(void)MRI; |
| 390 |
llvm_unreachable("Unknown predicate"); |
390 |
llvm_unreachable("Unknown predicate"); |
| 391 |
return false; |
391 |
return false; |
| 392 |
} |
392 |
} |
| 393 |
// PatFrag predicates. |
393 |
// PatFrag predicates. |
| 394 |
enum { |
394 |
enum { |
| 395 |
GICXXPred_I64_Predicate_immLi16 = GICXXPred_Invalid + 1, |
395 |
GICXXPred_I64_Predicate_immLi16 = GICXXPred_Invalid + 1, |
| 396 |
GICXXPred_I64_Predicate_immSExt6, |
396 |
GICXXPred_I64_Predicate_immSExt6, |
| 397 |
GICXXPred_I64_Predicate_immSExt10, |
397 |
GICXXPred_I64_Predicate_immSExt10, |
| 398 |
GICXXPred_I64_Predicate_immSExtAddiur2, |
398 |
GICXXPred_I64_Predicate_immSExtAddiur2, |
| 399 |
GICXXPred_I64_Predicate_immSExtAddius5, |
399 |
GICXXPred_I64_Predicate_immSExtAddius5, |
| 400 |
GICXXPred_I64_Predicate_immZExt1, |
400 |
GICXXPred_I64_Predicate_immZExt1, |
| 401 |
GICXXPred_I64_Predicate_immZExt1Ptr, |
401 |
GICXXPred_I64_Predicate_immZExt1Ptr, |
| 402 |
GICXXPred_I64_Predicate_immZExt2, |
402 |
GICXXPred_I64_Predicate_immZExt2, |
| 403 |
GICXXPred_I64_Predicate_immZExt2Lsa, |
403 |
GICXXPred_I64_Predicate_immZExt2Lsa, |
| 404 |
GICXXPred_I64_Predicate_immZExt2Ptr, |
404 |
GICXXPred_I64_Predicate_immZExt2Ptr, |
| 405 |
GICXXPred_I64_Predicate_immZExt2Shift, |
405 |
GICXXPred_I64_Predicate_immZExt2Shift, |
| 406 |
GICXXPred_I64_Predicate_immZExt3, |
406 |
GICXXPred_I64_Predicate_immZExt3, |
| 407 |
GICXXPred_I64_Predicate_immZExt3Ptr, |
407 |
GICXXPred_I64_Predicate_immZExt3Ptr, |
| 408 |
GICXXPred_I64_Predicate_immZExt4, |
408 |
GICXXPred_I64_Predicate_immZExt4, |
| 409 |
GICXXPred_I64_Predicate_immZExt4Ptr, |
409 |
GICXXPred_I64_Predicate_immZExt4Ptr, |
| 410 |
GICXXPred_I64_Predicate_immZExt5, |
410 |
GICXXPred_I64_Predicate_immZExt5, |
| 411 |
GICXXPred_I64_Predicate_immZExt5_64, |
411 |
GICXXPred_I64_Predicate_immZExt5_64, |
| 412 |
GICXXPred_I64_Predicate_immZExt6, |
412 |
GICXXPred_I64_Predicate_immZExt6, |
| 413 |
GICXXPred_I64_Predicate_immZExt8, |
413 |
GICXXPred_I64_Predicate_immZExt8, |
| 414 |
GICXXPred_I64_Predicate_immZExt10, |
414 |
GICXXPred_I64_Predicate_immZExt10, |
| 415 |
GICXXPred_I64_Predicate_immZExtAndi16, |
415 |
GICXXPred_I64_Predicate_immZExtAndi16, |
| 416 |
GICXXPred_I64_Predicate_immi32Cst7, |
416 |
GICXXPred_I64_Predicate_immi32Cst7, |
| 417 |
GICXXPred_I64_Predicate_immi32Cst15, |
417 |
GICXXPred_I64_Predicate_immi32Cst15, |
| 418 |
GICXXPred_I64_Predicate_immi32Cst31, |
418 |
GICXXPred_I64_Predicate_immi32Cst31, |
| 419 |
GICXXPred_I64_Predicate_timmSExt6, |
419 |
GICXXPred_I64_Predicate_timmSExt6, |
| 420 |
GICXXPred_I64_Predicate_timmZExt1, |
420 |
GICXXPred_I64_Predicate_timmZExt1, |
| 421 |
GICXXPred_I64_Predicate_timmZExt1Ptr, |
421 |
GICXXPred_I64_Predicate_timmZExt1Ptr, |
| 422 |
GICXXPred_I64_Predicate_timmZExt2, |
422 |
GICXXPred_I64_Predicate_timmZExt2, |
| 423 |
GICXXPred_I64_Predicate_timmZExt2Ptr, |
423 |
GICXXPred_I64_Predicate_timmZExt2Ptr, |
| 424 |
GICXXPred_I64_Predicate_timmZExt3, |
424 |
GICXXPred_I64_Predicate_timmZExt3, |
| 425 |
GICXXPred_I64_Predicate_timmZExt3Ptr, |
425 |
GICXXPred_I64_Predicate_timmZExt3Ptr, |
| 426 |
GICXXPred_I64_Predicate_timmZExt4, |
426 |
GICXXPred_I64_Predicate_timmZExt4, |
| 427 |
GICXXPred_I64_Predicate_timmZExt4Ptr, |
427 |
GICXXPred_I64_Predicate_timmZExt4Ptr, |
| 428 |
GICXXPred_I64_Predicate_timmZExt5, |
428 |
GICXXPred_I64_Predicate_timmZExt5, |
| 429 |
GICXXPred_I64_Predicate_timmZExt6, |
429 |
GICXXPred_I64_Predicate_timmZExt6, |
| 430 |
GICXXPred_I64_Predicate_timmZExt8, |
430 |
GICXXPred_I64_Predicate_timmZExt8, |
| 431 |
GICXXPred_I64_Predicate_timmZExt10, |
431 |
GICXXPred_I64_Predicate_timmZExt10, |
| 432 |
}; |
432 |
}; |
| 433 |
bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { |
433 |
bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { |
| 434 |
switch (PredicateID) { |
434 |
switch (PredicateID) { |
| 435 |
case GICXXPred_I64_Predicate_immLi16: { |
435 |
case GICXXPred_I64_Predicate_immLi16: { |
| 436 |
return Imm >= -1 && Imm <= 126; |
436 |
return Imm >= -1 && Imm <= 126; |
| 437 |
} |
437 |
} |
| 438 |
case GICXXPred_I64_Predicate_immSExt6: { |
438 |
case GICXXPred_I64_Predicate_immSExt6: { |
| 439 |
return isInt<6>(Imm); |
439 |
return isInt<6>(Imm); |
| 440 |
} |
440 |
} |
| 441 |
case GICXXPred_I64_Predicate_immSExt10: { |
441 |
case GICXXPred_I64_Predicate_immSExt10: { |
| 442 |
return isInt<10>(Imm); |
442 |
return isInt<10>(Imm); |
| 443 |
} |
443 |
} |
| 444 |
case GICXXPred_I64_Predicate_immSExtAddiur2: { |
444 |
case GICXXPred_I64_Predicate_immSExtAddiur2: { |
| 445 |
return Imm == 1 || Imm == -1 || |
445 |
return Imm == 1 || Imm == -1 || |
| 446 |
((Imm % 4 == 0) && |
446 |
((Imm % 4 == 0) && |
| 447 |
Imm < 28 && Imm > 0); |
447 |
Imm < 28 && Imm > 0); |
| 448 |
} |
448 |
} |
| 449 |
case GICXXPred_I64_Predicate_immSExtAddius5: { |
449 |
case GICXXPred_I64_Predicate_immSExtAddius5: { |
| 450 |
return Imm >= -8 && Imm <= 7; |
450 |
return Imm >= -8 && Imm <= 7; |
| 451 |
} |
451 |
} |
| 452 |
case GICXXPred_I64_Predicate_immZExt1: { |
452 |
case GICXXPred_I64_Predicate_immZExt1: { |
| 453 |
return isUInt<1>(Imm); |
453 |
return isUInt<1>(Imm); |
| 454 |
} |
454 |
} |
| 455 |
case GICXXPred_I64_Predicate_immZExt1Ptr: { |
455 |
case GICXXPred_I64_Predicate_immZExt1Ptr: { |
| 456 |
return isUInt<1>(Imm); |
456 |
return isUInt<1>(Imm); |
| 457 |
} |
457 |
} |
| 458 |
case GICXXPred_I64_Predicate_immZExt2: { |
458 |
case GICXXPred_I64_Predicate_immZExt2: { |
| 459 |
return isUInt<2>(Imm); |
459 |
return isUInt<2>(Imm); |
| 460 |
} |
460 |
} |
| 461 |
case GICXXPred_I64_Predicate_immZExt2Lsa: { |
461 |
case GICXXPred_I64_Predicate_immZExt2Lsa: { |
| 462 |
return isUInt<2>(Imm - 1); |
462 |
return isUInt<2>(Imm - 1); |
| 463 |
} |
463 |
} |
| 464 |
case GICXXPred_I64_Predicate_immZExt2Ptr: { |
464 |
case GICXXPred_I64_Predicate_immZExt2Ptr: { |
| 465 |
return isUInt<2>(Imm); |
465 |
return isUInt<2>(Imm); |
| 466 |
} |
466 |
} |
| 467 |
case GICXXPred_I64_Predicate_immZExt2Shift: { |
467 |
case GICXXPred_I64_Predicate_immZExt2Shift: { |
| 468 |
return Imm >= 1 && Imm <= 8; |
468 |
return Imm >= 1 && Imm <= 8; |
| 469 |
} |
469 |
} |
| 470 |
case GICXXPred_I64_Predicate_immZExt3: { |
470 |
case GICXXPred_I64_Predicate_immZExt3: { |
| 471 |
return isUInt<3>(Imm); |
471 |
return isUInt<3>(Imm); |
| 472 |
} |
472 |
} |
| 473 |
case GICXXPred_I64_Predicate_immZExt3Ptr: { |
473 |
case GICXXPred_I64_Predicate_immZExt3Ptr: { |
| 474 |
return isUInt<3>(Imm); |
474 |
return isUInt<3>(Imm); |
| 475 |
} |
475 |
} |
| 476 |
case GICXXPred_I64_Predicate_immZExt4: { |
476 |
case GICXXPred_I64_Predicate_immZExt4: { |
| 477 |
return isUInt<4>(Imm); |
477 |
return isUInt<4>(Imm); |
| 478 |
} |
478 |
} |
| 479 |
case GICXXPred_I64_Predicate_immZExt4Ptr: { |
479 |
case GICXXPred_I64_Predicate_immZExt4Ptr: { |
| 480 |
return isUInt<4>(Imm); |
480 |
return isUInt<4>(Imm); |
| 481 |
} |
481 |
} |
| 482 |
case GICXXPred_I64_Predicate_immZExt5: { |
482 |
case GICXXPred_I64_Predicate_immZExt5: { |
| 483 |
return Imm == (Imm & 0x1f); |
483 |
return Imm == (Imm & 0x1f); |
| 484 |
} |
484 |
} |
| 485 |
case GICXXPred_I64_Predicate_immZExt5_64: { |
485 |
case GICXXPred_I64_Predicate_immZExt5_64: { |
| 486 |
return Imm == (Imm & 0x1f); |
486 |
return Imm == (Imm & 0x1f); |
| 487 |
} |
487 |
} |
| 488 |
case GICXXPred_I64_Predicate_immZExt6: { |
488 |
case GICXXPred_I64_Predicate_immZExt6: { |
| 489 |
return Imm == (Imm & 0x3f); |
489 |
return Imm == (Imm & 0x3f); |
| 490 |
} |
490 |
} |
| 491 |
case GICXXPred_I64_Predicate_immZExt8: { |
491 |
case GICXXPred_I64_Predicate_immZExt8: { |
| 492 |
return isUInt<8>(Imm); |
492 |
return isUInt<8>(Imm); |
| 493 |
} |
493 |
} |
| 494 |
case GICXXPred_I64_Predicate_immZExt10: { |
494 |
case GICXXPred_I64_Predicate_immZExt10: { |
| 495 |
return isUInt<10>(Imm); |
495 |
return isUInt<10>(Imm); |
| 496 |
} |
496 |
} |
| 497 |
case GICXXPred_I64_Predicate_immZExtAndi16: { |
497 |
case GICXXPred_I64_Predicate_immZExtAndi16: { |
| 498 |
return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 || |
498 |
return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 || |
| 499 |
Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 || |
499 |
Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 || |
| 500 |
Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 ); |
500 |
Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 ); |
| 501 |
} |
501 |
} |
| 502 |
case GICXXPred_I64_Predicate_immi32Cst7: { |
502 |
case GICXXPred_I64_Predicate_immi32Cst7: { |
| 503 |
return isUInt<32>(Imm) && Imm == 7; |
503 |
return isUInt<32>(Imm) && Imm == 7; |
| 504 |
} |
504 |
} |
| 505 |
case GICXXPred_I64_Predicate_immi32Cst15: { |
505 |
case GICXXPred_I64_Predicate_immi32Cst15: { |
| 506 |
return isUInt<32>(Imm) && Imm == 15; |
506 |
return isUInt<32>(Imm) && Imm == 15; |
| 507 |
} |
507 |
} |
| 508 |
case GICXXPred_I64_Predicate_immi32Cst31: { |
508 |
case GICXXPred_I64_Predicate_immi32Cst31: { |
| 509 |
return isUInt<32>(Imm) && Imm == 31; |
509 |
return isUInt<32>(Imm) && Imm == 31; |
| 510 |
} |
510 |
} |
| 511 |
case GICXXPred_I64_Predicate_timmSExt6: { |
511 |
case GICXXPred_I64_Predicate_timmSExt6: { |
| 512 |
return isInt<6>(Imm); |
512 |
return isInt<6>(Imm); |
| 513 |
} |
513 |
} |
| 514 |
case GICXXPred_I64_Predicate_timmZExt1: { |
514 |
case GICXXPred_I64_Predicate_timmZExt1: { |
| 515 |
return isUInt<1>(Imm); |
515 |
return isUInt<1>(Imm); |
| 516 |
} |
516 |
} |
| 517 |
case GICXXPred_I64_Predicate_timmZExt1Ptr: { |
517 |
case GICXXPred_I64_Predicate_timmZExt1Ptr: { |
| 518 |
return isUInt<1>(Imm); |
518 |
return isUInt<1>(Imm); |
| 519 |
} |
519 |
} |
| 520 |
case GICXXPred_I64_Predicate_timmZExt2: { |
520 |
case GICXXPred_I64_Predicate_timmZExt2: { |
| 521 |
return isUInt<2>(Imm); |
521 |
return isUInt<2>(Imm); |
| 522 |
} |
522 |
} |
| 523 |
case GICXXPred_I64_Predicate_timmZExt2Ptr: { |
523 |
case GICXXPred_I64_Predicate_timmZExt2Ptr: { |
| 524 |
return isUInt<2>(Imm); |
524 |
return isUInt<2>(Imm); |
| 525 |
} |
525 |
} |
| 526 |
case GICXXPred_I64_Predicate_timmZExt3: { |
526 |
case GICXXPred_I64_Predicate_timmZExt3: { |
| 527 |
return isUInt<3>(Imm); |
527 |
return isUInt<3>(Imm); |
| 528 |
} |
528 |
} |
| 529 |
case GICXXPred_I64_Predicate_timmZExt3Ptr: { |
529 |
case GICXXPred_I64_Predicate_timmZExt3Ptr: { |
| 530 |
return isUInt<3>(Imm); |
530 |
return isUInt<3>(Imm); |
| 531 |
} |
531 |
} |
| 532 |
case GICXXPred_I64_Predicate_timmZExt4: { |
532 |
case GICXXPred_I64_Predicate_timmZExt4: { |
| 533 |
return isUInt<4>(Imm); |
533 |
return isUInt<4>(Imm); |
| 534 |
} |
534 |
} |
| 535 |
case GICXXPred_I64_Predicate_timmZExt4Ptr: { |
535 |
case GICXXPred_I64_Predicate_timmZExt4Ptr: { |
| 536 |
return isUInt<4>(Imm); |
536 |
return isUInt<4>(Imm); |
| 537 |
} |
537 |
} |
| 538 |
case GICXXPred_I64_Predicate_timmZExt5: { |
538 |
case GICXXPred_I64_Predicate_timmZExt5: { |
| 539 |
return Imm == (Imm & 0x1f); |
539 |
return Imm == (Imm & 0x1f); |
| 540 |
} |
540 |
} |
| 541 |
case GICXXPred_I64_Predicate_timmZExt6: { |
541 |
case GICXXPred_I64_Predicate_timmZExt6: { |
| 542 |
return Imm == (Imm & 0x3f); |
542 |
return Imm == (Imm & 0x3f); |
| 543 |
} |
543 |
} |
| 544 |
case GICXXPred_I64_Predicate_timmZExt8: { |
544 |
case GICXXPred_I64_Predicate_timmZExt8: { |
| 545 |
return isUInt<8>(Imm); |
545 |
return isUInt<8>(Imm); |
| 546 |
} |
546 |
} |
| 547 |
case GICXXPred_I64_Predicate_timmZExt10: { |
547 |
case GICXXPred_I64_Predicate_timmZExt10: { |
| 548 |
return isUInt<10>(Imm); |
548 |
return isUInt<10>(Imm); |
| 549 |
} |
549 |
} |
| 550 |
} |
550 |
} |
| 551 |
llvm_unreachable("Unknown predicate"); |
551 |
llvm_unreachable("Unknown predicate"); |
| 552 |
return false; |
552 |
return false; |
| 553 |
} |
553 |
} |
| 554 |
// PatFrag predicates. |
554 |
// PatFrag predicates. |
| 555 |
bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { |
555 |
bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { |
| 556 |
llvm_unreachable("Unknown predicate"); |
556 |
llvm_unreachable("Unknown predicate"); |
| 557 |
return false; |
557 |
return false; |
| 558 |
} |
558 |
} |
| 559 |
// PatFrag predicates. |
559 |
// PatFrag predicates. |
| 560 |
enum { |
560 |
enum { |
| 561 |
GICXXPred_APInt_Predicate_imm32SExt16 = GICXXPred_Invalid + 1, |
561 |
GICXXPred_APInt_Predicate_imm32SExt16 = GICXXPred_Invalid + 1, |
| 562 |
GICXXPred_APInt_Predicate_imm32ZExt16, |
562 |
GICXXPred_APInt_Predicate_imm32ZExt16, |
| 563 |
}; |
563 |
}; |
| 564 |
bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { |
564 |
bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { |
| 565 |
switch (PredicateID) { |
565 |
switch (PredicateID) { |
| 566 |
case GICXXPred_APInt_Predicate_imm32SExt16: { |
566 |
case GICXXPred_APInt_Predicate_imm32SExt16: { |
| 567 |
return isInt<16>(Imm.getSExtValue()); |
567 |
return isInt<16>(Imm.getSExtValue()); |
| 568 |
} |
568 |
} |
| 569 |
case GICXXPred_APInt_Predicate_imm32ZExt16: { |
569 |
case GICXXPred_APInt_Predicate_imm32ZExt16: { |
| 570 |
|
570 |
|
| 571 |
return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue(); |
571 |
return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue(); |
| 572 |
|
572 |
|
| 573 |
} |
573 |
} |
| 574 |
} |
574 |
} |
| 575 |
llvm_unreachable("Unknown predicate"); |
575 |
llvm_unreachable("Unknown predicate"); |
| 576 |
return false; |
576 |
return false; |
| 577 |
} |
577 |
} |
| 578 |
bool MipsInstructionSelector::testSimplePredicate(unsigned) const { |
578 |
bool MipsInstructionSelector::testSimplePredicate(unsigned) const { |
| 579 |
llvm_unreachable("MipsInstructionSelector does not support simple predicates!"); |
579 |
llvm_unreachable("MipsInstructionSelector does not support simple predicates!"); |
| 580 |
return false; |
580 |
return false; |
| 581 |
} |
581 |
} |
| 582 |
// Custom renderers. |
582 |
// Custom renderers. |
| 583 |
enum { |
583 |
enum { |
| 584 |
GICR_Invalid, |
584 |
GICR_Invalid, |
| 585 |
}; |
585 |
}; |
| 586 |
MipsInstructionSelector::CustomRendererFn |
586 |
MipsInstructionSelector::CustomRendererFn |
| 587 |
MipsInstructionSelector::CustomRenderers[] = { |
587 |
MipsInstructionSelector::CustomRenderers[] = { |
| 588 |
nullptr, // GICR_Invalid |
588 |
nullptr, // GICR_Invalid |
| 589 |
}; |
589 |
}; |
| 590 |
|
590 |
|
| 591 |
bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { |
591 |
bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { |
| 592 |
const PredicateBitset AvailableFeatures = getAvailableFeatures(); |
592 |
const PredicateBitset AvailableFeatures = getAvailableFeatures(); |
| 593 |
NewMIVector OutMIs; |
593 |
NewMIVector OutMIs; |
| 594 |
State.MIs.clear(); |
594 |
State.MIs.clear(); |
| 595 |
State.MIs.push_back(&I); |
595 |
State.MIs.push_back(&I); |
| 596 |
|
596 |
|
| 597 |
if (executeMatchTable(*this, OutMIs, State, ExecInfo, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) { |
597 |
if (executeMatchTable(*this, OutMIs, State, ExecInfo, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) { |
| 598 |
return true; |
598 |
return true; |
| 599 |
} |
599 |
} |
| 600 |
|
600 |
|
| 601 |
return false; |
601 |
return false; |
| 602 |
} |
602 |
} |
| 603 |
|
603 |
|
| 604 |
void MipsInstructionSelector::runCustomAction(unsigned, const MatcherState&) const { |
604 |
void MipsInstructionSelector::runCustomAction(unsigned, const MatcherState&) const { |
| 605 |
llvm_unreachable("MipsInstructionSelector does not support custom C++ actions!"); |
605 |
llvm_unreachable("MipsInstructionSelector does not support custom C++ actions!"); |
| 606 |
} |
606 |
} |
| 607 |
const int64_t *MipsInstructionSelector::getMatchTable() const { |
607 |
const int64_t *MipsInstructionSelector::getMatchTable() const { |
| 608 |
constexpr static int64_t MatchTable0[] = { |
608 |
constexpr static int64_t MatchTable0[] = { |
| 609 |
GIM_SwitchOpcode, /*MI*/0, /*[*/46, 219, /*)*//*default:*//*Label 58*/ 60451, |
609 |
GIM_SwitchOpcode, /*MI*/0, /*[*/46, 219, /*)*//*default:*//*Label 58*/ 60451, |
| 610 |
/*TargetOpcode::G_ADD*//*Label 0*/ 178, |
610 |
/*TargetOpcode::G_ADD*//*Label 0*/ 178, |
| 611 |
/*TargetOpcode::G_SUB*//*Label 1*/ 1398, |
611 |
/*TargetOpcode::G_SUB*//*Label 1*/ 1398, |
| 612 |
/*TargetOpcode::G_MUL*//*Label 2*/ 2010, |
612 |
/*TargetOpcode::G_MUL*//*Label 2*/ 2010, |
| 613 |
/*TargetOpcode::G_SDIV*//*Label 3*/ 2386, |
613 |
/*TargetOpcode::G_SDIV*//*Label 3*/ 2386, |
| 614 |
/*TargetOpcode::G_UDIV*//*Label 4*/ 2607, |
614 |
/*TargetOpcode::G_UDIV*//*Label 4*/ 2607, |
| 615 |
/*TargetOpcode::G_SREM*//*Label 5*/ 2828, |
615 |
/*TargetOpcode::G_SREM*//*Label 5*/ 2828, |
| 616 |
/*TargetOpcode::G_UREM*//*Label 6*/ 3049, 0, 0, |
616 |
/*TargetOpcode::G_UREM*//*Label 6*/ 3049, 0, 0, |
| 617 |
/*TargetOpcode::G_AND*//*Label 7*/ 3270, |
617 |
/*TargetOpcode::G_AND*//*Label 7*/ 3270, |
| 618 |
/*TargetOpcode::G_OR*//*Label 8*/ 3757, |
618 |
/*TargetOpcode::G_OR*//*Label 8*/ 3757, |
| 619 |
/*TargetOpcode::G_XOR*//*Label 9*/ 4102, 0, 0, 0, 0, 0, 0, 0, 0, |
619 |
/*TargetOpcode::G_XOR*//*Label 9*/ 4102, 0, 0, 0, 0, 0, 0, 0, 0, |
| 620 |
/*TargetOpcode::G_MERGE_VALUES*//*Label 10*/ 4942, |
620 |
/*TargetOpcode::G_MERGE_VALUES*//*Label 10*/ 4942, |
| 621 |
/*TargetOpcode::G_BUILD_VECTOR*//*Label 11*/ 5007, 0, 0, 0, 0, |
621 |
/*TargetOpcode::G_BUILD_VECTOR*//*Label 11*/ 5007, 0, 0, 0, 0, |
| 622 |
/*TargetOpcode::G_BITCAST*//*Label 12*/ 5368, 0, 0, 0, 0, 0, 0, 0, 0, |
622 |
/*TargetOpcode::G_BITCAST*//*Label 12*/ 5368, 0, 0, 0, 0, 0, 0, 0, 0, |
| 623 |
/*TargetOpcode::G_LOAD*//*Label 13*/ 9021, |
623 |
/*TargetOpcode::G_LOAD*//*Label 13*/ 9021, |
| 624 |
/*TargetOpcode::G_SEXTLOAD*//*Label 14*/ 9087, |
624 |
/*TargetOpcode::G_SEXTLOAD*//*Label 14*/ 9087, |
| 625 |
/*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ 9153, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
625 |
/*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ 9153, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 626 |
/*TargetOpcode::G_INTRINSIC*//*Label 16*/ 9219, |
626 |
/*TargetOpcode::G_INTRINSIC*//*Label 16*/ 9219, |
| 627 |
/*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 17*/ 25494, |
627 |
/*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 17*/ 25494, |
| 628 |
/*TargetOpcode::G_ANYEXT*//*Label 18*/ 30478, |
628 |
/*TargetOpcode::G_ANYEXT*//*Label 18*/ 30478, |
| 629 |
/*TargetOpcode::G_TRUNC*//*Label 19*/ 30544, |
629 |
/*TargetOpcode::G_TRUNC*//*Label 19*/ 30544, |
| 630 |
/*TargetOpcode::G_CONSTANT*//*Label 20*/ 30607, 0, 0, 0, |
630 |
/*TargetOpcode::G_CONSTANT*//*Label 20*/ 30607, 0, 0, 0, |
| 631 |
/*TargetOpcode::G_SEXT*//*Label 21*/ 30667, 0, |
631 |
/*TargetOpcode::G_SEXT*//*Label 21*/ 30667, 0, |
| 632 |
/*TargetOpcode::G_ZEXT*//*Label 22*/ 31925, |
632 |
/*TargetOpcode::G_ZEXT*//*Label 22*/ 31925, |
| 633 |
/*TargetOpcode::G_SHL*//*Label 23*/ 32119, |
633 |
/*TargetOpcode::G_SHL*//*Label 23*/ 32119, |
| 634 |
/*TargetOpcode::G_LSHR*//*Label 24*/ 33872, |
634 |
/*TargetOpcode::G_LSHR*//*Label 24*/ 33872, |
| 635 |
/*TargetOpcode::G_ASHR*//*Label 25*/ 35625, 0, 0, |
635 |
/*TargetOpcode::G_ASHR*//*Label 25*/ 35625, 0, 0, |
| 636 |
/*TargetOpcode::G_ROTR*//*Label 26*/ 37335, 0, |
636 |
/*TargetOpcode::G_ROTR*//*Label 26*/ 37335, 0, |
| 637 |
/*TargetOpcode::G_ICMP*//*Label 27*/ 37598, |
637 |
/*TargetOpcode::G_ICMP*//*Label 27*/ 37598, |
| 638 |
/*TargetOpcode::G_FCMP*//*Label 28*/ 40102, |
638 |
/*TargetOpcode::G_FCMP*//*Label 28*/ 40102, |
| 639 |
/*TargetOpcode::G_SELECT*//*Label 29*/ 41822, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
639 |
/*TargetOpcode::G_SELECT*//*Label 29*/ 41822, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 640 |
/*TargetOpcode::G_UMULH*//*Label 30*/ 54102, |
640 |
/*TargetOpcode::G_UMULH*//*Label 30*/ 54102, |
| 641 |
/*TargetOpcode::G_SMULH*//*Label 31*/ 54189, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
641 |
/*TargetOpcode::G_SMULH*//*Label 31*/ 54189, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 642 |
/*TargetOpcode::G_FADD*//*Label 32*/ 54276, |
642 |
/*TargetOpcode::G_FADD*//*Label 32*/ 54276, |
| 643 |
/*TargetOpcode::G_FSUB*//*Label 33*/ 55155, |
643 |
/*TargetOpcode::G_FSUB*//*Label 33*/ 55155, |
| 644 |
/*TargetOpcode::G_FMUL*//*Label 34*/ 55731, |
644 |
/*TargetOpcode::G_FMUL*//*Label 34*/ 55731, |
| 645 |
/*TargetOpcode::G_FMA*//*Label 35*/ 56168, 0, |
645 |
/*TargetOpcode::G_FMA*//*Label 35*/ 56168, 0, |
| 646 |
/*TargetOpcode::G_FDIV*//*Label 36*/ 56258, 0, 0, 0, 0, |
646 |
/*TargetOpcode::G_FDIV*//*Label 36*/ 56258, 0, 0, 0, 0, |
| 647 |
/*TargetOpcode::G_FEXP2*//*Label 37*/ 56509, 0, |
647 |
/*TargetOpcode::G_FEXP2*//*Label 37*/ 56509, 0, |
| 648 |
/*TargetOpcode::G_FLOG2*//*Label 38*/ 56567, 0, 0, 0, |
648 |
/*TargetOpcode::G_FLOG2*//*Label 38*/ 56567, 0, 0, 0, |
| 649 |
/*TargetOpcode::G_FNEG*//*Label 39*/ 56625, |
649 |
/*TargetOpcode::G_FNEG*//*Label 39*/ 56625, |
| 650 |
/*TargetOpcode::G_FPEXT*//*Label 40*/ 57921, |
650 |
/*TargetOpcode::G_FPEXT*//*Label 40*/ 57921, |
| 651 |
/*TargetOpcode::G_FPTRUNC*//*Label 41*/ 58070, |
651 |
/*TargetOpcode::G_FPTRUNC*//*Label 41*/ 58070, |
| 652 |
/*TargetOpcode::G_FPTOSI*//*Label 42*/ 58198, |
652 |
/*TargetOpcode::G_FPTOSI*//*Label 42*/ 58198, |
| 653 |
/*TargetOpcode::G_FPTOUI*//*Label 43*/ 58256, |
653 |
/*TargetOpcode::G_FPTOUI*//*Label 43*/ 58256, |
| 654 |
/*TargetOpcode::G_SITOFP*//*Label 44*/ 58314, |
654 |
/*TargetOpcode::G_SITOFP*//*Label 44*/ 58314, |
| 655 |
/*TargetOpcode::G_UITOFP*//*Label 45*/ 58522, |
655 |
/*TargetOpcode::G_UITOFP*//*Label 45*/ 58522, |
| 656 |
/*TargetOpcode::G_FABS*//*Label 46*/ 58580, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
656 |
/*TargetOpcode::G_FABS*//*Label 46*/ 58580, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 657 |
/*TargetOpcode::G_SMIN*//*Label 47*/ 58763, |
657 |
/*TargetOpcode::G_SMIN*//*Label 47*/ 58763, |
| 658 |
/*TargetOpcode::G_SMAX*//*Label 48*/ 58903, |
658 |
/*TargetOpcode::G_SMAX*//*Label 48*/ 58903, |
| 659 |
/*TargetOpcode::G_UMIN*//*Label 49*/ 59043, |
659 |
/*TargetOpcode::G_UMIN*//*Label 49*/ 59043, |
| 660 |
/*TargetOpcode::G_UMAX*//*Label 50*/ 59183, 0, 0, 0, |
660 |
/*TargetOpcode::G_UMAX*//*Label 50*/ 59183, 0, 0, 0, |
| 661 |
/*TargetOpcode::G_BR*//*Label 51*/ 59323, 0, 0, |
661 |
/*TargetOpcode::G_BR*//*Label 51*/ 59323, 0, 0, |
| 662 |
/*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 52*/ 59408, 0, 0, 0, |
662 |
/*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 52*/ 59408, 0, 0, 0, |
| 663 |
/*TargetOpcode::G_CTLZ*//*Label 53*/ 59464, 0, |
663 |
/*TargetOpcode::G_CTLZ*//*Label 53*/ 59464, 0, |
| 664 |
/*TargetOpcode::G_CTPOP*//*Label 54*/ 59899, |
664 |
/*TargetOpcode::G_CTPOP*//*Label 54*/ 59899, |
| 665 |
/*TargetOpcode::G_BSWAP*//*Label 55*/ 60058, 0, 0, 0, 0, |
665 |
/*TargetOpcode::G_BSWAP*//*Label 55*/ 60058, 0, 0, 0, 0, |
| 666 |
/*TargetOpcode::G_FSQRT*//*Label 56*/ 60210, 0, |
666 |
/*TargetOpcode::G_FSQRT*//*Label 56*/ 60210, 0, |
| 667 |
/*TargetOpcode::G_FRINT*//*Label 57*/ 60393, |
667 |
/*TargetOpcode::G_FRINT*//*Label 57*/ 60393, |
| 668 |
// Label 0: @178 |
668 |
// Label 0: @178 |
| 669 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 67*/ 1397, |
669 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 67*/ 1397, |
| 670 |
/*GILLT_s32*//*Label 59*/ 192, |
670 |
/*GILLT_s32*//*Label 59*/ 192, |
| 671 |
/*GILLT_s64*//*Label 60*/ 584, |
671 |
/*GILLT_s64*//*Label 60*/ 584, |
| 672 |
/*GILLT_v2s16*//*Label 61*/ 747, |
672 |
/*GILLT_v2s16*//*Label 61*/ 747, |
| 673 |
/*GILLT_v2s64*//*Label 62*/ 774, |
673 |
/*GILLT_v2s64*//*Label 62*/ 774, |
| 674 |
/*GILLT_v4s8*//*Label 63*/ 923, |
674 |
/*GILLT_v4s8*//*Label 63*/ 923, |
| 675 |
/*GILLT_v4s32*//*Label 64*/ 950, |
675 |
/*GILLT_v4s32*//*Label 64*/ 950, |
| 676 |
/*GILLT_v8s16*//*Label 65*/ 1099, |
676 |
/*GILLT_v8s16*//*Label 65*/ 1099, |
| 677 |
/*GILLT_v16s8*//*Label 66*/ 1248, |
677 |
/*GILLT_v16s8*//*Label 66*/ 1248, |
| 678 |
// Label 59: @192 |
678 |
// Label 59: @192 |
| 679 |
GIM_Try, /*On fail goto*//*Label 68*/ 583, |
679 |
GIM_Try, /*On fail goto*//*Label 68*/ 583, |
| 680 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
680 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 681 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
681 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 682 |
GIM_Try, /*On fail goto*//*Label 69*/ 270, // Rule ID 2348 // |
682 |
GIM_Try, /*On fail goto*//*Label 69*/ 270, // Rule ID 2348 // |
| 683 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
683 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 684 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
684 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 685 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
685 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 686 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, |
686 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, |
| 687 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
687 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 688 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
688 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 689 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
689 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 690 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
690 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 691 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
691 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 692 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt2Lsa, |
692 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt2Lsa, |
| 693 |
// MIs[2] Operand 1 |
693 |
// MIs[2] Operand 1 |
| 694 |
// No operand predicates |
694 |
// No operand predicates |
| 695 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
695 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 696 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
696 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 697 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
697 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 698 |
// (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$sa), GPR32Opnd:{ *:[i32] }:$rt) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa) |
698 |
// (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$sa), GPR32Opnd:{ *:[i32] }:$rt) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa) |
| 699 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA, |
699 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA, |
| 700 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
700 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 701 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
701 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 702 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
702 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 703 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa |
703 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa |
| 704 |
GIR_EraseFromParent, /*InsnID*/0, |
704 |
GIR_EraseFromParent, /*InsnID*/0, |
| 705 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
705 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 706 |
// GIR_Coverage, 2348, |
706 |
// GIR_Coverage, 2348, |
| 707 |
GIR_Done, |
707 |
GIR_Done, |
| 708 |
// Label 69: @270 |
708 |
// Label 69: @270 |
| 709 |
GIM_Try, /*On fail goto*//*Label 70*/ 338, // Rule ID 822 // |
709 |
GIM_Try, /*On fail goto*//*Label 70*/ 338, // Rule ID 822 // |
| 710 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
710 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 711 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
711 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 712 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
712 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 713 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
713 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 714 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, |
714 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, |
| 715 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
715 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 716 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
716 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 717 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
717 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 718 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
718 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 719 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
719 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 720 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt2Lsa, |
720 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt2Lsa, |
| 721 |
// MIs[2] Operand 1 |
721 |
// MIs[2] Operand 1 |
| 722 |
// No operand predicates |
722 |
// No operand predicates |
| 723 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
723 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 724 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
724 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 725 |
// (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$sa)) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa) |
725 |
// (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$sa)) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa) |
| 726 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA, |
726 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA, |
| 727 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
727 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 728 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
728 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 729 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
729 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 730 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa |
730 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa |
| 731 |
GIR_EraseFromParent, /*InsnID*/0, |
731 |
GIR_EraseFromParent, /*InsnID*/0, |
| 732 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
732 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 733 |
// GIR_Coverage, 822, |
733 |
// GIR_Coverage, 822, |
| 734 |
GIR_Done, |
734 |
GIR_Done, |
| 735 |
// Label 70: @338 |
735 |
// Label 70: @338 |
| 736 |
GIM_Try, /*On fail goto*//*Label 71*/ 381, // Rule ID 40 // |
736 |
GIM_Try, /*On fail goto*//*Label 71*/ 381, // Rule ID 40 // |
| 737 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
737 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 738 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
738 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 739 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
739 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 740 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
740 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 741 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
741 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 742 |
GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_APInt_Predicate_imm32SExt16, |
742 |
GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_APInt_Predicate_imm32SExt16, |
| 743 |
// MIs[1] Operand 1 |
743 |
// MIs[1] Operand 1 |
| 744 |
// No operand predicates |
744 |
// No operand predicates |
| 745 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
745 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 746 |
// (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$imm16) => (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16) |
746 |
// (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$imm16) => (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16) |
| 747 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDiu, |
747 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDiu, |
| 748 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
748 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 749 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
749 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 750 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
750 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 751 |
GIR_EraseFromParent, /*InsnID*/0, |
751 |
GIR_EraseFromParent, /*InsnID*/0, |
| 752 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
752 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 753 |
// GIR_Coverage, 40, |
753 |
// GIR_Coverage, 40, |
| 754 |
GIR_Done, |
754 |
GIR_Done, |
| 755 |
// Label 71: @381 |
755 |
// Label 71: @381 |
| 756 |
GIM_Try, /*On fail goto*//*Label 72*/ 424, // Rule ID 2123 // |
756 |
GIM_Try, /*On fail goto*//*Label 72*/ 424, // Rule ID 2123 // |
| 757 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
757 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 759 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
759 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 760 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
760 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 761 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
761 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 762 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immSExtAddiur2, |
762 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immSExtAddiur2, |
| 763 |
// MIs[1] Operand 1 |
763 |
// MIs[1] Operand 1 |
| 764 |
// No operand predicates |
764 |
// No operand predicates |
| 765 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
765 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 766 |
// (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
766 |
// (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
| 767 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM, |
767 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM, |
| 768 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
768 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 769 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
769 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 770 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
770 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 771 |
GIR_EraseFromParent, /*InsnID*/0, |
771 |
GIR_EraseFromParent, /*InsnID*/0, |
| 772 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
772 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 773 |
// GIR_Coverage, 2123, |
773 |
// GIR_Coverage, 2123, |
| 774 |
GIR_Done, |
774 |
GIR_Done, |
| 775 |
// Label 72: @424 |
775 |
// Label 72: @424 |
| 776 |
GIM_Try, /*On fail goto*//*Label 73*/ 467, // Rule ID 2124 // |
776 |
GIM_Try, /*On fail goto*//*Label 73*/ 467, // Rule ID 2124 // |
| 777 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
777 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 779 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
779 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 780 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
780 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 781 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
781 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 782 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immSExtAddius5, |
782 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immSExtAddius5, |
| 783 |
// MIs[1] Operand 1 |
783 |
// MIs[1] Operand 1 |
| 784 |
// No operand predicates |
784 |
// No operand predicates |
| 785 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
785 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 786 |
// (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
786 |
// (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
| 787 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM, |
787 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM, |
| 788 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
788 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 790 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
790 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 791 |
GIR_EraseFromParent, /*InsnID*/0, |
791 |
GIR_EraseFromParent, /*InsnID*/0, |
| 792 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
792 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 793 |
// GIR_Coverage, 2124, |
793 |
// GIR_Coverage, 2124, |
| 794 |
GIR_Done, |
794 |
GIR_Done, |
| 795 |
// Label 73: @467 |
795 |
// Label 73: @467 |
| 796 |
GIM_Try, /*On fail goto*//*Label 74*/ 490, // Rule ID 1196 // |
796 |
GIM_Try, /*On fail goto*//*Label 74*/ 490, // Rule ID 1196 // |
| 797 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
797 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 798 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
798 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 799 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
799 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 800 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
800 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
| 801 |
// (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
801 |
// (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
| 802 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MMR6, |
802 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MMR6, |
| 803 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
803 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 804 |
// GIR_Coverage, 1196, |
804 |
// GIR_Coverage, 1196, |
| 805 |
GIR_Done, |
805 |
GIR_Done, |
| 806 |
// Label 74: @490 |
806 |
// Label 74: @490 |
| 807 |
GIM_Try, /*On fail goto*//*Label 75*/ 513, // Rule ID 46 // |
807 |
GIM_Try, /*On fail goto*//*Label 75*/ 513, // Rule ID 46 // |
| 808 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
808 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 809 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
809 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 810 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
810 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 811 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
811 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 812 |
// (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
812 |
// (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 813 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu, |
813 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu, |
| 814 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
814 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 815 |
// GIR_Coverage, 46, |
815 |
// GIR_Coverage, 46, |
| 816 |
GIR_Done, |
816 |
GIR_Done, |
| 817 |
// Label 75: @513 |
817 |
// Label 75: @513 |
| 818 |
GIM_Try, /*On fail goto*//*Label 76*/ 536, // Rule ID 1048 // |
818 |
GIM_Try, /*On fail goto*//*Label 76*/ 536, // Rule ID 1048 // |
| 819 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
819 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 820 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
820 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 821 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
821 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 822 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
822 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
| 823 |
// (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
823 |
// (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
| 824 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MM, |
824 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MM, |
| 825 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
825 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 826 |
// GIR_Coverage, 1048, |
826 |
// GIR_Coverage, 1048, |
| 827 |
GIR_Done, |
827 |
GIR_Done, |
| 828 |
// Label 76: @536 |
828 |
// Label 76: @536 |
| 829 |
GIM_Try, /*On fail goto*//*Label 77*/ 559, // Rule ID 1060 // |
829 |
GIM_Try, /*On fail goto*//*Label 77*/ 559, // Rule ID 1060 // |
| 830 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
830 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 831 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
831 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 832 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
832 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 833 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
833 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 834 |
// (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
834 |
// (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 835 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu_MM, |
835 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu_MM, |
| 836 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
836 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 837 |
// GIR_Coverage, 1060, |
837 |
// GIR_Coverage, 1060, |
| 838 |
GIR_Done, |
838 |
GIR_Done, |
| 839 |
// Label 77: @559 |
839 |
// Label 77: @559 |
| 840 |
GIM_Try, /*On fail goto*//*Label 78*/ 582, // Rule ID 1783 // |
840 |
GIM_Try, /*On fail goto*//*Label 78*/ 582, // Rule ID 1783 // |
| 841 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
841 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 843 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
843 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 844 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
844 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 845 |
// (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) |
845 |
// (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) |
| 846 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AdduRxRyRz16, |
846 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AdduRxRyRz16, |
| 847 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
847 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 848 |
// GIR_Coverage, 1783, |
848 |
// GIR_Coverage, 1783, |
| 849 |
GIR_Done, |
849 |
GIR_Done, |
| 850 |
// Label 78: @582 |
850 |
// Label 78: @582 |
| 851 |
GIM_Reject, |
851 |
GIM_Reject, |
| 852 |
// Label 68: @583 |
852 |
// Label 68: @583 |
| 853 |
GIM_Reject, |
853 |
GIM_Reject, |
| 854 |
// Label 60: @584 |
854 |
// Label 60: @584 |
| 855 |
GIM_Try, /*On fail goto*//*Label 79*/ 746, |
855 |
GIM_Try, /*On fail goto*//*Label 79*/ 746, |
| 856 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
856 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 857 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
857 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 858 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
858 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 859 |
GIM_Try, /*On fail goto*//*Label 80*/ 662, // Rule ID 2349 // |
859 |
GIM_Try, /*On fail goto*//*Label 80*/ 662, // Rule ID 2349 // |
| 860 |
GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc, |
860 |
GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc, |
| 861 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
861 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 862 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, |
862 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, |
| 863 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
863 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 864 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
864 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 865 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
865 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 866 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
866 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 867 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
867 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 868 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt2Lsa, |
868 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt2Lsa, |
| 869 |
// MIs[2] Operand 1 |
869 |
// MIs[2] Operand 1 |
| 870 |
// No operand predicates |
870 |
// No operand predicates |
| 871 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
871 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 872 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
872 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 873 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
873 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 874 |
// (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<>:$sa), GPR64Opnd:{ *:[i64] }:$rt) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa) |
874 |
// (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<>:$sa), GPR64Opnd:{ *:[i64] }:$rt) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa) |
| 875 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA, |
875 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA, |
| 876 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
876 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 877 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
877 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 878 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
878 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 879 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa |
879 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa |
| 880 |
GIR_EraseFromParent, /*InsnID*/0, |
880 |
GIR_EraseFromParent, /*InsnID*/0, |
| 881 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
881 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 882 |
// GIR_Coverage, 2349, |
882 |
// GIR_Coverage, 2349, |
| 883 |
GIR_Done, |
883 |
GIR_Done, |
| 884 |
// Label 80: @662 |
884 |
// Label 80: @662 |
| 885 |
GIM_Try, /*On fail goto*//*Label 81*/ 726, // Rule ID 823 // |
885 |
GIM_Try, /*On fail goto*//*Label 81*/ 726, // Rule ID 823 // |
| 886 |
GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc, |
886 |
GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc, |
| 887 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
887 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 888 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
888 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 889 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, |
889 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, |
| 890 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
890 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 891 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
891 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 892 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
892 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 893 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
893 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 894 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
894 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 895 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt2Lsa, |
895 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt2Lsa, |
| 896 |
// MIs[2] Operand 1 |
896 |
// MIs[2] Operand 1 |
| 897 |
// No operand predicates |
897 |
// No operand predicates |
| 898 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
898 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 899 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
899 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 900 |
// (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<>:$sa)) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa) |
900 |
// (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<>:$sa)) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa) |
| 901 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA, |
901 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA, |
| 902 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
902 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 903 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
903 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 904 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
904 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 905 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa |
905 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa |
| 906 |
GIR_EraseFromParent, /*InsnID*/0, |
906 |
GIR_EraseFromParent, /*InsnID*/0, |
| 907 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
907 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 908 |
// GIR_Coverage, 823, |
908 |
// GIR_Coverage, 823, |
| 909 |
GIR_Done, |
909 |
GIR_Done, |
| 910 |
// Label 81: @726 |
910 |
// Label 81: @726 |
| 911 |
GIM_Try, /*On fail goto*//*Label 82*/ 745, // Rule ID 196 // |
911 |
GIM_Try, /*On fail goto*//*Label 82*/ 745, // Rule ID 196 // |
| 912 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
912 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
| 913 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
913 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 914 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
914 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 915 |
// (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
915 |
// (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 916 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu, |
916 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu, |
| 917 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
917 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 918 |
// GIR_Coverage, 196, |
918 |
// GIR_Coverage, 196, |
| 919 |
GIR_Done, |
919 |
GIR_Done, |
| 920 |
// Label 82: @745 |
920 |
// Label 82: @745 |
| 921 |
GIM_Reject, |
921 |
GIM_Reject, |
| 922 |
// Label 79: @746 |
922 |
// Label 79: @746 |
| 923 |
GIM_Reject, |
923 |
GIM_Reject, |
| 924 |
// Label 61: @747 |
924 |
// Label 61: @747 |
| 925 |
GIM_Try, /*On fail goto*//*Label 83*/ 773, // Rule ID 1882 // |
925 |
GIM_Try, /*On fail goto*//*Label 83*/ 773, // Rule ID 1882 // |
| 926 |
GIM_CheckFeatures, GIFBS_HasDSP, |
926 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 927 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
927 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
| 928 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
928 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 929 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
929 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 930 |
// (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) |
930 |
// (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) |
| 931 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDQ_PH, |
931 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDQ_PH, |
| 932 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20, |
932 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20, |
| 933 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
933 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 934 |
// GIR_Coverage, 1882, |
934 |
// GIR_Coverage, 1882, |
| 935 |
GIR_Done, |
935 |
GIR_Done, |
| 936 |
// Label 83: @773 |
936 |
// Label 83: @773 |
| 937 |
GIM_Reject, |
937 |
GIM_Reject, |
| 938 |
// Label 62: @774 |
938 |
// Label 62: @774 |
| 939 |
GIM_Try, /*On fail goto*//*Label 84*/ 922, |
939 |
GIM_Try, /*On fail goto*//*Label 84*/ 922, |
| 940 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
940 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 941 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
941 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 942 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
942 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 943 |
GIM_Try, /*On fail goto*//*Label 85*/ 845, // Rule ID 2353 // |
943 |
GIM_Try, /*On fail goto*//*Label 85*/ 845, // Rule ID 2353 // |
| 944 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
944 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 945 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
945 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 946 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
946 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 947 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
947 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 948 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
948 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 949 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
949 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 950 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
950 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 951 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
951 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 952 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
952 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 953 |
// (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
953 |
// (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 954 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D, |
954 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D, |
| 955 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
955 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 956 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
956 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 957 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
957 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 958 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
958 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 959 |
GIR_EraseFromParent, /*InsnID*/0, |
959 |
GIR_EraseFromParent, /*InsnID*/0, |
| 960 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
960 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 961 |
// GIR_Coverage, 2353, |
961 |
// GIR_Coverage, 2353, |
| 962 |
GIR_Done, |
962 |
GIR_Done, |
| 963 |
// Label 85: @845 |
963 |
// Label 85: @845 |
| 964 |
GIM_Try, /*On fail goto*//*Label 86*/ 902, // Rule ID 831 // |
964 |
GIM_Try, /*On fail goto*//*Label 86*/ 902, // Rule ID 831 // |
| 965 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
965 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 966 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
966 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 967 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
967 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 968 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
968 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 969 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
969 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 970 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
970 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 971 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
971 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 972 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
972 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 973 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
973 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 974 |
// (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
974 |
// (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 975 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D, |
975 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D, |
| 976 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
976 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 977 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
977 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
| 978 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
978 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 979 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
979 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 980 |
GIR_EraseFromParent, /*InsnID*/0, |
980 |
GIR_EraseFromParent, /*InsnID*/0, |
| 981 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
981 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 982 |
// GIR_Coverage, 831, |
982 |
// GIR_Coverage, 831, |
| 983 |
GIR_Done, |
983 |
GIR_Done, |
| 984 |
// Label 86: @902 |
984 |
// Label 86: @902 |
| 985 |
GIM_Try, /*On fail goto*//*Label 87*/ 921, // Rule ID 498 // |
985 |
GIM_Try, /*On fail goto*//*Label 87*/ 921, // Rule ID 498 // |
| 986 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
986 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 987 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
987 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 988 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
988 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 989 |
// (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
989 |
// (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 990 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_D, |
990 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_D, |
| 991 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
991 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 992 |
// GIR_Coverage, 498, |
992 |
// GIR_Coverage, 498, |
| 993 |
GIR_Done, |
993 |
GIR_Done, |
| 994 |
// Label 87: @921 |
994 |
// Label 87: @921 |
| 995 |
GIM_Reject, |
995 |
GIM_Reject, |
| 996 |
// Label 84: @922 |
996 |
// Label 84: @922 |
| 997 |
GIM_Reject, |
997 |
GIM_Reject, |
| 998 |
// Label 63: @923 |
998 |
// Label 63: @923 |
| 999 |
GIM_Try, /*On fail goto*//*Label 88*/ 949, // Rule ID 1888 // |
999 |
GIM_Try, /*On fail goto*//*Label 88*/ 949, // Rule ID 1888 // |
| 1000 |
GIM_CheckFeatures, GIFBS_HasDSP, |
1000 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 1001 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
1001 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
| 1002 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
1002 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 1003 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
1003 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 1004 |
// (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) |
1004 |
// (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) |
| 1005 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU_QB, |
1005 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU_QB, |
| 1006 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20, |
1006 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20, |
| 1007 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1007 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1008 |
// GIR_Coverage, 1888, |
1008 |
// GIR_Coverage, 1888, |
| 1009 |
GIR_Done, |
1009 |
GIR_Done, |
| 1010 |
// Label 88: @949 |
1010 |
// Label 88: @949 |
| 1011 |
GIM_Reject, |
1011 |
GIM_Reject, |
| 1012 |
// Label 64: @950 |
1012 |
// Label 64: @950 |
| 1013 |
GIM_Try, /*On fail goto*//*Label 89*/ 1098, |
1013 |
GIM_Try, /*On fail goto*//*Label 89*/ 1098, |
| 1014 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
1014 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1015 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
1015 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
1016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 1017 |
GIM_Try, /*On fail goto*//*Label 90*/ 1021, // Rule ID 2352 // |
1017 |
GIM_Try, /*On fail goto*//*Label 90*/ 1021, // Rule ID 2352 // |
| 1018 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1018 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1019 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
1019 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1020 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
1020 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1021 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
1021 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1022 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
1022 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1023 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
1023 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 1024 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
1024 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 1025 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
1025 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 1026 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
1026 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1027 |
// (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
1027 |
// (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 1028 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W, |
1028 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W, |
| 1029 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
1029 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 1030 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
1030 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 1031 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
1031 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 1032 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
1032 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 1033 |
GIR_EraseFromParent, /*InsnID*/0, |
1033 |
GIR_EraseFromParent, /*InsnID*/0, |
| 1034 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1034 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1035 |
// GIR_Coverage, 2352, |
1035 |
// GIR_Coverage, 2352, |
| 1036 |
GIR_Done, |
1036 |
GIR_Done, |
| 1037 |
// Label 90: @1021 |
1037 |
// Label 90: @1021 |
| 1038 |
GIM_Try, /*On fail goto*//*Label 91*/ 1078, // Rule ID 830 // |
1038 |
GIM_Try, /*On fail goto*//*Label 91*/ 1078, // Rule ID 830 // |
| 1039 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1039 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1040 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
1040 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 1041 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
1041 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1042 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
1042 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1043 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
1043 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1044 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
1044 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1045 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
1045 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 1046 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
1046 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 1047 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
1047 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1048 |
// (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
1048 |
// (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 1049 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W, |
1049 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W, |
| 1050 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
1050 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 1051 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
1051 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
| 1052 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
1052 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 1053 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
1053 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 1054 |
GIR_EraseFromParent, /*InsnID*/0, |
1054 |
GIR_EraseFromParent, /*InsnID*/0, |
| 1055 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1055 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1056 |
// GIR_Coverage, 830, |
1056 |
// GIR_Coverage, 830, |
| 1057 |
GIR_Done, |
1057 |
GIR_Done, |
| 1058 |
// Label 91: @1078 |
1058 |
// Label 91: @1078 |
| 1059 |
GIM_Try, /*On fail goto*//*Label 92*/ 1097, // Rule ID 497 // |
1059 |
GIM_Try, /*On fail goto*//*Label 92*/ 1097, // Rule ID 497 // |
| 1060 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1060 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1061 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
1061 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 1062 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
1062 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 1063 |
// (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
1063 |
// (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 1064 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_W, |
1064 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_W, |
| 1065 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1065 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1066 |
// GIR_Coverage, 497, |
1066 |
// GIR_Coverage, 497, |
| 1067 |
GIR_Done, |
1067 |
GIR_Done, |
| 1068 |
// Label 92: @1097 |
1068 |
// Label 92: @1097 |
| 1069 |
GIM_Reject, |
1069 |
GIM_Reject, |
| 1070 |
// Label 89: @1098 |
1070 |
// Label 89: @1098 |
| 1071 |
GIM_Reject, |
1071 |
GIM_Reject, |
| 1072 |
// Label 65: @1099 |
1072 |
// Label 65: @1099 |
| 1073 |
GIM_Try, /*On fail goto*//*Label 93*/ 1247, |
1073 |
GIM_Try, /*On fail goto*//*Label 93*/ 1247, |
| 1074 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
1074 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 1075 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
1075 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 1076 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
1076 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 1077 |
GIM_Try, /*On fail goto*//*Label 94*/ 1170, // Rule ID 2351 // |
1077 |
GIM_Try, /*On fail goto*//*Label 94*/ 1170, // Rule ID 2351 // |
| 1078 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1078 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1079 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
1079 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1080 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
1080 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1081 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
1081 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 1082 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
1082 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 1083 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
1083 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 1084 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
1084 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 1085 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
1085 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 1086 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
1086 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1087 |
// (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
1087 |
// (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 1088 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H, |
1088 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H, |
| 1089 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
1089 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 1090 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
1090 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 1091 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
1091 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 1092 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
1092 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 1093 |
GIR_EraseFromParent, /*InsnID*/0, |
1093 |
GIR_EraseFromParent, /*InsnID*/0, |
| 1094 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1094 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1095 |
// GIR_Coverage, 2351, |
1095 |
// GIR_Coverage, 2351, |
| 1096 |
GIR_Done, |
1096 |
GIR_Done, |
| 1097 |
// Label 94: @1170 |
1097 |
// Label 94: @1170 |
| 1098 |
GIM_Try, /*On fail goto*//*Label 95*/ 1227, // Rule ID 829 // |
1098 |
GIM_Try, /*On fail goto*//*Label 95*/ 1227, // Rule ID 829 // |
| 1099 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1099 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1100 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
1100 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 1101 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
1101 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1102 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
1102 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1103 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
1103 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 1104 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
1104 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 1105 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
1105 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 1106 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
1106 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 1107 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
1107 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1108 |
// (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
1108 |
// (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 1109 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H, |
1109 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H, |
| 1110 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
1110 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 1111 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
1111 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
| 1112 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
1112 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 1113 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
1113 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 1114 |
GIR_EraseFromParent, /*InsnID*/0, |
1114 |
GIR_EraseFromParent, /*InsnID*/0, |
| 1115 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1115 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1116 |
// GIR_Coverage, 829, |
1116 |
// GIR_Coverage, 829, |
| 1117 |
GIR_Done, |
1117 |
GIR_Done, |
| 1118 |
// Label 95: @1227 |
1118 |
// Label 95: @1227 |
| 1119 |
GIM_Try, /*On fail goto*//*Label 96*/ 1246, // Rule ID 496 // |
1119 |
GIM_Try, /*On fail goto*//*Label 96*/ 1246, // Rule ID 496 // |
| 1120 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1120 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1121 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
1121 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 1122 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
1122 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 1123 |
// (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
1123 |
// (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 1124 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_H, |
1124 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_H, |
| 1125 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1125 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1126 |
// GIR_Coverage, 496, |
1126 |
// GIR_Coverage, 496, |
| 1127 |
GIR_Done, |
1127 |
GIR_Done, |
| 1128 |
// Label 96: @1246 |
1128 |
// Label 96: @1246 |
| 1129 |
GIM_Reject, |
1129 |
GIM_Reject, |
| 1130 |
// Label 93: @1247 |
1130 |
// Label 93: @1247 |
| 1131 |
GIM_Reject, |
1131 |
GIM_Reject, |
| 1132 |
// Label 66: @1248 |
1132 |
// Label 66: @1248 |
| 1133 |
GIM_Try, /*On fail goto*//*Label 97*/ 1396, |
1133 |
GIM_Try, /*On fail goto*//*Label 97*/ 1396, |
| 1134 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
1134 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 1135 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
1135 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 1136 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
1136 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 1137 |
GIM_Try, /*On fail goto*//*Label 98*/ 1319, // Rule ID 2350 // |
1137 |
GIM_Try, /*On fail goto*//*Label 98*/ 1319, // Rule ID 2350 // |
| 1138 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1138 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1139 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
1139 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1140 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
1140 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1141 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
1141 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 1142 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
1142 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 1143 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
1143 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 1144 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
1144 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 1145 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
1145 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 1146 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
1146 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1147 |
// (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
1147 |
// (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 1148 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B, |
1148 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B, |
| 1149 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
1149 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 1150 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
1150 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 1151 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
1151 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 1152 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
1152 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 1153 |
GIR_EraseFromParent, /*InsnID*/0, |
1153 |
GIR_EraseFromParent, /*InsnID*/0, |
| 1154 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1154 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1155 |
// GIR_Coverage, 2350, |
1155 |
// GIR_Coverage, 2350, |
| 1156 |
GIR_Done, |
1156 |
GIR_Done, |
| 1157 |
// Label 98: @1319 |
1157 |
// Label 98: @1319 |
| 1158 |
GIM_Try, /*On fail goto*//*Label 99*/ 1376, // Rule ID 828 // |
1158 |
GIM_Try, /*On fail goto*//*Label 99*/ 1376, // Rule ID 828 // |
| 1159 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1159 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1160 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
1160 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 1161 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
1161 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1162 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
1162 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1163 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
1163 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 1164 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
1164 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 1165 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
1165 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 1166 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
1166 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 1167 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
1167 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1168 |
// (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
1168 |
// (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 1169 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B, |
1169 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B, |
| 1170 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
1170 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 1171 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
1171 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
| 1172 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
1172 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 1173 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
1173 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 1174 |
GIR_EraseFromParent, /*InsnID*/0, |
1174 |
GIR_EraseFromParent, /*InsnID*/0, |
| 1175 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1175 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1176 |
// GIR_Coverage, 828, |
1176 |
// GIR_Coverage, 828, |
| 1177 |
GIR_Done, |
1177 |
GIR_Done, |
| 1178 |
// Label 99: @1376 |
1178 |
// Label 99: @1376 |
| 1179 |
GIM_Try, /*On fail goto*//*Label 100*/ 1395, // Rule ID 495 // |
1179 |
GIM_Try, /*On fail goto*//*Label 100*/ 1395, // Rule ID 495 // |
| 1180 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1180 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1181 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
1181 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 1182 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
1182 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 1183 |
// (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
1183 |
// (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 1184 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_B, |
1184 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_B, |
| 1185 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1185 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1186 |
// GIR_Coverage, 495, |
1186 |
// GIR_Coverage, 495, |
| 1187 |
GIR_Done, |
1187 |
GIR_Done, |
| 1188 |
// Label 100: @1395 |
1188 |
// Label 100: @1395 |
| 1189 |
GIM_Reject, |
1189 |
GIM_Reject, |
| 1190 |
// Label 97: @1396 |
1190 |
// Label 97: @1396 |
| 1191 |
GIM_Reject, |
1191 |
GIM_Reject, |
| 1192 |
// Label 67: @1397 |
1192 |
// Label 67: @1397 |
| 1193 |
GIM_Reject, |
1193 |
GIM_Reject, |
| 1194 |
// Label 1: @1398 |
1194 |
// Label 1: @1398 |
| 1195 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 109*/ 2009, |
1195 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 109*/ 2009, |
| 1196 |
/*GILLT_s32*//*Label 101*/ 1412, |
1196 |
/*GILLT_s32*//*Label 101*/ 1412, |
| 1197 |
/*GILLT_s64*//*Label 102*/ 1571, |
1197 |
/*GILLT_s64*//*Label 102*/ 1571, |
| 1198 |
/*GILLT_v2s16*//*Label 103*/ 1603, |
1198 |
/*GILLT_v2s16*//*Label 103*/ 1603, |
| 1199 |
/*GILLT_v2s64*//*Label 104*/ 1630, |
1199 |
/*GILLT_v2s64*//*Label 104*/ 1630, |
| 1200 |
/*GILLT_v4s8*//*Label 105*/ 1718, |
1200 |
/*GILLT_v4s8*//*Label 105*/ 1718, |
| 1201 |
/*GILLT_v4s32*//*Label 106*/ 1745, |
1201 |
/*GILLT_v4s32*//*Label 106*/ 1745, |
| 1202 |
/*GILLT_v8s16*//*Label 107*/ 1833, |
1202 |
/*GILLT_v8s16*//*Label 107*/ 1833, |
| 1203 |
/*GILLT_v16s8*//*Label 108*/ 1921, |
1203 |
/*GILLT_v16s8*//*Label 108*/ 1921, |
| 1204 |
// Label 101: @1412 |
1204 |
// Label 101: @1412 |
| 1205 |
GIM_Try, /*On fail goto*//*Label 110*/ 1570, |
1205 |
GIM_Try, /*On fail goto*//*Label 110*/ 1570, |
| 1206 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
1206 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 1207 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
1207 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 1208 |
GIM_Try, /*On fail goto*//*Label 111*/ 1454, // Rule ID 1782 // |
1208 |
GIM_Try, /*On fail goto*//*Label 111*/ 1454, // Rule ID 1782 // |
| 1209 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
1209 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 1210 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
1210 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 1211 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, |
1211 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, |
| 1212 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
1212 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 1213 |
// (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) => (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r) |
1213 |
// (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) => (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r) |
| 1214 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16, |
1214 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16, |
| 1215 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx |
1215 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx |
| 1216 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // r |
1216 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // r |
| 1217 |
GIR_EraseFromParent, /*InsnID*/0, |
1217 |
GIR_EraseFromParent, /*InsnID*/0, |
| 1218 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1218 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1219 |
// GIR_Coverage, 1782, |
1219 |
// GIR_Coverage, 1782, |
| 1220 |
GIR_Done, |
1220 |
GIR_Done, |
| 1221 |
// Label 111: @1454 |
1221 |
// Label 111: @1454 |
| 1222 |
GIM_Try, /*On fail goto*//*Label 112*/ 1477, // Rule ID 1198 // |
1222 |
GIM_Try, /*On fail goto*//*Label 112*/ 1477, // Rule ID 1198 // |
| 1223 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
1223 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 1224 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
1224 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 1225 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
1225 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 1226 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
1226 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
| 1227 |
// (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
1227 |
// (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
| 1228 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MMR6, |
1228 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MMR6, |
| 1229 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1229 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1230 |
// GIR_Coverage, 1198, |
1230 |
// GIR_Coverage, 1198, |
| 1231 |
GIR_Done, |
1231 |
GIR_Done, |
| 1232 |
// Label 112: @1477 |
1232 |
// Label 112: @1477 |
| 1233 |
GIM_Try, /*On fail goto*//*Label 113*/ 1500, // Rule ID 47 // |
1233 |
GIM_Try, /*On fail goto*//*Label 113*/ 1500, // Rule ID 47 // |
| 1234 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
1234 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 1235 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
1235 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 1236 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
1236 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 1237 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
1237 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 1238 |
// (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
1238 |
// (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 1239 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu, |
1239 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu, |
| 1240 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1240 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1241 |
// GIR_Coverage, 47, |
1241 |
// GIR_Coverage, 47, |
| 1242 |
GIR_Done, |
1242 |
GIR_Done, |
| 1243 |
// Label 113: @1500 |
1243 |
// Label 113: @1500 |
| 1244 |
GIM_Try, /*On fail goto*//*Label 114*/ 1523, // Rule ID 1052 // |
1244 |
GIM_Try, /*On fail goto*//*Label 114*/ 1523, // Rule ID 1052 // |
| 1245 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
1245 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 1246 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
1246 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 1247 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
1247 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 1248 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
1248 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
| 1249 |
// (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
1249 |
// (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
| 1250 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MM, |
1250 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MM, |
| 1251 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1251 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1252 |
// GIR_Coverage, 1052, |
1252 |
// GIR_Coverage, 1052, |
| 1253 |
GIR_Done, |
1253 |
GIR_Done, |
| 1254 |
// Label 114: @1523 |
1254 |
// Label 114: @1523 |
| 1255 |
GIM_Try, /*On fail goto*//*Label 115*/ 1546, // Rule ID 1061 // |
1255 |
GIM_Try, /*On fail goto*//*Label 115*/ 1546, // Rule ID 1061 // |
| 1256 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
1256 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 1257 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
1257 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 1258 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
1258 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 1259 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
1259 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 1260 |
// (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
1260 |
// (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 1261 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu_MM, |
1261 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu_MM, |
| 1262 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1262 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1263 |
// GIR_Coverage, 1061, |
1263 |
// GIR_Coverage, 1061, |
| 1264 |
GIR_Done, |
1264 |
GIR_Done, |
| 1265 |
// Label 115: @1546 |
1265 |
// Label 115: @1546 |
| 1266 |
GIM_Try, /*On fail goto*//*Label 116*/ 1569, // Rule ID 1787 // |
1266 |
GIM_Try, /*On fail goto*//*Label 116*/ 1569, // Rule ID 1787 // |
| 1267 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
1267 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 1268 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
1268 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 1269 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
1269 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 1270 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
1270 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 1271 |
// (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) |
1271 |
// (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) |
| 1272 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SubuRxRyRz16, |
1272 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SubuRxRyRz16, |
| 1273 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1273 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1274 |
// GIR_Coverage, 1787, |
1274 |
// GIR_Coverage, 1787, |
| 1275 |
GIR_Done, |
1275 |
GIR_Done, |
| 1276 |
// Label 116: @1569 |
1276 |
// Label 116: @1569 |
| 1277 |
GIM_Reject, |
1277 |
GIM_Reject, |
| 1278 |
// Label 110: @1570 |
1278 |
// Label 110: @1570 |
| 1279 |
GIM_Reject, |
1279 |
GIM_Reject, |
| 1280 |
// Label 102: @1571 |
1280 |
// Label 102: @1571 |
| 1281 |
GIM_Try, /*On fail goto*//*Label 117*/ 1602, // Rule ID 197 // |
1281 |
GIM_Try, /*On fail goto*//*Label 117*/ 1602, // Rule ID 197 // |
| 1282 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
1282 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
| 1283 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
1283 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 1284 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
1284 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 1285 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
1285 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 1286 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
1286 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 1287 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
1287 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 1288 |
// (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
1288 |
// (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 1289 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu, |
1289 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu, |
| 1290 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1290 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1291 |
// GIR_Coverage, 197, |
1291 |
// GIR_Coverage, 197, |
| 1292 |
GIR_Done, |
1292 |
GIR_Done, |
| 1293 |
// Label 117: @1602 |
1293 |
// Label 117: @1602 |
| 1294 |
GIM_Reject, |
1294 |
GIM_Reject, |
| 1295 |
// Label 103: @1603 |
1295 |
// Label 103: @1603 |
| 1296 |
GIM_Try, /*On fail goto*//*Label 118*/ 1629, // Rule ID 1884 // |
1296 |
GIM_Try, /*On fail goto*//*Label 118*/ 1629, // Rule ID 1884 // |
| 1297 |
GIM_CheckFeatures, GIFBS_HasDSP, |
1297 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 1298 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
1298 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
| 1299 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
1299 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 1300 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
1300 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 1301 |
// (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) |
1301 |
// (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) |
| 1302 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBQ_PH, |
1302 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBQ_PH, |
| 1303 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20, |
1303 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20, |
| 1304 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1304 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1305 |
// GIR_Coverage, 1884, |
1305 |
// GIR_Coverage, 1884, |
| 1306 |
GIR_Done, |
1306 |
GIR_Done, |
| 1307 |
// Label 118: @1629 |
1307 |
// Label 118: @1629 |
| 1308 |
GIM_Reject, |
1308 |
GIM_Reject, |
| 1309 |
// Label 104: @1630 |
1309 |
// Label 104: @1630 |
| 1310 |
GIM_Try, /*On fail goto*//*Label 119*/ 1717, |
1310 |
GIM_Try, /*On fail goto*//*Label 119*/ 1717, |
| 1311 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
1311 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 1312 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
1312 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 1313 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
1313 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 1314 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
1314 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 1315 |
GIM_Try, /*On fail goto*//*Label 120*/ 1701, // Rule ID 887 // |
1315 |
GIM_Try, /*On fail goto*//*Label 120*/ 1701, // Rule ID 887 // |
| 1316 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1316 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1317 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
1317 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1318 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
1318 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1319 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
1319 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 1320 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
1320 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 1321 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
1321 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 1322 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
1322 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 1323 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
1323 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1324 |
// (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
1324 |
// (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 1325 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D, |
1325 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D, |
| 1326 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
1326 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 1327 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
1327 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
| 1328 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
1328 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 1329 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
1329 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 1330 |
GIR_EraseFromParent, /*InsnID*/0, |
1330 |
GIR_EraseFromParent, /*InsnID*/0, |
| 1331 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1331 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1332 |
// GIR_Coverage, 887, |
1332 |
// GIR_Coverage, 887, |
| 1333 |
GIR_Done, |
1333 |
GIR_Done, |
| 1334 |
// Label 120: @1701 |
1334 |
// Label 120: @1701 |
| 1335 |
GIM_Try, /*On fail goto*//*Label 121*/ 1716, // Rule ID 1016 // |
1335 |
GIM_Try, /*On fail goto*//*Label 121*/ 1716, // Rule ID 1016 // |
| 1336 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1336 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1337 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
1337 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 1338 |
// (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
1338 |
// (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 1339 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_D, |
1339 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_D, |
| 1340 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1340 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1341 |
// GIR_Coverage, 1016, |
1341 |
// GIR_Coverage, 1016, |
| 1342 |
GIR_Done, |
1342 |
GIR_Done, |
| 1343 |
// Label 121: @1716 |
1343 |
// Label 121: @1716 |
| 1344 |
GIM_Reject, |
1344 |
GIM_Reject, |
| 1345 |
// Label 119: @1717 |
1345 |
// Label 119: @1717 |
| 1346 |
GIM_Reject, |
1346 |
GIM_Reject, |
| 1347 |
// Label 105: @1718 |
1347 |
// Label 105: @1718 |
| 1348 |
GIM_Try, /*On fail goto*//*Label 122*/ 1744, // Rule ID 1890 // |
1348 |
GIM_Try, /*On fail goto*//*Label 122*/ 1744, // Rule ID 1890 // |
| 1349 |
GIM_CheckFeatures, GIFBS_HasDSP, |
1349 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 1350 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
1350 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
| 1351 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
1351 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 1352 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
1352 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 1353 |
// (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) |
1353 |
// (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) |
| 1354 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU_QB, |
1354 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU_QB, |
| 1355 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20, |
1355 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20, |
| 1356 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1356 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1357 |
// GIR_Coverage, 1890, |
1357 |
// GIR_Coverage, 1890, |
| 1358 |
GIR_Done, |
1358 |
GIR_Done, |
| 1359 |
// Label 122: @1744 |
1359 |
// Label 122: @1744 |
| 1360 |
GIM_Reject, |
1360 |
GIM_Reject, |
| 1361 |
// Label 106: @1745 |
1361 |
// Label 106: @1745 |
| 1362 |
GIM_Try, /*On fail goto*//*Label 123*/ 1832, |
1362 |
GIM_Try, /*On fail goto*//*Label 123*/ 1832, |
| 1363 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
1363 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1364 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
1364 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1365 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
1365 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 1366 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
1366 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 1367 |
GIM_Try, /*On fail goto*//*Label 124*/ 1816, // Rule ID 886 // |
1367 |
GIM_Try, /*On fail goto*//*Label 124*/ 1816, // Rule ID 886 // |
| 1368 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1368 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1369 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
1369 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1370 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
1370 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1371 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
1371 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1372 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
1372 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1373 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
1373 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 1374 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
1374 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 1375 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
1375 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1376 |
// (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
1376 |
// (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 1377 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W, |
1377 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W, |
| 1378 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
1378 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 1379 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
1379 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
| 1380 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
1380 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 1381 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
1381 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 1382 |
GIR_EraseFromParent, /*InsnID*/0, |
1382 |
GIR_EraseFromParent, /*InsnID*/0, |
| 1383 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1383 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1384 |
// GIR_Coverage, 886, |
1384 |
// GIR_Coverage, 886, |
| 1385 |
GIR_Done, |
1385 |
GIR_Done, |
| 1386 |
// Label 124: @1816 |
1386 |
// Label 124: @1816 |
| 1387 |
GIM_Try, /*On fail goto*//*Label 125*/ 1831, // Rule ID 1015 // |
1387 |
GIM_Try, /*On fail goto*//*Label 125*/ 1831, // Rule ID 1015 // |
| 1388 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1388 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1389 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
1389 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 1390 |
// (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
1390 |
// (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 1391 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_W, |
1391 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_W, |
| 1392 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1392 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1393 |
// GIR_Coverage, 1015, |
1393 |
// GIR_Coverage, 1015, |
| 1394 |
GIR_Done, |
1394 |
GIR_Done, |
| 1395 |
// Label 125: @1831 |
1395 |
// Label 125: @1831 |
| 1396 |
GIM_Reject, |
1396 |
GIM_Reject, |
| 1397 |
// Label 123: @1832 |
1397 |
// Label 123: @1832 |
| 1398 |
GIM_Reject, |
1398 |
GIM_Reject, |
| 1399 |
// Label 107: @1833 |
1399 |
// Label 107: @1833 |
| 1400 |
GIM_Try, /*On fail goto*//*Label 126*/ 1920, |
1400 |
GIM_Try, /*On fail goto*//*Label 126*/ 1920, |
| 1401 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
1401 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 1402 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
1402 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 1403 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
1403 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 1404 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
1404 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 1405 |
GIM_Try, /*On fail goto*//*Label 127*/ 1904, // Rule ID 885 // |
1405 |
GIM_Try, /*On fail goto*//*Label 127*/ 1904, // Rule ID 885 // |
| 1406 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1406 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1407 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
1407 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1408 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
1408 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1409 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
1409 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 1410 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
1410 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 1411 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
1411 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 1412 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
1412 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 1413 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
1413 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1414 |
// (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
1414 |
// (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 1415 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H, |
1415 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H, |
| 1416 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
1416 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 1417 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
1417 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
| 1418 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
1418 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 1419 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
1419 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 1420 |
GIR_EraseFromParent, /*InsnID*/0, |
1420 |
GIR_EraseFromParent, /*InsnID*/0, |
| 1421 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1421 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1422 |
// GIR_Coverage, 885, |
1422 |
// GIR_Coverage, 885, |
| 1423 |
GIR_Done, |
1423 |
GIR_Done, |
| 1424 |
// Label 127: @1904 |
1424 |
// Label 127: @1904 |
| 1425 |
GIM_Try, /*On fail goto*//*Label 128*/ 1919, // Rule ID 1014 // |
1425 |
GIM_Try, /*On fail goto*//*Label 128*/ 1919, // Rule ID 1014 // |
| 1426 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1426 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1427 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
1427 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 1428 |
// (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
1428 |
// (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 1429 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_H, |
1429 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_H, |
| 1430 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1430 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1431 |
// GIR_Coverage, 1014, |
1431 |
// GIR_Coverage, 1014, |
| 1432 |
GIR_Done, |
1432 |
GIR_Done, |
| 1433 |
// Label 128: @1919 |
1433 |
// Label 128: @1919 |
| 1434 |
GIM_Reject, |
1434 |
GIM_Reject, |
| 1435 |
// Label 126: @1920 |
1435 |
// Label 126: @1920 |
| 1436 |
GIM_Reject, |
1436 |
GIM_Reject, |
| 1437 |
// Label 108: @1921 |
1437 |
// Label 108: @1921 |
| 1438 |
GIM_Try, /*On fail goto*//*Label 129*/ 2008, |
1438 |
GIM_Try, /*On fail goto*//*Label 129*/ 2008, |
| 1439 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
1439 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 1440 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
1440 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 1441 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
1441 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 1442 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
1442 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 1443 |
GIM_Try, /*On fail goto*//*Label 130*/ 1992, // Rule ID 884 // |
1443 |
GIM_Try, /*On fail goto*//*Label 130*/ 1992, // Rule ID 884 // |
| 1444 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1444 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1445 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
1445 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1446 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
1446 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 1447 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
1447 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 1448 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
1448 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 1449 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
1449 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 1450 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
1450 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 1451 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
1451 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 1452 |
// (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
1452 |
// (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 1453 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B, |
1453 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B, |
| 1454 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
1454 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 1455 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
1455 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in |
| 1456 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
1456 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 1457 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
1457 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 1458 |
GIR_EraseFromParent, /*InsnID*/0, |
1458 |
GIR_EraseFromParent, /*InsnID*/0, |
| 1459 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1459 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1460 |
// GIR_Coverage, 884, |
1460 |
// GIR_Coverage, 884, |
| 1461 |
GIR_Done, |
1461 |
GIR_Done, |
| 1462 |
// Label 130: @1992 |
1462 |
// Label 130: @1992 |
| 1463 |
GIM_Try, /*On fail goto*//*Label 131*/ 2007, // Rule ID 1013 // |
1463 |
GIM_Try, /*On fail goto*//*Label 131*/ 2007, // Rule ID 1013 // |
| 1464 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1464 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1465 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
1465 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 1466 |
// (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
1466 |
// (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 1467 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_B, |
1467 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_B, |
| 1468 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1468 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1469 |
// GIR_Coverage, 1013, |
1469 |
// GIR_Coverage, 1013, |
| 1470 |
GIR_Done, |
1470 |
GIR_Done, |
| 1471 |
// Label 131: @2007 |
1471 |
// Label 131: @2007 |
| 1472 |
GIM_Reject, |
1472 |
GIM_Reject, |
| 1473 |
// Label 129: @2008 |
1473 |
// Label 129: @2008 |
| 1474 |
GIM_Reject, |
1474 |
GIM_Reject, |
| 1475 |
// Label 109: @2009 |
1475 |
// Label 109: @2009 |
| 1476 |
GIM_Reject, |
1476 |
GIM_Reject, |
| 1477 |
// Label 2: @2010 |
1477 |
// Label 2: @2010 |
| 1478 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 139*/ 2385, |
1478 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 139*/ 2385, |
| 1479 |
/*GILLT_s32*//*Label 132*/ 2024, |
1479 |
/*GILLT_s32*//*Label 132*/ 2024, |
| 1480 |
/*GILLT_s64*//*Label 133*/ 2169, |
1480 |
/*GILLT_s64*//*Label 133*/ 2169, |
| 1481 |
/*GILLT_v2s16*//*Label 134*/ 2230, |
1481 |
/*GILLT_v2s16*//*Label 134*/ 2230, |
| 1482 |
/*GILLT_v2s64*//*Label 135*/ 2257, 0, |
1482 |
/*GILLT_v2s64*//*Label 135*/ 2257, 0, |
| 1483 |
/*GILLT_v4s32*//*Label 136*/ 2289, |
1483 |
/*GILLT_v4s32*//*Label 136*/ 2289, |
| 1484 |
/*GILLT_v8s16*//*Label 137*/ 2321, |
1484 |
/*GILLT_v8s16*//*Label 137*/ 2321, |
| 1485 |
/*GILLT_v16s8*//*Label 138*/ 2353, |
1485 |
/*GILLT_v16s8*//*Label 138*/ 2353, |
| 1486 |
// Label 132: @2024 |
1486 |
// Label 132: @2024 |
| 1487 |
GIM_Try, /*On fail goto*//*Label 140*/ 2168, |
1487 |
GIM_Try, /*On fail goto*//*Label 140*/ 2168, |
| 1488 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
1488 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 1489 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
1489 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 1490 |
GIM_Try, /*On fail goto*//*Label 141*/ 2063, // Rule ID 48 // |
1490 |
GIM_Try, /*On fail goto*//*Label 141*/ 2063, // Rule ID 48 // |
| 1491 |
GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
1491 |
GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 1492 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
1492 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 1493 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
1493 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 1494 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
1494 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 1495 |
// (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
1495 |
// (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 1496 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL, |
1496 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL, |
| 1497 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0, |
1497 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0, |
| 1498 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0, |
1498 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0, |
| 1499 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1499 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1500 |
// GIR_Coverage, 48, |
1500 |
// GIR_Coverage, 48, |
| 1501 |
GIR_Done, |
1501 |
GIR_Done, |
| 1502 |
// Label 141: @2063 |
1502 |
// Label 141: @2063 |
| 1503 |
GIM_Try, /*On fail goto*//*Label 142*/ 2086, // Rule ID 320 // |
1503 |
GIM_Try, /*On fail goto*//*Label 142*/ 2086, // Rule ID 320 // |
| 1504 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
1504 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 1505 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
1505 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 1506 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
1506 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 1507 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
1507 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 1508 |
// (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
1508 |
// (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 1509 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_R6, |
1509 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_R6, |
| 1510 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1510 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1511 |
// GIR_Coverage, 320, |
1511 |
// GIR_Coverage, 320, |
| 1512 |
GIR_Done, |
1512 |
GIR_Done, |
| 1513 |
// Label 142: @2086 |
1513 |
// Label 142: @2086 |
| 1514 |
GIM_Try, /*On fail goto*//*Label 143*/ 2115, // Rule ID 1062 // |
1514 |
GIM_Try, /*On fail goto*//*Label 143*/ 2115, // Rule ID 1062 // |
| 1515 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
1515 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 1516 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
1516 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 1517 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
1517 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 1518 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
1518 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 1519 |
// (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
1519 |
// (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 1520 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MM, |
1520 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MM, |
| 1521 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0, |
1521 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0, |
| 1522 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0, |
1522 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0, |
| 1523 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1523 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1524 |
// GIR_Coverage, 1062, |
1524 |
// GIR_Coverage, 1062, |
| 1525 |
GIR_Done, |
1525 |
GIR_Done, |
| 1526 |
// Label 143: @2115 |
1526 |
// Label 143: @2115 |
| 1527 |
GIM_Try, /*On fail goto*//*Label 144*/ 2138, // Rule ID 1167 // |
1527 |
GIM_Try, /*On fail goto*//*Label 144*/ 2138, // Rule ID 1167 // |
| 1528 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
1528 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 1529 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
1529 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 1530 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
1530 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 1531 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
1531 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 1532 |
// (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
1532 |
// (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 1533 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MMR6, |
1533 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MMR6, |
| 1534 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1534 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1535 |
// GIR_Coverage, 1167, |
1535 |
// GIR_Coverage, 1167, |
| 1536 |
GIR_Done, |
1536 |
GIR_Done, |
| 1537 |
// Label 144: @2138 |
1537 |
// Label 144: @2138 |
| 1538 |
GIM_Try, /*On fail goto*//*Label 145*/ 2167, // Rule ID 1785 // |
1538 |
GIM_Try, /*On fail goto*//*Label 145*/ 2167, // Rule ID 1785 // |
| 1539 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
1539 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 1540 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
1540 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 1541 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
1541 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 1542 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
1542 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 1543 |
// (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) |
1543 |
// (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) |
| 1544 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MultRxRyRz16, |
1544 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MultRxRyRz16, |
| 1545 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0, |
1545 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0, |
| 1546 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0, |
1546 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0, |
| 1547 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1547 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1548 |
// GIR_Coverage, 1785, |
1548 |
// GIR_Coverage, 1785, |
| 1549 |
GIR_Done, |
1549 |
GIR_Done, |
| 1550 |
// Label 145: @2167 |
1550 |
// Label 145: @2167 |
| 1551 |
GIM_Reject, |
1551 |
GIM_Reject, |
| 1552 |
// Label 140: @2168 |
1552 |
// Label 140: @2168 |
| 1553 |
GIM_Reject, |
1553 |
GIM_Reject, |
| 1554 |
// Label 133: @2169 |
1554 |
// Label 133: @2169 |
| 1555 |
GIM_Try, /*On fail goto*//*Label 146*/ 2229, |
1555 |
GIM_Try, /*On fail goto*//*Label 146*/ 2229, |
| 1556 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
1556 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 1557 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
1557 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 1558 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
1558 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 1559 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
1559 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 1560 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
1560 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 1561 |
GIM_Try, /*On fail goto*//*Label 147*/ 2217, // Rule ID 262 // |
1561 |
GIM_Try, /*On fail goto*//*Label 147*/ 2217, // Rule ID 262 // |
| 1562 |
GIM_CheckFeatures, GIFBS_HasCnMips, |
1562 |
GIM_CheckFeatures, GIFBS_HasCnMips, |
| 1563 |
// (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
1563 |
// (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 1564 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL, |
1564 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL, |
| 1565 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0, |
1565 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0, |
| 1566 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0, |
1566 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0, |
| 1567 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::P0, |
1567 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::P0, |
| 1568 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::P1, |
1568 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::P1, |
| 1569 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::P2, |
1569 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::P2, |
| 1570 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1570 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1571 |
// GIR_Coverage, 262, |
1571 |
// GIR_Coverage, 262, |
| 1572 |
GIR_Done, |
1572 |
GIR_Done, |
| 1573 |
// Label 147: @2217 |
1573 |
// Label 147: @2217 |
| 1574 |
GIM_Try, /*On fail goto*//*Label 148*/ 2228, // Rule ID 335 // |
1574 |
GIM_Try, /*On fail goto*//*Label 148*/ 2228, // Rule ID 335 // |
| 1575 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
1575 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
| 1576 |
// (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
1576 |
// (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 1577 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL_R6, |
1577 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL_R6, |
| 1578 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1578 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1579 |
// GIR_Coverage, 335, |
1579 |
// GIR_Coverage, 335, |
| 1580 |
GIR_Done, |
1580 |
GIR_Done, |
| 1581 |
// Label 148: @2228 |
1581 |
// Label 148: @2228 |
| 1582 |
GIM_Reject, |
1582 |
GIM_Reject, |
| 1583 |
// Label 146: @2229 |
1583 |
// Label 146: @2229 |
| 1584 |
GIM_Reject, |
1584 |
GIM_Reject, |
| 1585 |
// Label 134: @2230 |
1585 |
// Label 134: @2230 |
| 1586 |
GIM_Try, /*On fail goto*//*Label 149*/ 2256, // Rule ID 1886 // |
1586 |
GIM_Try, /*On fail goto*//*Label 149*/ 2256, // Rule ID 1886 // |
| 1587 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
1587 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 1588 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
1588 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
| 1589 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
1589 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 1590 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
1590 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 1591 |
// (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) |
1591 |
// (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) |
| 1592 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_PH, |
1592 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_PH, |
| 1593 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag21, |
1593 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag21, |
| 1594 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1594 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1595 |
// GIR_Coverage, 1886, |
1595 |
// GIR_Coverage, 1886, |
| 1596 |
GIR_Done, |
1596 |
GIR_Done, |
| 1597 |
// Label 149: @2256 |
1597 |
// Label 149: @2256 |
| 1598 |
GIM_Reject, |
1598 |
GIM_Reject, |
| 1599 |
// Label 135: @2257 |
1599 |
// Label 135: @2257 |
| 1600 |
GIM_Try, /*On fail goto*//*Label 150*/ 2288, // Rule ID 895 // |
1600 |
GIM_Try, /*On fail goto*//*Label 150*/ 2288, // Rule ID 895 // |
| 1601 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1601 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1602 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
1602 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 1603 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
1603 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 1604 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
1604 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 1605 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
1605 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 1606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
1606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 1607 |
// (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
1607 |
// (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 1608 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_D, |
1608 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_D, |
| 1609 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1609 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1610 |
// GIR_Coverage, 895, |
1610 |
// GIR_Coverage, 895, |
| 1611 |
GIR_Done, |
1611 |
GIR_Done, |
| 1612 |
// Label 150: @2288 |
1612 |
// Label 150: @2288 |
| 1613 |
GIM_Reject, |
1613 |
GIM_Reject, |
| 1614 |
// Label 136: @2289 |
1614 |
// Label 136: @2289 |
| 1615 |
GIM_Try, /*On fail goto*//*Label 151*/ 2320, // Rule ID 894 // |
1615 |
GIM_Try, /*On fail goto*//*Label 151*/ 2320, // Rule ID 894 // |
| 1616 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1616 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1617 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
1617 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1618 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
1618 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1619 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
1619 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 1620 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
1620 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 1621 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
1621 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 1622 |
// (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
1622 |
// (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 1623 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_W, |
1623 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_W, |
| 1624 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1624 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1625 |
// GIR_Coverage, 894, |
1625 |
// GIR_Coverage, 894, |
| 1626 |
GIR_Done, |
1626 |
GIR_Done, |
| 1627 |
// Label 151: @2320 |
1627 |
// Label 151: @2320 |
| 1628 |
GIM_Reject, |
1628 |
GIM_Reject, |
| 1629 |
// Label 137: @2321 |
1629 |
// Label 137: @2321 |
| 1630 |
GIM_Try, /*On fail goto*//*Label 152*/ 2352, // Rule ID 893 // |
1630 |
GIM_Try, /*On fail goto*//*Label 152*/ 2352, // Rule ID 893 // |
| 1631 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1631 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1632 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
1632 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 1633 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
1633 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 1634 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
1634 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 1635 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
1635 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 1636 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
1636 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 1637 |
// (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
1637 |
// (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 1638 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_H, |
1638 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_H, |
| 1639 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1639 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1640 |
// GIR_Coverage, 893, |
1640 |
// GIR_Coverage, 893, |
| 1641 |
GIR_Done, |
1641 |
GIR_Done, |
| 1642 |
// Label 152: @2352 |
1642 |
// Label 152: @2352 |
| 1643 |
GIM_Reject, |
1643 |
GIM_Reject, |
| 1644 |
// Label 138: @2353 |
1644 |
// Label 138: @2353 |
| 1645 |
GIM_Try, /*On fail goto*//*Label 153*/ 2384, // Rule ID 892 // |
1645 |
GIM_Try, /*On fail goto*//*Label 153*/ 2384, // Rule ID 892 // |
| 1646 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1646 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1647 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
1647 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 1648 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
1648 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 1649 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
1649 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 1650 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
1650 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 1651 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
1651 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 1652 |
// (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
1652 |
// (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 1653 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_B, |
1653 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_B, |
| 1654 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1654 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1655 |
// GIR_Coverage, 892, |
1655 |
// GIR_Coverage, 892, |
| 1656 |
GIR_Done, |
1656 |
GIR_Done, |
| 1657 |
// Label 153: @2384 |
1657 |
// Label 153: @2384 |
| 1658 |
GIM_Reject, |
1658 |
GIM_Reject, |
| 1659 |
// Label 139: @2385 |
1659 |
// Label 139: @2385 |
| 1660 |
GIM_Reject, |
1660 |
GIM_Reject, |
| 1661 |
// Label 3: @2386 |
1661 |
// Label 3: @2386 |
| 1662 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 160*/ 2606, |
1662 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 160*/ 2606, |
| 1663 |
/*GILLT_s32*//*Label 154*/ 2400, |
1663 |
/*GILLT_s32*//*Label 154*/ 2400, |
| 1664 |
/*GILLT_s64*//*Label 155*/ 2446, 0, |
1664 |
/*GILLT_s64*//*Label 155*/ 2446, 0, |
| 1665 |
/*GILLT_v2s64*//*Label 156*/ 2478, 0, |
1665 |
/*GILLT_v2s64*//*Label 156*/ 2478, 0, |
| 1666 |
/*GILLT_v4s32*//*Label 157*/ 2510, |
1666 |
/*GILLT_v4s32*//*Label 157*/ 2510, |
| 1667 |
/*GILLT_v8s16*//*Label 158*/ 2542, |
1667 |
/*GILLT_v8s16*//*Label 158*/ 2542, |
| 1668 |
/*GILLT_v16s8*//*Label 159*/ 2574, |
1668 |
/*GILLT_v16s8*//*Label 159*/ 2574, |
| 1669 |
// Label 154: @2400 |
1669 |
// Label 154: @2400 |
| 1670 |
GIM_Try, /*On fail goto*//*Label 161*/ 2445, |
1670 |
GIM_Try, /*On fail goto*//*Label 161*/ 2445, |
| 1671 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
1671 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 1672 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
1672 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 1673 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
1673 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 1674 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
1674 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 1675 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
1675 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 1676 |
GIM_Try, /*On fail goto*//*Label 162*/ 2433, // Rule ID 314 // |
1676 |
GIM_Try, /*On fail goto*//*Label 162*/ 2433, // Rule ID 314 // |
| 1677 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
1677 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 1678 |
// (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
1678 |
// (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 1679 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV, |
1679 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV, |
| 1680 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1680 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1681 |
// GIR_Coverage, 314, |
1681 |
// GIR_Coverage, 314, |
| 1682 |
GIR_Done, |
1682 |
GIR_Done, |
| 1683 |
// Label 162: @2433 |
1683 |
// Label 162: @2433 |
| 1684 |
GIM_Try, /*On fail goto*//*Label 163*/ 2444, // Rule ID 1160 // |
1684 |
GIM_Try, /*On fail goto*//*Label 163*/ 2444, // Rule ID 1160 // |
| 1685 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
1685 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 1686 |
// (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
1686 |
// (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 1687 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_MMR6, |
1687 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_MMR6, |
| 1688 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1688 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1689 |
// GIR_Coverage, 1160, |
1689 |
// GIR_Coverage, 1160, |
| 1690 |
GIR_Done, |
1690 |
GIR_Done, |
| 1691 |
// Label 163: @2444 |
1691 |
// Label 163: @2444 |
| 1692 |
GIM_Reject, |
1692 |
GIM_Reject, |
| 1693 |
// Label 161: @2445 |
1693 |
// Label 161: @2445 |
| 1694 |
GIM_Reject, |
1694 |
GIM_Reject, |
| 1695 |
// Label 155: @2446 |
1695 |
// Label 155: @2446 |
| 1696 |
GIM_Try, /*On fail goto*//*Label 164*/ 2477, // Rule ID 329 // |
1696 |
GIM_Try, /*On fail goto*//*Label 164*/ 2477, // Rule ID 329 // |
| 1697 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
1697 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
| 1698 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
1698 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 1699 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
1699 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 1700 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
1700 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 1701 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
1701 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 1702 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
1702 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 1703 |
// (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
1703 |
// (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 1704 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIV, |
1704 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIV, |
| 1705 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1705 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1706 |
// GIR_Coverage, 329, |
1706 |
// GIR_Coverage, 329, |
| 1707 |
GIR_Done, |
1707 |
GIR_Done, |
| 1708 |
// Label 164: @2477 |
1708 |
// Label 164: @2477 |
| 1709 |
GIM_Reject, |
1709 |
GIM_Reject, |
| 1710 |
// Label 156: @2478 |
1710 |
// Label 156: @2478 |
| 1711 |
GIM_Try, /*On fail goto*//*Label 165*/ 2509, // Rule ID 635 // |
1711 |
GIM_Try, /*On fail goto*//*Label 165*/ 2509, // Rule ID 635 // |
| 1712 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1712 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1713 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
1713 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 1714 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
1714 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 1715 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
1715 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 1716 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
1716 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 1717 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
1717 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 1718 |
// (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
1718 |
// (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 1719 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_D, |
1719 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_D, |
| 1720 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1720 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1721 |
// GIR_Coverage, 635, |
1721 |
// GIR_Coverage, 635, |
| 1722 |
GIR_Done, |
1722 |
GIR_Done, |
| 1723 |
// Label 165: @2509 |
1723 |
// Label 165: @2509 |
| 1724 |
GIM_Reject, |
1724 |
GIM_Reject, |
| 1725 |
// Label 157: @2510 |
1725 |
// Label 157: @2510 |
| 1726 |
GIM_Try, /*On fail goto*//*Label 166*/ 2541, // Rule ID 634 // |
1726 |
GIM_Try, /*On fail goto*//*Label 166*/ 2541, // Rule ID 634 // |
| 1727 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1727 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1728 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
1728 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1729 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
1729 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1730 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
1730 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 1731 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
1731 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 1732 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
1732 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 1733 |
// (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
1733 |
// (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 1734 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_W, |
1734 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_W, |
| 1735 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1735 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1736 |
// GIR_Coverage, 634, |
1736 |
// GIR_Coverage, 634, |
| 1737 |
GIR_Done, |
1737 |
GIR_Done, |
| 1738 |
// Label 166: @2541 |
1738 |
// Label 166: @2541 |
| 1739 |
GIM_Reject, |
1739 |
GIM_Reject, |
| 1740 |
// Label 158: @2542 |
1740 |
// Label 158: @2542 |
| 1741 |
GIM_Try, /*On fail goto*//*Label 167*/ 2573, // Rule ID 633 // |
1741 |
GIM_Try, /*On fail goto*//*Label 167*/ 2573, // Rule ID 633 // |
| 1742 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1742 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1743 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
1743 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 1744 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
1744 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 1745 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
1745 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 1746 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
1746 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 1747 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
1747 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 1748 |
// (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
1748 |
// (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 1749 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_H, |
1749 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_H, |
| 1750 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1750 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1751 |
// GIR_Coverage, 633, |
1751 |
// GIR_Coverage, 633, |
| 1752 |
GIR_Done, |
1752 |
GIR_Done, |
| 1753 |
// Label 167: @2573 |
1753 |
// Label 167: @2573 |
| 1754 |
GIM_Reject, |
1754 |
GIM_Reject, |
| 1755 |
// Label 159: @2574 |
1755 |
// Label 159: @2574 |
| 1756 |
GIM_Try, /*On fail goto*//*Label 168*/ 2605, // Rule ID 632 // |
1756 |
GIM_Try, /*On fail goto*//*Label 168*/ 2605, // Rule ID 632 // |
| 1757 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1757 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1758 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
1758 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 1759 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
1759 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 1760 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
1760 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 1761 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
1761 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 1762 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
1762 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 1763 |
// (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
1763 |
// (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 1764 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_B, |
1764 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_B, |
| 1765 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1765 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1766 |
// GIR_Coverage, 632, |
1766 |
// GIR_Coverage, 632, |
| 1767 |
GIR_Done, |
1767 |
GIR_Done, |
| 1768 |
// Label 168: @2605 |
1768 |
// Label 168: @2605 |
| 1769 |
GIM_Reject, |
1769 |
GIM_Reject, |
| 1770 |
// Label 160: @2606 |
1770 |
// Label 160: @2606 |
| 1771 |
GIM_Reject, |
1771 |
GIM_Reject, |
| 1772 |
// Label 4: @2607 |
1772 |
// Label 4: @2607 |
| 1773 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 175*/ 2827, |
1773 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 175*/ 2827, |
| 1774 |
/*GILLT_s32*//*Label 169*/ 2621, |
1774 |
/*GILLT_s32*//*Label 169*/ 2621, |
| 1775 |
/*GILLT_s64*//*Label 170*/ 2667, 0, |
1775 |
/*GILLT_s64*//*Label 170*/ 2667, 0, |
| 1776 |
/*GILLT_v2s64*//*Label 171*/ 2699, 0, |
1776 |
/*GILLT_v2s64*//*Label 171*/ 2699, 0, |
| 1777 |
/*GILLT_v4s32*//*Label 172*/ 2731, |
1777 |
/*GILLT_v4s32*//*Label 172*/ 2731, |
| 1778 |
/*GILLT_v8s16*//*Label 173*/ 2763, |
1778 |
/*GILLT_v8s16*//*Label 173*/ 2763, |
| 1779 |
/*GILLT_v16s8*//*Label 174*/ 2795, |
1779 |
/*GILLT_v16s8*//*Label 174*/ 2795, |
| 1780 |
// Label 169: @2621 |
1780 |
// Label 169: @2621 |
| 1781 |
GIM_Try, /*On fail goto*//*Label 176*/ 2666, |
1781 |
GIM_Try, /*On fail goto*//*Label 176*/ 2666, |
| 1782 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
1782 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 1783 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
1783 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 1784 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
1784 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 1785 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
1785 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 1786 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
1786 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 1787 |
GIM_Try, /*On fail goto*//*Label 177*/ 2654, // Rule ID 315 // |
1787 |
GIM_Try, /*On fail goto*//*Label 177*/ 2654, // Rule ID 315 // |
| 1788 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
1788 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 1789 |
// (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
1789 |
// (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 1790 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU, |
1790 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU, |
| 1791 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1791 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1792 |
// GIR_Coverage, 315, |
1792 |
// GIR_Coverage, 315, |
| 1793 |
GIR_Done, |
1793 |
GIR_Done, |
| 1794 |
// Label 177: @2654 |
1794 |
// Label 177: @2654 |
| 1795 |
GIM_Try, /*On fail goto*//*Label 178*/ 2665, // Rule ID 1161 // |
1795 |
GIM_Try, /*On fail goto*//*Label 178*/ 2665, // Rule ID 1161 // |
| 1796 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
1796 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 1797 |
// (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
1797 |
// (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 1798 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU_MMR6, |
1798 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU_MMR6, |
| 1799 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1799 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1800 |
// GIR_Coverage, 1161, |
1800 |
// GIR_Coverage, 1161, |
| 1801 |
GIR_Done, |
1801 |
GIR_Done, |
| 1802 |
// Label 178: @2665 |
1802 |
// Label 178: @2665 |
| 1803 |
GIM_Reject, |
1803 |
GIM_Reject, |
| 1804 |
// Label 176: @2666 |
1804 |
// Label 176: @2666 |
| 1805 |
GIM_Reject, |
1805 |
GIM_Reject, |
| 1806 |
// Label 170: @2667 |
1806 |
// Label 170: @2667 |
| 1807 |
GIM_Try, /*On fail goto*//*Label 179*/ 2698, // Rule ID 330 // |
1807 |
GIM_Try, /*On fail goto*//*Label 179*/ 2698, // Rule ID 330 // |
| 1808 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
1808 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
| 1809 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
1809 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 1810 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
1810 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 1811 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
1811 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 1812 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
1812 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 1813 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
1813 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 1814 |
// (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
1814 |
// (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 1815 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU, |
1815 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU, |
| 1816 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1816 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1817 |
// GIR_Coverage, 330, |
1817 |
// GIR_Coverage, 330, |
| 1818 |
GIR_Done, |
1818 |
GIR_Done, |
| 1819 |
// Label 179: @2698 |
1819 |
// Label 179: @2698 |
| 1820 |
GIM_Reject, |
1820 |
GIM_Reject, |
| 1821 |
// Label 171: @2699 |
1821 |
// Label 171: @2699 |
| 1822 |
GIM_Try, /*On fail goto*//*Label 180*/ 2730, // Rule ID 639 // |
1822 |
GIM_Try, /*On fail goto*//*Label 180*/ 2730, // Rule ID 639 // |
| 1823 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1823 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1824 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
1824 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 1825 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
1825 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 1826 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
1826 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 1827 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
1827 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 1828 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
1828 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 1829 |
// (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
1829 |
// (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 1830 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_D, |
1830 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_D, |
| 1831 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1831 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1832 |
// GIR_Coverage, 639, |
1832 |
// GIR_Coverage, 639, |
| 1833 |
GIR_Done, |
1833 |
GIR_Done, |
| 1834 |
// Label 180: @2730 |
1834 |
// Label 180: @2730 |
| 1835 |
GIM_Reject, |
1835 |
GIM_Reject, |
| 1836 |
// Label 172: @2731 |
1836 |
// Label 172: @2731 |
| 1837 |
GIM_Try, /*On fail goto*//*Label 181*/ 2762, // Rule ID 638 // |
1837 |
GIM_Try, /*On fail goto*//*Label 181*/ 2762, // Rule ID 638 // |
| 1838 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1838 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1839 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
1839 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1840 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
1840 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1841 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
1841 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 1842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
1842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 1843 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
1843 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 1844 |
// (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
1844 |
// (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 1845 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_W, |
1845 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_W, |
| 1846 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1846 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1847 |
// GIR_Coverage, 638, |
1847 |
// GIR_Coverage, 638, |
| 1848 |
GIR_Done, |
1848 |
GIR_Done, |
| 1849 |
// Label 181: @2762 |
1849 |
// Label 181: @2762 |
| 1850 |
GIM_Reject, |
1850 |
GIM_Reject, |
| 1851 |
// Label 173: @2763 |
1851 |
// Label 173: @2763 |
| 1852 |
GIM_Try, /*On fail goto*//*Label 182*/ 2794, // Rule ID 637 // |
1852 |
GIM_Try, /*On fail goto*//*Label 182*/ 2794, // Rule ID 637 // |
| 1853 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1853 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1854 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
1854 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 1855 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
1855 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 1856 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
1856 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 1857 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
1857 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 1858 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
1858 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 1859 |
// (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
1859 |
// (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 1860 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_H, |
1860 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_H, |
| 1861 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1861 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1862 |
// GIR_Coverage, 637, |
1862 |
// GIR_Coverage, 637, |
| 1863 |
GIR_Done, |
1863 |
GIR_Done, |
| 1864 |
// Label 182: @2794 |
1864 |
// Label 182: @2794 |
| 1865 |
GIM_Reject, |
1865 |
GIM_Reject, |
| 1866 |
// Label 174: @2795 |
1866 |
// Label 174: @2795 |
| 1867 |
GIM_Try, /*On fail goto*//*Label 183*/ 2826, // Rule ID 636 // |
1867 |
GIM_Try, /*On fail goto*//*Label 183*/ 2826, // Rule ID 636 // |
| 1868 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1868 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1869 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
1869 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 1870 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
1870 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 1871 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
1871 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 1872 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
1872 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 1873 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
1873 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 1874 |
// (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
1874 |
// (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 1875 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_B, |
1875 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_B, |
| 1876 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1876 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1877 |
// GIR_Coverage, 636, |
1877 |
// GIR_Coverage, 636, |
| 1878 |
GIR_Done, |
1878 |
GIR_Done, |
| 1879 |
// Label 183: @2826 |
1879 |
// Label 183: @2826 |
| 1880 |
GIM_Reject, |
1880 |
GIM_Reject, |
| 1881 |
// Label 175: @2827 |
1881 |
// Label 175: @2827 |
| 1882 |
GIM_Reject, |
1882 |
GIM_Reject, |
| 1883 |
// Label 5: @2828 |
1883 |
// Label 5: @2828 |
| 1884 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 190*/ 3048, |
1884 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 190*/ 3048, |
| 1885 |
/*GILLT_s32*//*Label 184*/ 2842, |
1885 |
/*GILLT_s32*//*Label 184*/ 2842, |
| 1886 |
/*GILLT_s64*//*Label 185*/ 2888, 0, |
1886 |
/*GILLT_s64*//*Label 185*/ 2888, 0, |
| 1887 |
/*GILLT_v2s64*//*Label 186*/ 2920, 0, |
1887 |
/*GILLT_v2s64*//*Label 186*/ 2920, 0, |
| 1888 |
/*GILLT_v4s32*//*Label 187*/ 2952, |
1888 |
/*GILLT_v4s32*//*Label 187*/ 2952, |
| 1889 |
/*GILLT_v8s16*//*Label 188*/ 2984, |
1889 |
/*GILLT_v8s16*//*Label 188*/ 2984, |
| 1890 |
/*GILLT_v16s8*//*Label 189*/ 3016, |
1890 |
/*GILLT_v16s8*//*Label 189*/ 3016, |
| 1891 |
// Label 184: @2842 |
1891 |
// Label 184: @2842 |
| 1892 |
GIM_Try, /*On fail goto*//*Label 191*/ 2887, |
1892 |
GIM_Try, /*On fail goto*//*Label 191*/ 2887, |
| 1893 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
1893 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 1894 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
1894 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 1895 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
1895 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 1896 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
1896 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 1897 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
1897 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 1898 |
GIM_Try, /*On fail goto*//*Label 192*/ 2875, // Rule ID 316 // |
1898 |
GIM_Try, /*On fail goto*//*Label 192*/ 2875, // Rule ID 316 // |
| 1899 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
1899 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 1900 |
// (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
1900 |
// (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 1901 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD, |
1901 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD, |
| 1902 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1902 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1903 |
// GIR_Coverage, 316, |
1903 |
// GIR_Coverage, 316, |
| 1904 |
GIR_Done, |
1904 |
GIR_Done, |
| 1905 |
// Label 192: @2875 |
1905 |
// Label 192: @2875 |
| 1906 |
GIM_Try, /*On fail goto*//*Label 193*/ 2886, // Rule ID 1165 // |
1906 |
GIM_Try, /*On fail goto*//*Label 193*/ 2886, // Rule ID 1165 // |
| 1907 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
1907 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 1908 |
// (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
1908 |
// (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 1909 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_MMR6, |
1909 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_MMR6, |
| 1910 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1910 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1911 |
// GIR_Coverage, 1165, |
1911 |
// GIR_Coverage, 1165, |
| 1912 |
GIR_Done, |
1912 |
GIR_Done, |
| 1913 |
// Label 193: @2886 |
1913 |
// Label 193: @2886 |
| 1914 |
GIM_Reject, |
1914 |
GIM_Reject, |
| 1915 |
// Label 191: @2887 |
1915 |
// Label 191: @2887 |
| 1916 |
GIM_Reject, |
1916 |
GIM_Reject, |
| 1917 |
// Label 185: @2888 |
1917 |
// Label 185: @2888 |
| 1918 |
GIM_Try, /*On fail goto*//*Label 194*/ 2919, // Rule ID 331 // |
1918 |
GIM_Try, /*On fail goto*//*Label 194*/ 2919, // Rule ID 331 // |
| 1919 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
1919 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
| 1920 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
1920 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 1921 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
1921 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 1922 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
1922 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 1923 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
1923 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 1924 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
1924 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 1925 |
// (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
1925 |
// (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 1926 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMOD, |
1926 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMOD, |
| 1927 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1927 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1928 |
// GIR_Coverage, 331, |
1928 |
// GIR_Coverage, 331, |
| 1929 |
GIR_Done, |
1929 |
GIR_Done, |
| 1930 |
// Label 194: @2919 |
1930 |
// Label 194: @2919 |
| 1931 |
GIM_Reject, |
1931 |
GIM_Reject, |
| 1932 |
// Label 186: @2920 |
1932 |
// Label 186: @2920 |
| 1933 |
GIM_Try, /*On fail goto*//*Label 195*/ 2951, // Rule ID 875 // |
1933 |
GIM_Try, /*On fail goto*//*Label 195*/ 2951, // Rule ID 875 // |
| 1934 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1934 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1935 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
1935 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 1936 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
1936 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 1937 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
1937 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 1938 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
1938 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 1939 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
1939 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 1940 |
// (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
1940 |
// (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 1941 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_D, |
1941 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_D, |
| 1942 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1942 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1943 |
// GIR_Coverage, 875, |
1943 |
// GIR_Coverage, 875, |
| 1944 |
GIR_Done, |
1944 |
GIR_Done, |
| 1945 |
// Label 195: @2951 |
1945 |
// Label 195: @2951 |
| 1946 |
GIM_Reject, |
1946 |
GIM_Reject, |
| 1947 |
// Label 187: @2952 |
1947 |
// Label 187: @2952 |
| 1948 |
GIM_Try, /*On fail goto*//*Label 196*/ 2983, // Rule ID 874 // |
1948 |
GIM_Try, /*On fail goto*//*Label 196*/ 2983, // Rule ID 874 // |
| 1949 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1949 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1950 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
1950 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1951 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
1951 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1952 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
1952 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 1953 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
1953 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 1954 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
1954 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 1955 |
// (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
1955 |
// (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 1956 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_W, |
1956 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_W, |
| 1957 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1957 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1958 |
// GIR_Coverage, 874, |
1958 |
// GIR_Coverage, 874, |
| 1959 |
GIR_Done, |
1959 |
GIR_Done, |
| 1960 |
// Label 196: @2983 |
1960 |
// Label 196: @2983 |
| 1961 |
GIM_Reject, |
1961 |
GIM_Reject, |
| 1962 |
// Label 188: @2984 |
1962 |
// Label 188: @2984 |
| 1963 |
GIM_Try, /*On fail goto*//*Label 197*/ 3015, // Rule ID 873 // |
1963 |
GIM_Try, /*On fail goto*//*Label 197*/ 3015, // Rule ID 873 // |
| 1964 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1964 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1965 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
1965 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 1966 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
1966 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 1967 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
1967 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 1968 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
1968 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 1969 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
1969 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 1970 |
// (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
1970 |
// (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 1971 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_H, |
1971 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_H, |
| 1972 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1972 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1973 |
// GIR_Coverage, 873, |
1973 |
// GIR_Coverage, 873, |
| 1974 |
GIR_Done, |
1974 |
GIR_Done, |
| 1975 |
// Label 197: @3015 |
1975 |
// Label 197: @3015 |
| 1976 |
GIM_Reject, |
1976 |
GIM_Reject, |
| 1977 |
// Label 189: @3016 |
1977 |
// Label 189: @3016 |
| 1978 |
GIM_Try, /*On fail goto*//*Label 198*/ 3047, // Rule ID 872 // |
1978 |
GIM_Try, /*On fail goto*//*Label 198*/ 3047, // Rule ID 872 // |
| 1979 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
1979 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 1980 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
1980 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 1981 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
1981 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 1982 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
1982 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 1983 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
1983 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 1984 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
1984 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 1985 |
// (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
1985 |
// (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 1986 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_B, |
1986 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_B, |
| 1987 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
1987 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 1988 |
// GIR_Coverage, 872, |
1988 |
// GIR_Coverage, 872, |
| 1989 |
GIR_Done, |
1989 |
GIR_Done, |
| 1990 |
// Label 198: @3047 |
1990 |
// Label 198: @3047 |
| 1991 |
GIM_Reject, |
1991 |
GIM_Reject, |
| 1992 |
// Label 190: @3048 |
1992 |
// Label 190: @3048 |
| 1993 |
GIM_Reject, |
1993 |
GIM_Reject, |
| 1994 |
// Label 6: @3049 |
1994 |
// Label 6: @3049 |
| 1995 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 205*/ 3269, |
1995 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 205*/ 3269, |
| 1996 |
/*GILLT_s32*//*Label 199*/ 3063, |
1996 |
/*GILLT_s32*//*Label 199*/ 3063, |
| 1997 |
/*GILLT_s64*//*Label 200*/ 3109, 0, |
1997 |
/*GILLT_s64*//*Label 200*/ 3109, 0, |
| 1998 |
/*GILLT_v2s64*//*Label 201*/ 3141, 0, |
1998 |
/*GILLT_v2s64*//*Label 201*/ 3141, 0, |
| 1999 |
/*GILLT_v4s32*//*Label 202*/ 3173, |
1999 |
/*GILLT_v4s32*//*Label 202*/ 3173, |
| 2000 |
/*GILLT_v8s16*//*Label 203*/ 3205, |
2000 |
/*GILLT_v8s16*//*Label 203*/ 3205, |
| 2001 |
/*GILLT_v16s8*//*Label 204*/ 3237, |
2001 |
/*GILLT_v16s8*//*Label 204*/ 3237, |
| 2002 |
// Label 199: @3063 |
2002 |
// Label 199: @3063 |
| 2003 |
GIM_Try, /*On fail goto*//*Label 206*/ 3108, |
2003 |
GIM_Try, /*On fail goto*//*Label 206*/ 3108, |
| 2004 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
2004 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 2005 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
2005 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 2006 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2006 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2007 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2007 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2008 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2008 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2009 |
GIM_Try, /*On fail goto*//*Label 207*/ 3096, // Rule ID 317 // |
2009 |
GIM_Try, /*On fail goto*//*Label 207*/ 3096, // Rule ID 317 // |
| 2010 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
2010 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 2011 |
// (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2011 |
// (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2012 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU, |
2012 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU, |
| 2013 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2013 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2014 |
// GIR_Coverage, 317, |
2014 |
// GIR_Coverage, 317, |
| 2015 |
GIR_Done, |
2015 |
GIR_Done, |
| 2016 |
// Label 207: @3096 |
2016 |
// Label 207: @3096 |
| 2017 |
GIM_Try, /*On fail goto*//*Label 208*/ 3107, // Rule ID 1166 // |
2017 |
GIM_Try, /*On fail goto*//*Label 208*/ 3107, // Rule ID 1166 // |
| 2018 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
2018 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 2019 |
// (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2019 |
// (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2020 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU_MMR6, |
2020 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU_MMR6, |
| 2021 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2021 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2022 |
// GIR_Coverage, 1166, |
2022 |
// GIR_Coverage, 1166, |
| 2023 |
GIR_Done, |
2023 |
GIR_Done, |
| 2024 |
// Label 208: @3107 |
2024 |
// Label 208: @3107 |
| 2025 |
GIM_Reject, |
2025 |
GIM_Reject, |
| 2026 |
// Label 206: @3108 |
2026 |
// Label 206: @3108 |
| 2027 |
GIM_Reject, |
2027 |
GIM_Reject, |
| 2028 |
// Label 200: @3109 |
2028 |
// Label 200: @3109 |
| 2029 |
GIM_Try, /*On fail goto*//*Label 209*/ 3140, // Rule ID 332 // |
2029 |
GIM_Try, /*On fail goto*//*Label 209*/ 3140, // Rule ID 332 // |
| 2030 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
2030 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
| 2031 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
2031 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 2032 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
2032 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 2033 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
2033 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 2034 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
2034 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 2035 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
2035 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 2036 |
// (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
2036 |
// (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 2037 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU, |
2037 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU, |
| 2038 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2038 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2039 |
// GIR_Coverage, 332, |
2039 |
// GIR_Coverage, 332, |
| 2040 |
GIR_Done, |
2040 |
GIR_Done, |
| 2041 |
// Label 209: @3140 |
2041 |
// Label 209: @3140 |
| 2042 |
GIM_Reject, |
2042 |
GIM_Reject, |
| 2043 |
// Label 201: @3141 |
2043 |
// Label 201: @3141 |
| 2044 |
GIM_Try, /*On fail goto*//*Label 210*/ 3172, // Rule ID 879 // |
2044 |
GIM_Try, /*On fail goto*//*Label 210*/ 3172, // Rule ID 879 // |
| 2045 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2045 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2046 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
2046 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 2047 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
2047 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 2048 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
2048 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 2049 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
2049 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 2050 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
2050 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 2051 |
// (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
2051 |
// (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 2052 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_D, |
2052 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_D, |
| 2053 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2053 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2054 |
// GIR_Coverage, 879, |
2054 |
// GIR_Coverage, 879, |
| 2055 |
GIR_Done, |
2055 |
GIR_Done, |
| 2056 |
// Label 210: @3172 |
2056 |
// Label 210: @3172 |
| 2057 |
GIM_Reject, |
2057 |
GIM_Reject, |
| 2058 |
// Label 202: @3173 |
2058 |
// Label 202: @3173 |
| 2059 |
GIM_Try, /*On fail goto*//*Label 211*/ 3204, // Rule ID 878 // |
2059 |
GIM_Try, /*On fail goto*//*Label 211*/ 3204, // Rule ID 878 // |
| 2060 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2060 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2061 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
2061 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2062 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
2062 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2063 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
2063 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 2064 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
2064 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 2065 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
2065 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 2066 |
// (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
2066 |
// (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 2067 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_W, |
2067 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_W, |
| 2068 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2068 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2069 |
// GIR_Coverage, 878, |
2069 |
// GIR_Coverage, 878, |
| 2070 |
GIR_Done, |
2070 |
GIR_Done, |
| 2071 |
// Label 211: @3204 |
2071 |
// Label 211: @3204 |
| 2072 |
GIM_Reject, |
2072 |
GIM_Reject, |
| 2073 |
// Label 203: @3205 |
2073 |
// Label 203: @3205 |
| 2074 |
GIM_Try, /*On fail goto*//*Label 212*/ 3236, // Rule ID 877 // |
2074 |
GIM_Try, /*On fail goto*//*Label 212*/ 3236, // Rule ID 877 // |
| 2075 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2075 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2076 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
2076 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2077 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
2077 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 2078 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
2078 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 2079 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
2079 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 2080 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
2080 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 2081 |
// (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
2081 |
// (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 2082 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_H, |
2082 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_H, |
| 2083 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2083 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2084 |
// GIR_Coverage, 877, |
2084 |
// GIR_Coverage, 877, |
| 2085 |
GIR_Done, |
2085 |
GIR_Done, |
| 2086 |
// Label 212: @3236 |
2086 |
// Label 212: @3236 |
| 2087 |
GIM_Reject, |
2087 |
GIM_Reject, |
| 2088 |
// Label 204: @3237 |
2088 |
// Label 204: @3237 |
| 2089 |
GIM_Try, /*On fail goto*//*Label 213*/ 3268, // Rule ID 876 // |
2089 |
GIM_Try, /*On fail goto*//*Label 213*/ 3268, // Rule ID 876 // |
| 2090 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2090 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2091 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
2091 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2092 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
2092 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2093 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
2093 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 2094 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
2094 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 2095 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
2095 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 2096 |
// (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
2096 |
// (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 2097 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_B, |
2097 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_B, |
| 2098 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2098 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2099 |
// GIR_Coverage, 876, |
2099 |
// GIR_Coverage, 876, |
| 2100 |
GIR_Done, |
2100 |
GIR_Done, |
| 2101 |
// Label 213: @3268 |
2101 |
// Label 213: @3268 |
| 2102 |
GIM_Reject, |
2102 |
GIM_Reject, |
| 2103 |
// Label 205: @3269 |
2103 |
// Label 205: @3269 |
| 2104 |
GIM_Reject, |
2104 |
GIM_Reject, |
| 2105 |
// Label 7: @3270 |
2105 |
// Label 7: @3270 |
| 2106 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 220*/ 3756, |
2106 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 220*/ 3756, |
| 2107 |
/*GILLT_s32*//*Label 214*/ 3284, |
2107 |
/*GILLT_s32*//*Label 214*/ 3284, |
| 2108 |
/*GILLT_s64*//*Label 215*/ 3540, 0, |
2108 |
/*GILLT_s64*//*Label 215*/ 3540, 0, |
| 2109 |
/*GILLT_v2s64*//*Label 216*/ 3628, 0, |
2109 |
/*GILLT_v2s64*//*Label 216*/ 3628, 0, |
| 2110 |
/*GILLT_v4s32*//*Label 217*/ 3660, |
2110 |
/*GILLT_v4s32*//*Label 217*/ 3660, |
| 2111 |
/*GILLT_v8s16*//*Label 218*/ 3692, |
2111 |
/*GILLT_v8s16*//*Label 218*/ 3692, |
| 2112 |
/*GILLT_v16s8*//*Label 219*/ 3724, |
2112 |
/*GILLT_v16s8*//*Label 219*/ 3724, |
| 2113 |
// Label 214: @3284 |
2113 |
// Label 214: @3284 |
| 2114 |
GIM_Try, /*On fail goto*//*Label 221*/ 3539, |
2114 |
GIM_Try, /*On fail goto*//*Label 221*/ 3539, |
| 2115 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
2115 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 2116 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
2116 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 2117 |
GIM_Try, /*On fail goto*//*Label 222*/ 3337, // Rule ID 41 // |
2117 |
GIM_Try, /*On fail goto*//*Label 222*/ 3337, // Rule ID 41 // |
| 2118 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
2118 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 2119 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2119 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2120 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2120 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2121 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
2121 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2122 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
2122 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 2123 |
GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_APInt_Predicate_imm32ZExt16, |
2123 |
GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_APInt_Predicate_imm32ZExt16, |
| 2124 |
// MIs[1] Operand 1 |
2124 |
// MIs[1] Operand 1 |
| 2125 |
// No operand predicates |
2125 |
// No operand predicates |
| 2126 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
2126 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2127 |
// (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$imm16) => (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16) |
2127 |
// (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$imm16) => (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16) |
| 2128 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDi, |
2128 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDi, |
| 2129 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
2129 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 2130 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
2130 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 2131 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
2131 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 2132 |
GIR_EraseFromParent, /*InsnID*/0, |
2132 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2133 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2133 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2134 |
// GIR_Coverage, 41, |
2134 |
// GIR_Coverage, 41, |
| 2135 |
GIR_Done, |
2135 |
GIR_Done, |
| 2136 |
// Label 222: @3337 |
2136 |
// Label 222: @3337 |
| 2137 |
GIM_Try, /*On fail goto*//*Label 223*/ 3380, // Rule ID 2126 // |
2137 |
GIM_Try, /*On fail goto*//*Label 223*/ 3380, // Rule ID 2126 // |
| 2138 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
2138 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 2139 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
2139 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 2140 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
2140 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 2141 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
2141 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2142 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
2142 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 2143 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExtAndi16, |
2143 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExtAndi16, |
| 2144 |
// MIs[1] Operand 1 |
2144 |
// MIs[1] Operand 1 |
| 2145 |
// No operand predicates |
2145 |
// No operand predicates |
| 2146 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
2146 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2147 |
// (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
2147 |
// (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
| 2148 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM, |
2148 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM, |
| 2149 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
2149 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 2150 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
2150 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 2151 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
2151 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2152 |
GIR_EraseFromParent, /*InsnID*/0, |
2152 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2153 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2153 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2154 |
// GIR_Coverage, 2126, |
2154 |
// GIR_Coverage, 2126, |
| 2155 |
GIR_Done, |
2155 |
GIR_Done, |
| 2156 |
// Label 223: @3380 |
2156 |
// Label 223: @3380 |
| 2157 |
GIM_Try, /*On fail goto*//*Label 224*/ 3423, // Rule ID 2285 // |
2157 |
GIM_Try, /*On fail goto*//*Label 224*/ 3423, // Rule ID 2285 // |
| 2158 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
2158 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 2159 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
2159 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 2160 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
2160 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 2161 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
2161 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2162 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
2162 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 2163 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExtAndi16, |
2163 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExtAndi16, |
| 2164 |
// MIs[1] Operand 1 |
2164 |
// MIs[1] Operand 1 |
| 2165 |
// No operand predicates |
2165 |
// No operand predicates |
| 2166 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
2166 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2167 |
// (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
2167 |
// (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
| 2168 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6, |
2168 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6, |
| 2169 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
2169 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 2170 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
2170 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 2171 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
2171 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2172 |
GIR_EraseFromParent, /*InsnID*/0, |
2172 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2173 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2173 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2174 |
// GIR_Coverage, 2285, |
2174 |
// GIR_Coverage, 2285, |
| 2175 |
GIR_Done, |
2175 |
GIR_Done, |
| 2176 |
// Label 224: @3423 |
2176 |
// Label 224: @3423 |
| 2177 |
GIM_Try, /*On fail goto*//*Label 225*/ 3446, // Rule ID 51 // |
2177 |
GIM_Try, /*On fail goto*//*Label 225*/ 3446, // Rule ID 51 // |
| 2178 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
2178 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 2179 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2179 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2180 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2180 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2181 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2181 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2182 |
// (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2182 |
// (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2183 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND, |
2183 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND, |
| 2184 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2184 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2185 |
// GIR_Coverage, 51, |
2185 |
// GIR_Coverage, 51, |
| 2186 |
GIR_Done, |
2186 |
GIR_Done, |
| 2187 |
// Label 225: @3446 |
2187 |
// Label 225: @3446 |
| 2188 |
GIM_Try, /*On fail goto*//*Label 226*/ 3469, // Rule ID 1049 // |
2188 |
GIM_Try, /*On fail goto*//*Label 226*/ 3469, // Rule ID 1049 // |
| 2189 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
2189 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 2190 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
2190 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 2191 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
2191 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 2192 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
2192 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
| 2193 |
// (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
2193 |
// (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
| 2194 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND16_MM, |
2194 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND16_MM, |
| 2195 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2195 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2196 |
// GIR_Coverage, 1049, |
2196 |
// GIR_Coverage, 1049, |
| 2197 |
GIR_Done, |
2197 |
GIR_Done, |
| 2198 |
// Label 226: @3469 |
2198 |
// Label 226: @3469 |
| 2199 |
GIM_Try, /*On fail goto*//*Label 227*/ 3492, // Rule ID 1065 // |
2199 |
GIM_Try, /*On fail goto*//*Label 227*/ 3492, // Rule ID 1065 // |
| 2200 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
2200 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 2201 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2201 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2202 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2202 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2203 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2203 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2204 |
// (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2204 |
// (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2205 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MM, |
2205 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MM, |
| 2206 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2206 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2207 |
// GIR_Coverage, 1065, |
2207 |
// GIR_Coverage, 1065, |
| 2208 |
GIR_Done, |
2208 |
GIR_Done, |
| 2209 |
// Label 227: @3492 |
2209 |
// Label 227: @3492 |
| 2210 |
GIM_Try, /*On fail goto*//*Label 228*/ 3515, // Rule ID 1158 // |
2210 |
GIM_Try, /*On fail goto*//*Label 228*/ 3515, // Rule ID 1158 // |
| 2211 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
2211 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 2212 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2212 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2213 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2213 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2214 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2214 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2215 |
// (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2215 |
// (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2216 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MMR6, |
2216 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MMR6, |
| 2217 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2217 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2218 |
// GIR_Coverage, 1158, |
2218 |
// GIR_Coverage, 1158, |
| 2219 |
GIR_Done, |
2219 |
GIR_Done, |
| 2220 |
// Label 228: @3515 |
2220 |
// Label 228: @3515 |
| 2221 |
GIM_Try, /*On fail goto*//*Label 229*/ 3538, // Rule ID 1784 // |
2221 |
GIM_Try, /*On fail goto*//*Label 229*/ 3538, // Rule ID 1784 // |
| 2222 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
2222 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 2223 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
2223 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 2224 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
2224 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 2225 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
2225 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 2226 |
// (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) |
2226 |
// (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) |
| 2227 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AndRxRxRy16, |
2227 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AndRxRxRy16, |
| 2228 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2228 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2229 |
// GIR_Coverage, 1784, |
2229 |
// GIR_Coverage, 1784, |
| 2230 |
GIR_Done, |
2230 |
GIR_Done, |
| 2231 |
// Label 229: @3538 |
2231 |
// Label 229: @3538 |
| 2232 |
GIM_Reject, |
2232 |
GIM_Reject, |
| 2233 |
// Label 221: @3539 |
2233 |
// Label 221: @3539 |
| 2234 |
GIM_Reject, |
2234 |
GIM_Reject, |
| 2235 |
// Label 215: @3540 |
2235 |
// Label 215: @3540 |
| 2236 |
GIM_Try, /*On fail goto*//*Label 230*/ 3627, |
2236 |
GIM_Try, /*On fail goto*//*Label 230*/ 3627, |
| 2237 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
2237 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 2238 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
2238 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 2239 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
2239 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 2240 |
GIM_Try, /*On fail goto*//*Label 231*/ 3607, // Rule ID 257 // |
2240 |
GIM_Try, /*On fail goto*//*Label 231*/ 3607, // Rule ID 257 // |
| 2241 |
GIM_CheckFeatures, GIFBS_HasCnMips, |
2241 |
GIM_CheckFeatures, GIFBS_HasCnMips, |
| 2242 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
2242 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2243 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, |
2243 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, |
| 2244 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
2244 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2245 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
2245 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2246 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
2246 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 2247 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
2247 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 2248 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, |
2248 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, |
| 2249 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
2249 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2250 |
// (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) => (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
2250 |
// (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) => (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 2251 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu, |
2251 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu, |
| 2252 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
2252 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 2253 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
2253 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 2254 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt |
2254 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt |
| 2255 |
GIR_EraseFromParent, /*InsnID*/0, |
2255 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2256 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2256 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2257 |
// GIR_Coverage, 257, |
2257 |
// GIR_Coverage, 257, |
| 2258 |
GIR_Done, |
2258 |
GIR_Done, |
| 2259 |
// Label 231: @3607 |
2259 |
// Label 231: @3607 |
| 2260 |
GIM_Try, /*On fail goto*//*Label 232*/ 3626, // Rule ID 200 // |
2260 |
GIM_Try, /*On fail goto*//*Label 232*/ 3626, // Rule ID 200 // |
| 2261 |
GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, |
2261 |
GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, |
| 2262 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
2262 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 2263 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
2263 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 2264 |
// (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
2264 |
// (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 2265 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND64, |
2265 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND64, |
| 2266 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2266 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2267 |
// GIR_Coverage, 200, |
2267 |
// GIR_Coverage, 200, |
| 2268 |
GIR_Done, |
2268 |
GIR_Done, |
| 2269 |
// Label 232: @3626 |
2269 |
// Label 232: @3626 |
| 2270 |
GIM_Reject, |
2270 |
GIM_Reject, |
| 2271 |
// Label 230: @3627 |
2271 |
// Label 230: @3627 |
| 2272 |
GIM_Reject, |
2272 |
GIM_Reject, |
| 2273 |
// Label 216: @3628 |
2273 |
// Label 216: @3628 |
| 2274 |
GIM_Try, /*On fail goto*//*Label 233*/ 3659, // Rule ID 506 // |
2274 |
GIM_Try, /*On fail goto*//*Label 233*/ 3659, // Rule ID 506 // |
| 2275 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2275 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2276 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
2276 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 2277 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
2277 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 2278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
2278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 2279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
2279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 2280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
2280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 2281 |
// (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
2281 |
// (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 2282 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_D_PSEUDO, |
2282 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_D_PSEUDO, |
| 2283 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2283 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2284 |
// GIR_Coverage, 506, |
2284 |
// GIR_Coverage, 506, |
| 2285 |
GIR_Done, |
2285 |
GIR_Done, |
| 2286 |
// Label 233: @3659 |
2286 |
// Label 233: @3659 |
| 2287 |
GIM_Reject, |
2287 |
GIM_Reject, |
| 2288 |
// Label 217: @3660 |
2288 |
// Label 217: @3660 |
| 2289 |
GIM_Try, /*On fail goto*//*Label 234*/ 3691, // Rule ID 505 // |
2289 |
GIM_Try, /*On fail goto*//*Label 234*/ 3691, // Rule ID 505 // |
| 2290 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2290 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2291 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
2291 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2292 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
2292 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2293 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
2293 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 2294 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
2294 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 2295 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
2295 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 2296 |
// (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
2296 |
// (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 2297 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_W_PSEUDO, |
2297 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_W_PSEUDO, |
| 2298 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2298 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2299 |
// GIR_Coverage, 505, |
2299 |
// GIR_Coverage, 505, |
| 2300 |
GIR_Done, |
2300 |
GIR_Done, |
| 2301 |
// Label 234: @3691 |
2301 |
// Label 234: @3691 |
| 2302 |
GIM_Reject, |
2302 |
GIM_Reject, |
| 2303 |
// Label 218: @3692 |
2303 |
// Label 218: @3692 |
| 2304 |
GIM_Try, /*On fail goto*//*Label 235*/ 3723, // Rule ID 504 // |
2304 |
GIM_Try, /*On fail goto*//*Label 235*/ 3723, // Rule ID 504 // |
| 2305 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2305 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2306 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
2306 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2307 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
2307 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 2308 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
2308 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 2309 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
2309 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 2310 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
2310 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 2311 |
// (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
2311 |
// (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 2312 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_H_PSEUDO, |
2312 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_H_PSEUDO, |
| 2313 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2313 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2314 |
// GIR_Coverage, 504, |
2314 |
// GIR_Coverage, 504, |
| 2315 |
GIR_Done, |
2315 |
GIR_Done, |
| 2316 |
// Label 235: @3723 |
2316 |
// Label 235: @3723 |
| 2317 |
GIM_Reject, |
2317 |
GIM_Reject, |
| 2318 |
// Label 219: @3724 |
2318 |
// Label 219: @3724 |
| 2319 |
GIM_Try, /*On fail goto*//*Label 236*/ 3755, // Rule ID 503 // |
2319 |
GIM_Try, /*On fail goto*//*Label 236*/ 3755, // Rule ID 503 // |
| 2320 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2320 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2321 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
2321 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2322 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
2322 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2323 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
2323 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 2324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
2324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 2325 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
2325 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 2326 |
// (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
2326 |
// (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 2327 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V, |
2327 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V, |
| 2328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2329 |
// GIR_Coverage, 503, |
2329 |
// GIR_Coverage, 503, |
| 2330 |
GIR_Done, |
2330 |
GIR_Done, |
| 2331 |
// Label 236: @3755 |
2331 |
// Label 236: @3755 |
| 2332 |
GIM_Reject, |
2332 |
GIM_Reject, |
| 2333 |
// Label 220: @3756 |
2333 |
// Label 220: @3756 |
| 2334 |
GIM_Reject, |
2334 |
GIM_Reject, |
| 2335 |
// Label 8: @3757 |
2335 |
// Label 8: @3757 |
| 2336 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 243*/ 4101, |
2336 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 243*/ 4101, |
| 2337 |
/*GILLT_s32*//*Label 237*/ 3771, |
2337 |
/*GILLT_s32*//*Label 237*/ 3771, |
| 2338 |
/*GILLT_s64*//*Label 238*/ 3941, 0, |
2338 |
/*GILLT_s64*//*Label 238*/ 3941, 0, |
| 2339 |
/*GILLT_v2s64*//*Label 239*/ 3973, 0, |
2339 |
/*GILLT_v2s64*//*Label 239*/ 3973, 0, |
| 2340 |
/*GILLT_v4s32*//*Label 240*/ 4005, |
2340 |
/*GILLT_v4s32*//*Label 240*/ 4005, |
| 2341 |
/*GILLT_v8s16*//*Label 241*/ 4037, |
2341 |
/*GILLT_v8s16*//*Label 241*/ 4037, |
| 2342 |
/*GILLT_v16s8*//*Label 242*/ 4069, |
2342 |
/*GILLT_v16s8*//*Label 242*/ 4069, |
| 2343 |
// Label 237: @3771 |
2343 |
// Label 237: @3771 |
| 2344 |
GIM_Try, /*On fail goto*//*Label 244*/ 3940, |
2344 |
GIM_Try, /*On fail goto*//*Label 244*/ 3940, |
| 2345 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
2345 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 2346 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
2346 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 2347 |
GIM_Try, /*On fail goto*//*Label 245*/ 3824, // Rule ID 42 // |
2347 |
GIM_Try, /*On fail goto*//*Label 245*/ 3824, // Rule ID 42 // |
| 2348 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
2348 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 2349 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2349 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2350 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2350 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2351 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
2351 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2352 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
2352 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 2353 |
GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_APInt_Predicate_imm32ZExt16, |
2353 |
GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_APInt_Predicate_imm32ZExt16, |
| 2354 |
// MIs[1] Operand 1 |
2354 |
// MIs[1] Operand 1 |
| 2355 |
// No operand predicates |
2355 |
// No operand predicates |
| 2356 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
2356 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2357 |
// (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$imm16) => (ORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16) |
2357 |
// (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$imm16) => (ORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16) |
| 2358 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ORi, |
2358 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ORi, |
| 2359 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
2359 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 2360 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
2360 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 2361 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
2361 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 2362 |
GIR_EraseFromParent, /*InsnID*/0, |
2362 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2363 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2363 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2364 |
// GIR_Coverage, 42, |
2364 |
// GIR_Coverage, 42, |
| 2365 |
GIR_Done, |
2365 |
GIR_Done, |
| 2366 |
// Label 245: @3824 |
2366 |
// Label 245: @3824 |
| 2367 |
GIM_Try, /*On fail goto*//*Label 246*/ 3847, // Rule ID 52 // |
2367 |
GIM_Try, /*On fail goto*//*Label 246*/ 3847, // Rule ID 52 // |
| 2368 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
2368 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 2369 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2369 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2370 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2370 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2371 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2371 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2372 |
// (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2372 |
// (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2373 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR, |
2373 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR, |
| 2374 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2374 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2375 |
// GIR_Coverage, 52, |
2375 |
// GIR_Coverage, 52, |
| 2376 |
GIR_Done, |
2376 |
GIR_Done, |
| 2377 |
// Label 246: @3847 |
2377 |
// Label 246: @3847 |
| 2378 |
GIM_Try, /*On fail goto*//*Label 247*/ 3870, // Rule ID 1051 // |
2378 |
GIM_Try, /*On fail goto*//*Label 247*/ 3870, // Rule ID 1051 // |
| 2379 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
2379 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 2380 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
2380 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 2381 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
2381 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 2382 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
2382 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
| 2383 |
// (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
2383 |
// (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
| 2384 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR16_MM, |
2384 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR16_MM, |
| 2385 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2385 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2386 |
// GIR_Coverage, 1051, |
2386 |
// GIR_Coverage, 1051, |
| 2387 |
GIR_Done, |
2387 |
GIR_Done, |
| 2388 |
// Label 247: @3870 |
2388 |
// Label 247: @3870 |
| 2389 |
GIM_Try, /*On fail goto*//*Label 248*/ 3893, // Rule ID 1066 // |
2389 |
GIM_Try, /*On fail goto*//*Label 248*/ 3893, // Rule ID 1066 // |
| 2390 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
2390 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 2391 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2391 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2392 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2392 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2393 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2393 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2394 |
// (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2394 |
// (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2395 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MM, |
2395 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MM, |
| 2396 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2396 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2397 |
// GIR_Coverage, 1066, |
2397 |
// GIR_Coverage, 1066, |
| 2398 |
GIR_Done, |
2398 |
GIR_Done, |
| 2399 |
// Label 248: @3893 |
2399 |
// Label 248: @3893 |
| 2400 |
GIM_Try, /*On fail goto*//*Label 249*/ 3916, // Rule ID 1171 // |
2400 |
GIM_Try, /*On fail goto*//*Label 249*/ 3916, // Rule ID 1171 // |
| 2401 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
2401 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 2402 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2402 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2403 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2403 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2404 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2404 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2405 |
// (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2405 |
// (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2406 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MMR6, |
2406 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MMR6, |
| 2407 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2407 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2408 |
// GIR_Coverage, 1171, |
2408 |
// GIR_Coverage, 1171, |
| 2409 |
GIR_Done, |
2409 |
GIR_Done, |
| 2410 |
// Label 249: @3916 |
2410 |
// Label 249: @3916 |
| 2411 |
GIM_Try, /*On fail goto*//*Label 250*/ 3939, // Rule ID 1786 // |
2411 |
GIM_Try, /*On fail goto*//*Label 250*/ 3939, // Rule ID 1786 // |
| 2412 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
2412 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 2413 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
2413 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 2414 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
2414 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 2415 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
2415 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 2416 |
// (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) |
2416 |
// (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) |
| 2417 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OrRxRxRy16, |
2417 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OrRxRxRy16, |
| 2418 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2418 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2419 |
// GIR_Coverage, 1786, |
2419 |
// GIR_Coverage, 1786, |
| 2420 |
GIR_Done, |
2420 |
GIR_Done, |
| 2421 |
// Label 250: @3939 |
2421 |
// Label 250: @3939 |
| 2422 |
GIM_Reject, |
2422 |
GIM_Reject, |
| 2423 |
// Label 244: @3940 |
2423 |
// Label 244: @3940 |
| 2424 |
GIM_Reject, |
2424 |
GIM_Reject, |
| 2425 |
// Label 238: @3941 |
2425 |
// Label 238: @3941 |
| 2426 |
GIM_Try, /*On fail goto*//*Label 251*/ 3972, // Rule ID 201 // |
2426 |
GIM_Try, /*On fail goto*//*Label 251*/ 3972, // Rule ID 201 // |
| 2427 |
GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, |
2427 |
GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, |
| 2428 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
2428 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 2429 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
2429 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 2430 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
2430 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 2431 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
2431 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 2432 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
2432 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 2433 |
// (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
2433 |
// (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 2434 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR64, |
2434 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR64, |
| 2435 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2435 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2436 |
// GIR_Coverage, 201, |
2436 |
// GIR_Coverage, 201, |
| 2437 |
GIR_Done, |
2437 |
GIR_Done, |
| 2438 |
// Label 251: @3972 |
2438 |
// Label 251: @3972 |
| 2439 |
GIM_Reject, |
2439 |
GIM_Reject, |
| 2440 |
// Label 239: @3973 |
2440 |
// Label 239: @3973 |
| 2441 |
GIM_Try, /*On fail goto*//*Label 252*/ 4004, // Rule ID 912 // |
2441 |
GIM_Try, /*On fail goto*//*Label 252*/ 4004, // Rule ID 912 // |
| 2442 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2442 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2443 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
2443 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 2444 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
2444 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 2445 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
2445 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 2446 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
2446 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 2447 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
2447 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 2448 |
// (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
2448 |
// (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 2449 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_D_PSEUDO, |
2449 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_D_PSEUDO, |
| 2450 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2450 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2451 |
// GIR_Coverage, 912, |
2451 |
// GIR_Coverage, 912, |
| 2452 |
GIR_Done, |
2452 |
GIR_Done, |
| 2453 |
// Label 252: @4004 |
2453 |
// Label 252: @4004 |
| 2454 |
GIM_Reject, |
2454 |
GIM_Reject, |
| 2455 |
// Label 240: @4005 |
2455 |
// Label 240: @4005 |
| 2456 |
GIM_Try, /*On fail goto*//*Label 253*/ 4036, // Rule ID 911 // |
2456 |
GIM_Try, /*On fail goto*//*Label 253*/ 4036, // Rule ID 911 // |
| 2457 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2457 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2458 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
2458 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2459 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
2459 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2460 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
2460 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 2461 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
2461 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 2462 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
2462 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 2463 |
// (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
2463 |
// (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 2464 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_W_PSEUDO, |
2464 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_W_PSEUDO, |
| 2465 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2465 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2466 |
// GIR_Coverage, 911, |
2466 |
// GIR_Coverage, 911, |
| 2467 |
GIR_Done, |
2467 |
GIR_Done, |
| 2468 |
// Label 253: @4036 |
2468 |
// Label 253: @4036 |
| 2469 |
GIM_Reject, |
2469 |
GIM_Reject, |
| 2470 |
// Label 241: @4037 |
2470 |
// Label 241: @4037 |
| 2471 |
GIM_Try, /*On fail goto*//*Label 254*/ 4068, // Rule ID 910 // |
2471 |
GIM_Try, /*On fail goto*//*Label 254*/ 4068, // Rule ID 910 // |
| 2472 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2472 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2473 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
2473 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2474 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
2474 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 2475 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
2475 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 2476 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
2476 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 2477 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
2477 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 2478 |
// (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
2478 |
// (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 2479 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_H_PSEUDO, |
2479 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_H_PSEUDO, |
| 2480 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2480 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2481 |
// GIR_Coverage, 910, |
2481 |
// GIR_Coverage, 910, |
| 2482 |
GIR_Done, |
2482 |
GIR_Done, |
| 2483 |
// Label 254: @4068 |
2483 |
// Label 254: @4068 |
| 2484 |
GIM_Reject, |
2484 |
GIM_Reject, |
| 2485 |
// Label 242: @4069 |
2485 |
// Label 242: @4069 |
| 2486 |
GIM_Try, /*On fail goto*//*Label 255*/ 4100, // Rule ID 909 // |
2486 |
GIM_Try, /*On fail goto*//*Label 255*/ 4100, // Rule ID 909 // |
| 2487 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2487 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2488 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
2488 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2489 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
2489 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2490 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
2490 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 2491 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
2491 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 2492 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
2492 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 2493 |
// (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
2493 |
// (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 2494 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V, |
2494 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V, |
| 2495 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2495 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2496 |
// GIR_Coverage, 909, |
2496 |
// GIR_Coverage, 909, |
| 2497 |
GIR_Done, |
2497 |
GIR_Done, |
| 2498 |
// Label 255: @4100 |
2498 |
// Label 255: @4100 |
| 2499 |
GIM_Reject, |
2499 |
GIM_Reject, |
| 2500 |
// Label 243: @4101 |
2500 |
// Label 243: @4101 |
| 2501 |
GIM_Reject, |
2501 |
GIM_Reject, |
| 2502 |
// Label 9: @4102 |
2502 |
// Label 9: @4102 |
| 2503 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 262*/ 4941, |
2503 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 262*/ 4941, |
| 2504 |
/*GILLT_s32*//*Label 256*/ 4116, |
2504 |
/*GILLT_s32*//*Label 256*/ 4116, |
| 2505 |
/*GILLT_s64*//*Label 257*/ 4725, 0, |
2505 |
/*GILLT_s64*//*Label 257*/ 4725, 0, |
| 2506 |
/*GILLT_v2s64*//*Label 258*/ 4813, 0, |
2506 |
/*GILLT_v2s64*//*Label 258*/ 4813, 0, |
| 2507 |
/*GILLT_v4s32*//*Label 259*/ 4845, |
2507 |
/*GILLT_v4s32*//*Label 259*/ 4845, |
| 2508 |
/*GILLT_v8s16*//*Label 260*/ 4877, |
2508 |
/*GILLT_v8s16*//*Label 260*/ 4877, |
| 2509 |
/*GILLT_v16s8*//*Label 261*/ 4909, |
2509 |
/*GILLT_v16s8*//*Label 261*/ 4909, |
| 2510 |
// Label 256: @4116 |
2510 |
// Label 256: @4116 |
| 2511 |
GIM_Try, /*On fail goto*//*Label 263*/ 4724, |
2511 |
GIM_Try, /*On fail goto*//*Label 263*/ 4724, |
| 2512 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
2512 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 2513 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
2513 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 2514 |
GIM_Try, /*On fail goto*//*Label 264*/ 4183, // Rule ID 54 // |
2514 |
GIM_Try, /*On fail goto*//*Label 264*/ 4183, // Rule ID 54 // |
| 2515 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
2515 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 2516 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2516 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2517 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
2517 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2518 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, |
2518 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, |
| 2519 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
2519 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2520 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
2520 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2521 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2521 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2522 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2522 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2523 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
2523 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 2524 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
2524 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2525 |
// (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2525 |
// (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2526 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
2526 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
| 2527 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
2527 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 2528 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
2528 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 2529 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt |
2529 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt |
| 2530 |
GIR_EraseFromParent, /*InsnID*/0, |
2530 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2531 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2531 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2532 |
// GIR_Coverage, 54, |
2532 |
// GIR_Coverage, 54, |
| 2533 |
GIR_Done, |
2533 |
GIR_Done, |
| 2534 |
// Label 264: @4183 |
2534 |
// Label 264: @4183 |
| 2535 |
GIM_Try, /*On fail goto*//*Label 265*/ 4240, // Rule ID 1068 // |
2535 |
GIM_Try, /*On fail goto*//*Label 265*/ 4240, // Rule ID 1068 // |
| 2536 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
2536 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 2537 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2537 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2538 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
2538 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2539 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, |
2539 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, |
| 2540 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
2540 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2541 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
2541 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2542 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2542 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2543 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2543 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2544 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
2544 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 2545 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
2545 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2546 |
// (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2546 |
// (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2547 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM, |
2547 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM, |
| 2548 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
2548 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 2549 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
2549 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 2550 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt |
2550 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt |
| 2551 |
GIR_EraseFromParent, /*InsnID*/0, |
2551 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2552 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2552 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2553 |
// GIR_Coverage, 1068, |
2553 |
// GIR_Coverage, 1068, |
| 2554 |
GIR_Done, |
2554 |
GIR_Done, |
| 2555 |
// Label 265: @4240 |
2555 |
// Label 265: @4240 |
| 2556 |
GIM_Try, /*On fail goto*//*Label 266*/ 4297, // Rule ID 1170 // |
2556 |
GIM_Try, /*On fail goto*//*Label 266*/ 4297, // Rule ID 1170 // |
| 2557 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
2557 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 2558 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2558 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2559 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
2559 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2560 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, |
2560 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, |
| 2561 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
2561 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2562 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
2562 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2563 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2563 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2564 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2564 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2565 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
2565 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 2566 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
2566 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2567 |
// (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2567 |
// (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2568 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
2568 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
| 2569 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
2569 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 2570 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
2570 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 2571 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt |
2571 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt |
| 2572 |
GIR_EraseFromParent, /*InsnID*/0, |
2572 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2573 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2573 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2574 |
// GIR_Coverage, 1170, |
2574 |
// GIR_Coverage, 1170, |
| 2575 |
GIR_Done, |
2575 |
GIR_Done, |
| 2576 |
// Label 266: @4297 |
2576 |
// Label 266: @4297 |
| 2577 |
GIM_Try, /*On fail goto*//*Label 267*/ 4329, // Rule ID 1197 // |
2577 |
GIM_Try, /*On fail goto*//*Label 267*/ 4329, // Rule ID 1197 // |
| 2578 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
2578 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 2579 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
2579 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 2580 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
2580 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 2581 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
2581 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 2582 |
// (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs) |
2582 |
// (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs) |
| 2583 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6, |
2583 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6, |
| 2584 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
2584 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 2585 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
2585 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 2586 |
GIR_EraseFromParent, /*InsnID*/0, |
2586 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2587 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2587 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2588 |
// GIR_Coverage, 1197, |
2588 |
// GIR_Coverage, 1197, |
| 2589 |
GIR_Done, |
2589 |
GIR_Done, |
| 2590 |
// Label 267: @4329 |
2590 |
// Label 267: @4329 |
| 2591 |
GIM_Try, /*On fail goto*//*Label 268*/ 4361, // Rule ID 1050 // |
2591 |
GIM_Try, /*On fail goto*//*Label 268*/ 4361, // Rule ID 1050 // |
| 2592 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
2592 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 2593 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
2593 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 2594 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
2594 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 2595 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
2595 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 2596 |
// (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs) |
2596 |
// (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs) |
| 2597 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM, |
2597 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM, |
| 2598 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
2598 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 2599 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
2599 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 2600 |
GIR_EraseFromParent, /*InsnID*/0, |
2600 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2601 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2601 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2602 |
// GIR_Coverage, 1050, |
2602 |
// GIR_Coverage, 1050, |
| 2603 |
GIR_Done, |
2603 |
GIR_Done, |
| 2604 |
// Label 268: @4361 |
2604 |
// Label 268: @4361 |
| 2605 |
GIM_Try, /*On fail goto*//*Label 269*/ 4397, // Rule ID 1385 // |
2605 |
GIM_Try, /*On fail goto*//*Label 269*/ 4397, // Rule ID 1385 // |
| 2606 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
2606 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 2607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2608 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2608 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2609 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
2609 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 2610 |
// (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] }) |
2610 |
// (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] }) |
| 2611 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
2611 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
| 2612 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
2612 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 2613 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
2613 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
| 2614 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
2614 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 2615 |
GIR_EraseFromParent, /*InsnID*/0, |
2615 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2616 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2616 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2617 |
// GIR_Coverage, 1385, |
2617 |
// GIR_Coverage, 1385, |
| 2618 |
GIR_Done, |
2618 |
GIR_Done, |
| 2619 |
// Label 269: @4397 |
2619 |
// Label 269: @4397 |
| 2620 |
GIM_Try, /*On fail goto*//*Label 270*/ 4429, // Rule ID 1781 // |
2620 |
GIM_Try, /*On fail goto*//*Label 270*/ 4429, // Rule ID 1781 // |
| 2621 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
2621 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 2622 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
2622 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 2623 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
2623 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 2624 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
2624 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 2625 |
// (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] }) => (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r) |
2625 |
// (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] }) => (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r) |
| 2626 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NotRxRy16, |
2626 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NotRxRy16, |
| 2627 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx |
2627 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx |
| 2628 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // r |
2628 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // r |
| 2629 |
GIR_EraseFromParent, /*InsnID*/0, |
2629 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2630 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2630 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2631 |
// GIR_Coverage, 1781, |
2631 |
// GIR_Coverage, 1781, |
| 2632 |
GIR_Done, |
2632 |
GIR_Done, |
| 2633 |
// Label 270: @4429 |
2633 |
// Label 270: @4429 |
| 2634 |
GIM_Try, /*On fail goto*//*Label 271*/ 4461, // Rule ID 2121 // |
2634 |
GIM_Try, /*On fail goto*//*Label 271*/ 4461, // Rule ID 2121 // |
| 2635 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
2635 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 2636 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
2636 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 2637 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
2637 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 2638 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
2638 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 2639 |
// (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in) |
2639 |
// (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in) |
| 2640 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM, |
2640 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM, |
| 2641 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
2641 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 2642 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
2642 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
| 2643 |
GIR_EraseFromParent, /*InsnID*/0, |
2643 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2644 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2644 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2645 |
// GIR_Coverage, 2121, |
2645 |
// GIR_Coverage, 2121, |
| 2646 |
GIR_Done, |
2646 |
GIR_Done, |
| 2647 |
// Label 271: @4461 |
2647 |
// Label 271: @4461 |
| 2648 |
GIM_Try, /*On fail goto*//*Label 272*/ 4497, // Rule ID 2122 // |
2648 |
GIM_Try, /*On fail goto*//*Label 272*/ 4497, // Rule ID 2122 // |
| 2649 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
2649 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 2650 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2650 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2651 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2651 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2652 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
2652 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 2653 |
// (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] }) |
2653 |
// (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] }) |
| 2654 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM, |
2654 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM, |
| 2655 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
2655 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 2656 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
2656 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
| 2657 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
2657 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 2658 |
GIR_EraseFromParent, /*InsnID*/0, |
2658 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2659 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2659 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2660 |
// GIR_Coverage, 2122, |
2660 |
// GIR_Coverage, 2122, |
| 2661 |
GIR_Done, |
2661 |
GIR_Done, |
| 2662 |
// Label 272: @4497 |
2662 |
// Label 272: @4497 |
| 2663 |
GIM_Try, /*On fail goto*//*Label 273*/ 4529, // Rule ID 2288 // |
2663 |
GIM_Try, /*On fail goto*//*Label 273*/ 4529, // Rule ID 2288 // |
| 2664 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
2664 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 2665 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
2665 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 2666 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
2666 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 2667 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
2667 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 2668 |
// (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in) |
2668 |
// (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in) |
| 2669 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6, |
2669 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6, |
| 2670 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
2670 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 2671 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
2671 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
| 2672 |
GIR_EraseFromParent, /*InsnID*/0, |
2672 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2673 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2673 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2674 |
// GIR_Coverage, 2288, |
2674 |
// GIR_Coverage, 2288, |
| 2675 |
GIR_Done, |
2675 |
GIR_Done, |
| 2676 |
// Label 273: @4529 |
2676 |
// Label 273: @4529 |
| 2677 |
GIM_Try, /*On fail goto*//*Label 274*/ 4565, // Rule ID 2289 // |
2677 |
GIM_Try, /*On fail goto*//*Label 274*/ 4565, // Rule ID 2289 // |
| 2678 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
2678 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 2679 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2679 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2680 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2680 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2681 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
2681 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 2682 |
// (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] }) |
2682 |
// (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] }) |
| 2683 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
2683 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
| 2684 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
2684 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 2685 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
2685 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
| 2686 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
2686 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 2687 |
GIR_EraseFromParent, /*InsnID*/0, |
2687 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2688 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2688 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2689 |
// GIR_Coverage, 2289, |
2689 |
// GIR_Coverage, 2289, |
| 2690 |
GIR_Done, |
2690 |
GIR_Done, |
| 2691 |
// Label 274: @4565 |
2691 |
// Label 274: @4565 |
| 2692 |
GIM_Try, /*On fail goto*//*Label 275*/ 4608, // Rule ID 43 // |
2692 |
GIM_Try, /*On fail goto*//*Label 275*/ 4608, // Rule ID 43 // |
| 2693 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
2693 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 2694 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2694 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2695 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2695 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2696 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
2696 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2697 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
2697 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 2698 |
GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_APInt_Predicate_imm32ZExt16, |
2698 |
GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_APInt_Predicate_imm32ZExt16, |
| 2699 |
// MIs[1] Operand 1 |
2699 |
// MIs[1] Operand 1 |
| 2700 |
// No operand predicates |
2700 |
// No operand predicates |
| 2701 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
2701 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2702 |
// (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$imm16) => (XORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16) |
2702 |
// (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$imm16) => (XORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16) |
| 2703 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
2703 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
| 2704 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
2704 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 2705 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
2705 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 2706 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
2706 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 2707 |
GIR_EraseFromParent, /*InsnID*/0, |
2707 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2708 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2708 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2709 |
// GIR_Coverage, 43, |
2709 |
// GIR_Coverage, 43, |
| 2710 |
GIR_Done, |
2710 |
GIR_Done, |
| 2711 |
// Label 275: @4608 |
2711 |
// Label 275: @4608 |
| 2712 |
GIM_Try, /*On fail goto*//*Label 276*/ 4631, // Rule ID 53 // |
2712 |
GIM_Try, /*On fail goto*//*Label 276*/ 4631, // Rule ID 53 // |
| 2713 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
2713 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 2714 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2714 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2715 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2715 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2716 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2716 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2717 |
// (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2717 |
// (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2718 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR, |
2718 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR, |
| 2719 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2719 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2720 |
// GIR_Coverage, 53, |
2720 |
// GIR_Coverage, 53, |
| 2721 |
GIR_Done, |
2721 |
GIR_Done, |
| 2722 |
// Label 276: @4631 |
2722 |
// Label 276: @4631 |
| 2723 |
GIM_Try, /*On fail goto*//*Label 277*/ 4654, // Rule ID 1053 // |
2723 |
GIM_Try, /*On fail goto*//*Label 277*/ 4654, // Rule ID 1053 // |
| 2724 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
2724 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 2725 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
2725 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 2726 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
2726 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 2727 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
2727 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID, |
| 2728 |
// (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
2728 |
// (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) |
| 2729 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR16_MM, |
2729 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR16_MM, |
| 2730 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2730 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2731 |
// GIR_Coverage, 1053, |
2731 |
// GIR_Coverage, 1053, |
| 2732 |
GIR_Done, |
2732 |
GIR_Done, |
| 2733 |
// Label 277: @4654 |
2733 |
// Label 277: @4654 |
| 2734 |
GIM_Try, /*On fail goto*//*Label 278*/ 4677, // Rule ID 1067 // |
2734 |
GIM_Try, /*On fail goto*//*Label 278*/ 4677, // Rule ID 1067 // |
| 2735 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
2735 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 2736 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2736 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2737 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2737 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2738 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2738 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2739 |
// (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2739 |
// (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2740 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MM, |
2740 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MM, |
| 2741 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2741 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2742 |
// GIR_Coverage, 1067, |
2742 |
// GIR_Coverage, 1067, |
| 2743 |
GIR_Done, |
2743 |
GIR_Done, |
| 2744 |
// Label 278: @4677 |
2744 |
// Label 278: @4677 |
| 2745 |
GIM_Try, /*On fail goto*//*Label 279*/ 4700, // Rule ID 1174 // |
2745 |
GIM_Try, /*On fail goto*//*Label 279*/ 4700, // Rule ID 1174 // |
| 2746 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
2746 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 2747 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
2747 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 2748 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2748 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2749 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2749 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2750 |
// (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
2750 |
// (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 2751 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MMR6, |
2751 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MMR6, |
| 2752 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2752 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2753 |
// GIR_Coverage, 1174, |
2753 |
// GIR_Coverage, 1174, |
| 2754 |
GIR_Done, |
2754 |
GIR_Done, |
| 2755 |
// Label 279: @4700 |
2755 |
// Label 279: @4700 |
| 2756 |
GIM_Try, /*On fail goto*//*Label 280*/ 4723, // Rule ID 1788 // |
2756 |
GIM_Try, /*On fail goto*//*Label 280*/ 4723, // Rule ID 1788 // |
| 2757 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
2757 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 2758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
2758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 2759 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
2759 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 2760 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
2760 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 2761 |
// (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) |
2761 |
// (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) |
| 2762 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XorRxRxRy16, |
2762 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XorRxRxRy16, |
| 2763 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2763 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2764 |
// GIR_Coverage, 1788, |
2764 |
// GIR_Coverage, 1788, |
| 2765 |
GIR_Done, |
2765 |
GIR_Done, |
| 2766 |
// Label 280: @4723 |
2766 |
// Label 280: @4723 |
| 2767 |
GIM_Reject, |
2767 |
GIM_Reject, |
| 2768 |
// Label 263: @4724 |
2768 |
// Label 263: @4724 |
| 2769 |
GIM_Reject, |
2769 |
GIM_Reject, |
| 2770 |
// Label 257: @4725 |
2770 |
// Label 257: @4725 |
| 2771 |
GIM_Try, /*On fail goto*//*Label 281*/ 4812, |
2771 |
GIM_Try, /*On fail goto*//*Label 281*/ 4812, |
| 2772 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
2772 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 2773 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
2773 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 2774 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
2774 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 2775 |
GIM_Try, /*On fail goto*//*Label 282*/ 4792, // Rule ID 203 // |
2775 |
GIM_Try, /*On fail goto*//*Label 282*/ 4792, // Rule ID 203 // |
| 2776 |
GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, |
2776 |
GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, |
| 2777 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
2777 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2778 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, |
2778 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, |
| 2779 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
2779 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 2780 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
2780 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 2781 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
2781 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 2782 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
2782 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 2783 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
2783 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, |
| 2784 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
2784 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 2785 |
// (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] }) => (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
2785 |
// (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] }) => (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 2786 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR64, |
2786 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR64, |
| 2787 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
2787 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 2788 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
2788 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 2789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt |
2789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt |
| 2790 |
GIR_EraseFromParent, /*InsnID*/0, |
2790 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2791 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2791 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2792 |
// GIR_Coverage, 203, |
2792 |
// GIR_Coverage, 203, |
| 2793 |
GIR_Done, |
2793 |
GIR_Done, |
| 2794 |
// Label 282: @4792 |
2794 |
// Label 282: @4792 |
| 2795 |
GIM_Try, /*On fail goto*//*Label 283*/ 4811, // Rule ID 202 // |
2795 |
GIM_Try, /*On fail goto*//*Label 283*/ 4811, // Rule ID 202 // |
| 2796 |
GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, |
2796 |
GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, |
| 2797 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
2797 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 2798 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
2798 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 2799 |
// (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
2799 |
// (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 2800 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR64, |
2800 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR64, |
| 2801 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2801 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2802 |
// GIR_Coverage, 202, |
2802 |
// GIR_Coverage, 202, |
| 2803 |
GIR_Done, |
2803 |
GIR_Done, |
| 2804 |
// Label 283: @4811 |
2804 |
// Label 283: @4811 |
| 2805 |
GIM_Reject, |
2805 |
GIM_Reject, |
| 2806 |
// Label 281: @4812 |
2806 |
// Label 281: @4812 |
| 2807 |
GIM_Reject, |
2807 |
GIM_Reject, |
| 2808 |
// Label 258: @4813 |
2808 |
// Label 258: @4813 |
| 2809 |
GIM_Try, /*On fail goto*//*Label 284*/ 4844, // Rule ID 1028 // |
2809 |
GIM_Try, /*On fail goto*//*Label 284*/ 4844, // Rule ID 1028 // |
| 2810 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2810 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2811 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
2811 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 2812 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
2812 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 2813 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
2813 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 2814 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
2814 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 2815 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
2815 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 2816 |
// (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
2816 |
// (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 2817 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_D_PSEUDO, |
2817 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_D_PSEUDO, |
| 2818 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2818 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2819 |
// GIR_Coverage, 1028, |
2819 |
// GIR_Coverage, 1028, |
| 2820 |
GIR_Done, |
2820 |
GIR_Done, |
| 2821 |
// Label 284: @4844 |
2821 |
// Label 284: @4844 |
| 2822 |
GIM_Reject, |
2822 |
GIM_Reject, |
| 2823 |
// Label 259: @4845 |
2823 |
// Label 259: @4845 |
| 2824 |
GIM_Try, /*On fail goto*//*Label 285*/ 4876, // Rule ID 1027 // |
2824 |
GIM_Try, /*On fail goto*//*Label 285*/ 4876, // Rule ID 1027 // |
| 2825 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2825 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2826 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
2826 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2827 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
2827 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2828 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
2828 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 2829 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
2829 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 2830 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
2830 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 2831 |
// (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
2831 |
// (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 2832 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_W_PSEUDO, |
2832 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_W_PSEUDO, |
| 2833 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2833 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2834 |
// GIR_Coverage, 1027, |
2834 |
// GIR_Coverage, 1027, |
| 2835 |
GIR_Done, |
2835 |
GIR_Done, |
| 2836 |
// Label 285: @4876 |
2836 |
// Label 285: @4876 |
| 2837 |
GIM_Reject, |
2837 |
GIM_Reject, |
| 2838 |
// Label 260: @4877 |
2838 |
// Label 260: @4877 |
| 2839 |
GIM_Try, /*On fail goto*//*Label 286*/ 4908, // Rule ID 1026 // |
2839 |
GIM_Try, /*On fail goto*//*Label 286*/ 4908, // Rule ID 1026 // |
| 2840 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2840 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2841 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
2841 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2842 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
2842 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 2843 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
2843 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 2844 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
2844 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 2845 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
2845 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 2846 |
// (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
2846 |
// (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 2847 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_H_PSEUDO, |
2847 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_H_PSEUDO, |
| 2848 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2848 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2849 |
// GIR_Coverage, 1026, |
2849 |
// GIR_Coverage, 1026, |
| 2850 |
GIR_Done, |
2850 |
GIR_Done, |
| 2851 |
// Label 286: @4908 |
2851 |
// Label 286: @4908 |
| 2852 |
GIM_Reject, |
2852 |
GIM_Reject, |
| 2853 |
// Label 261: @4909 |
2853 |
// Label 261: @4909 |
| 2854 |
GIM_Try, /*On fail goto*//*Label 287*/ 4940, // Rule ID 1025 // |
2854 |
GIM_Try, /*On fail goto*//*Label 287*/ 4940, // Rule ID 1025 // |
| 2855 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2855 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2856 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
2856 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2857 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
2857 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2858 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
2858 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 2859 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
2859 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 2860 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
2860 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 2861 |
// (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
2861 |
// (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 2862 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V, |
2862 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V, |
| 2863 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2863 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2864 |
// GIR_Coverage, 1025, |
2864 |
// GIR_Coverage, 1025, |
| 2865 |
GIR_Done, |
2865 |
GIR_Done, |
| 2866 |
// Label 287: @4940 |
2866 |
// Label 287: @4940 |
| 2867 |
GIM_Reject, |
2867 |
GIM_Reject, |
| 2868 |
// Label 262: @4941 |
2868 |
// Label 262: @4941 |
| 2869 |
GIM_Reject, |
2869 |
GIM_Reject, |
| 2870 |
// Label 10: @4942 |
2870 |
// Label 10: @4942 |
| 2871 |
GIM_Try, /*On fail goto*//*Label 288*/ 5006, |
2871 |
GIM_Try, /*On fail goto*//*Label 288*/ 5006, |
| 2872 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
2872 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 2873 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
2873 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 2874 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
2874 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 2875 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
2875 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 2876 |
GIM_Try, /*On fail goto*//*Label 289*/ 4982, // Rule ID 174 // |
2876 |
GIM_Try, /*On fail goto*//*Label 289*/ 4982, // Rule ID 174 // |
| 2877 |
GIM_CheckFeatures, GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode, |
2877 |
GIM_CheckFeatures, GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode, |
| 2878 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
2878 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 2879 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2879 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2880 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2880 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2881 |
// (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) |
2881 |
// (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) |
| 2882 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::BuildPairF64, |
2882 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::BuildPairF64, |
| 2883 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2883 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2884 |
// GIR_Coverage, 174, |
2884 |
// GIR_Coverage, 174, |
| 2885 |
GIR_Done, |
2885 |
GIR_Done, |
| 2886 |
// Label 289: @4982 |
2886 |
// Label 289: @4982 |
| 2887 |
GIM_Try, /*On fail goto*//*Label 290*/ 5005, // Rule ID 175 // |
2887 |
GIM_Try, /*On fail goto*//*Label 290*/ 5005, // Rule ID 175 // |
| 2888 |
GIM_CheckFeatures, GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode, |
2888 |
GIM_CheckFeatures, GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode, |
| 2889 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
2889 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 2890 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2890 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2891 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
2891 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 2892 |
// (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64_64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) |
2892 |
// (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) => (BuildPairF64_64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) |
| 2893 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::BuildPairF64_64, |
2893 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::BuildPairF64_64, |
| 2894 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2894 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2895 |
// GIR_Coverage, 175, |
2895 |
// GIR_Coverage, 175, |
| 2896 |
GIR_Done, |
2896 |
GIR_Done, |
| 2897 |
// Label 290: @5005 |
2897 |
// Label 290: @5005 |
| 2898 |
GIM_Reject, |
2898 |
GIM_Reject, |
| 2899 |
// Label 288: @5006 |
2899 |
// Label 288: @5006 |
| 2900 |
GIM_Reject, |
2900 |
GIM_Reject, |
| 2901 |
// Label 11: @5007 |
2901 |
// Label 11: @5007 |
| 2902 |
GIM_Try, /*On fail goto*//*Label 291*/ 5083, |
2902 |
GIM_Try, /*On fail goto*//*Label 291*/ 5083, |
| 2903 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
2903 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 2904 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
2904 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 2905 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
2905 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 2906 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
2906 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 2907 |
GIM_Try, /*On fail goto*//*Label 292*/ 5053, // Rule ID 707 // |
2907 |
GIM_Try, /*On fail goto*//*Label 292*/ 5053, // Rule ID 707 // |
| 2908 |
GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc, |
2908 |
GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc, |
| 2909 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
2909 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 2910 |
// MIs[0] rs |
2910 |
// MIs[0] rs |
| 2911 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
2911 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2912 |
// (build_vector:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rs) => (FILL_D:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs) |
2912 |
// (build_vector:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rs) => (FILL_D:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs) |
| 2913 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_D, |
2913 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_D, |
| 2914 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
2914 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 2915 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
2915 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 2916 |
GIR_EraseFromParent, /*InsnID*/0, |
2916 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2917 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2917 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2918 |
// GIR_Coverage, 707, |
2918 |
// GIR_Coverage, 707, |
| 2919 |
GIR_Done, |
2919 |
GIR_Done, |
| 2920 |
// Label 292: @5053 |
2920 |
// Label 292: @5053 |
| 2921 |
GIM_Try, /*On fail goto*//*Label 293*/ 5082, // Rule ID 709 // |
2921 |
GIM_Try, /*On fail goto*//*Label 293*/ 5082, // Rule ID 709 // |
| 2922 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2922 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2923 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
2923 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 2924 |
// MIs[0] fs |
2924 |
// MIs[0] fs |
| 2925 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
2925 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2926 |
// (build_vector:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$fs) => (FILL_FD_PSEUDO:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs) |
2926 |
// (build_vector:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$fs) => (FILL_FD_PSEUDO:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs) |
| 2927 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_FD_PSEUDO, |
2927 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_FD_PSEUDO, |
| 2928 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
2928 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 2929 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs |
2929 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs |
| 2930 |
GIR_EraseFromParent, /*InsnID*/0, |
2930 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2931 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2931 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2932 |
// GIR_Coverage, 709, |
2932 |
// GIR_Coverage, 709, |
| 2933 |
GIR_Done, |
2933 |
GIR_Done, |
| 2934 |
// Label 293: @5082 |
2934 |
// Label 293: @5082 |
| 2935 |
GIM_Reject, |
2935 |
GIM_Reject, |
| 2936 |
// Label 291: @5083 |
2936 |
// Label 291: @5083 |
| 2937 |
GIM_Try, /*On fail goto*//*Label 294*/ 5179, |
2937 |
GIM_Try, /*On fail goto*//*Label 294*/ 5179, |
| 2938 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
2938 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 2939 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
2939 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 2940 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
2940 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 2941 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
2941 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 2942 |
GIM_Try, /*On fail goto*//*Label 295*/ 5139, // Rule ID 706 // |
2942 |
GIM_Try, /*On fail goto*//*Label 295*/ 5139, // Rule ID 706 // |
| 2943 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2943 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2944 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2944 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2945 |
// MIs[0] rs |
2945 |
// MIs[0] rs |
| 2946 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
2946 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2947 |
// MIs[0] rs |
2947 |
// MIs[0] rs |
| 2948 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
2948 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2949 |
// MIs[0] rs |
2949 |
// MIs[0] rs |
| 2950 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
2950 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2951 |
// (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_W:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs) |
2951 |
// (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_W:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs) |
| 2952 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_W, |
2952 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_W, |
| 2953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
2953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 2954 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
2954 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 2955 |
GIR_EraseFromParent, /*InsnID*/0, |
2955 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2956 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2956 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2957 |
// GIR_Coverage, 706, |
2957 |
// GIR_Coverage, 706, |
| 2958 |
GIR_Done, |
2958 |
GIR_Done, |
| 2959 |
// Label 295: @5139 |
2959 |
// Label 295: @5139 |
| 2960 |
GIM_Try, /*On fail goto*//*Label 296*/ 5178, // Rule ID 708 // |
2960 |
GIM_Try, /*On fail goto*//*Label 296*/ 5178, // Rule ID 708 // |
| 2961 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2961 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2962 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
2962 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 2963 |
// MIs[0] fs |
2963 |
// MIs[0] fs |
| 2964 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
2964 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2965 |
// MIs[0] fs |
2965 |
// MIs[0] fs |
| 2966 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
2966 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2967 |
// MIs[0] fs |
2967 |
// MIs[0] fs |
| 2968 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
2968 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2969 |
// (build_vector:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs) => (FILL_FW_PSEUDO:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs) |
2969 |
// (build_vector:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs) => (FILL_FW_PSEUDO:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs) |
| 2970 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_FW_PSEUDO, |
2970 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_FW_PSEUDO, |
| 2971 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
2971 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 2972 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs |
2972 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs |
| 2973 |
GIR_EraseFromParent, /*InsnID*/0, |
2973 |
GIR_EraseFromParent, /*InsnID*/0, |
| 2974 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
2974 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 2975 |
// GIR_Coverage, 708, |
2975 |
// GIR_Coverage, 708, |
| 2976 |
GIR_Done, |
2976 |
GIR_Done, |
| 2977 |
// Label 296: @5178 |
2977 |
// Label 296: @5178 |
| 2978 |
GIM_Reject, |
2978 |
GIM_Reject, |
| 2979 |
// Label 294: @5179 |
2979 |
// Label 294: @5179 |
| 2980 |
GIM_Try, /*On fail goto*//*Label 297*/ 5253, // Rule ID 705 // |
2980 |
GIM_Try, /*On fail goto*//*Label 297*/ 5253, // Rule ID 705 // |
| 2981 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
2981 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 2982 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/9, |
2982 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/9, |
| 2983 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
2983 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 2984 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
2984 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 2985 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
2985 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 2986 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
2986 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 2987 |
// MIs[0] rs |
2987 |
// MIs[0] rs |
| 2988 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
2988 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2989 |
// MIs[0] rs |
2989 |
// MIs[0] rs |
| 2990 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
2990 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2991 |
// MIs[0] rs |
2991 |
// MIs[0] rs |
| 2992 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
2992 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2993 |
// MIs[0] rs |
2993 |
// MIs[0] rs |
| 2994 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1, |
2994 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2995 |
// MIs[0] rs |
2995 |
// MIs[0] rs |
| 2996 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1, |
2996 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2997 |
// MIs[0] rs |
2997 |
// MIs[0] rs |
| 2998 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1, |
2998 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 2999 |
// MIs[0] rs |
2999 |
// MIs[0] rs |
| 3000 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1, |
3000 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3001 |
// (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_H:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs) |
3001 |
// (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_H:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs) |
| 3002 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_H, |
3002 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_H, |
| 3003 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
3003 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 3004 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
3004 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 3005 |
GIR_EraseFromParent, /*InsnID*/0, |
3005 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3006 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
3006 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3007 |
// GIR_Coverage, 705, |
3007 |
// GIR_Coverage, 705, |
| 3008 |
GIR_Done, |
3008 |
GIR_Done, |
| 3009 |
// Label 297: @5253 |
3009 |
// Label 297: @5253 |
| 3010 |
GIM_Try, /*On fail goto*//*Label 298*/ 5367, // Rule ID 704 // |
3010 |
GIM_Try, /*On fail goto*//*Label 298*/ 5367, // Rule ID 704 // |
| 3011 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
3011 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 3012 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/17, |
3012 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/17, |
| 3013 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
3013 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 3014 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
3014 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 3015 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
3015 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 3016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
3016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 3017 |
// MIs[0] rs |
3017 |
// MIs[0] rs |
| 3018 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
3018 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3019 |
// MIs[0] rs |
3019 |
// MIs[0] rs |
| 3020 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
3020 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3021 |
// MIs[0] rs |
3021 |
// MIs[0] rs |
| 3022 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
3022 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3023 |
// MIs[0] rs |
3023 |
// MIs[0] rs |
| 3024 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1, |
3024 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3025 |
// MIs[0] rs |
3025 |
// MIs[0] rs |
| 3026 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1, |
3026 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3027 |
// MIs[0] rs |
3027 |
// MIs[0] rs |
| 3028 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1, |
3028 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3029 |
// MIs[0] rs |
3029 |
// MIs[0] rs |
| 3030 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1, |
3030 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3031 |
// MIs[0] rs |
3031 |
// MIs[0] rs |
| 3032 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1, |
3032 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3033 |
// MIs[0] rs |
3033 |
// MIs[0] rs |
| 3034 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1, |
3034 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3035 |
// MIs[0] rs |
3035 |
// MIs[0] rs |
| 3036 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1, |
3036 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3037 |
// MIs[0] rs |
3037 |
// MIs[0] rs |
| 3038 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1, |
3038 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3039 |
// MIs[0] rs |
3039 |
// MIs[0] rs |
| 3040 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1, |
3040 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3041 |
// MIs[0] rs |
3041 |
// MIs[0] rs |
| 3042 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1, |
3042 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3043 |
// MIs[0] rs |
3043 |
// MIs[0] rs |
| 3044 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1, |
3044 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3045 |
// MIs[0] rs |
3045 |
// MIs[0] rs |
| 3046 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1, |
3046 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 3047 |
// (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_B:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs) |
3047 |
// (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) => (FILL_B:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs) |
| 3048 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_B, |
3048 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FILL_B, |
| 3049 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
3049 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 3050 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
3050 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 3051 |
GIR_EraseFromParent, /*InsnID*/0, |
3051 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3052 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
3052 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3053 |
// GIR_Coverage, 704, |
3053 |
// GIR_Coverage, 704, |
| 3054 |
GIR_Done, |
3054 |
GIR_Done, |
| 3055 |
// Label 298: @5367 |
3055 |
// Label 298: @5367 |
| 3056 |
GIM_Reject, |
3056 |
GIM_Reject, |
| 3057 |
// Label 12: @5368 |
3057 |
// Label 12: @5368 |
| 3058 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 307*/ 9020, |
3058 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 307*/ 9020, |
| 3059 |
/*GILLT_s32*//*Label 299*/ 5382, |
3059 |
/*GILLT_s32*//*Label 299*/ 5382, |
| 3060 |
/*GILLT_s64*//*Label 300*/ 5621, |
3060 |
/*GILLT_s64*//*Label 300*/ 5621, |
| 3061 |
/*GILLT_v2s16*//*Label 301*/ 5667, |
3061 |
/*GILLT_v2s16*//*Label 301*/ 5667, |
| 3062 |
/*GILLT_v2s64*//*Label 302*/ 5713, |
3062 |
/*GILLT_v2s64*//*Label 302*/ 5713, |
| 3063 |
/*GILLT_v4s8*//*Label 303*/ 6686, |
3063 |
/*GILLT_v4s8*//*Label 303*/ 6686, |
| 3064 |
/*GILLT_v4s32*//*Label 304*/ 6732, |
3064 |
/*GILLT_v4s32*//*Label 304*/ 6732, |
| 3065 |
/*GILLT_v8s16*//*Label 305*/ 7635, |
3065 |
/*GILLT_v8s16*//*Label 305*/ 7635, |
| 3066 |
/*GILLT_v16s8*//*Label 306*/ 8433, |
3066 |
/*GILLT_v16s8*//*Label 306*/ 8433, |
| 3067 |
// Label 299: @5382 |
3067 |
// Label 299: @5382 |
| 3068 |
GIM_Try, /*On fail goto*//*Label 308*/ 5405, // Rule ID 129 // |
3068 |
GIM_Try, /*On fail goto*//*Label 308*/ 5405, // Rule ID 129 // |
| 3069 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
3069 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 3070 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
3070 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 3071 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
3071 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 3072 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
3072 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 3073 |
// (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) |
3073 |
// (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) |
| 3074 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1, |
3074 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1, |
| 3075 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
3075 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3076 |
// GIR_Coverage, 129, |
3076 |
// GIR_Coverage, 129, |
| 3077 |
GIR_Done, |
3077 |
GIR_Done, |
| 3078 |
// Label 308: @5405 |
3078 |
// Label 308: @5405 |
| 3079 |
GIM_Try, /*On fail goto*//*Label 309*/ 5428, // Rule ID 130 // |
3079 |
GIM_Try, /*On fail goto*//*Label 309*/ 5428, // Rule ID 130 // |
| 3080 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
3080 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 3081 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
3081 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 3082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
3082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 3083 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
3083 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 3084 |
// (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) |
3084 |
// (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) |
| 3085 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1, |
3085 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1, |
| 3086 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
3086 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3087 |
// GIR_Coverage, 130, |
3087 |
// GIR_Coverage, 130, |
| 3088 |
GIR_Done, |
3088 |
GIR_Done, |
| 3089 |
// Label 309: @5428 |
3089 |
// Label 309: @5428 |
| 3090 |
GIM_Try, /*On fail goto*//*Label 310*/ 5451, // Rule ID 1148 // |
3090 |
GIM_Try, /*On fail goto*//*Label 310*/ 5451, // Rule ID 1148 // |
| 3091 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
3091 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
| 3092 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
3092 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 3093 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
3093 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 3094 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
3094 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 3095 |
// (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) |
3095 |
// (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) |
| 3096 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MM, |
3096 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MM, |
| 3097 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
3097 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3098 |
// GIR_Coverage, 1148, |
3098 |
// GIR_Coverage, 1148, |
| 3099 |
GIR_Done, |
3099 |
GIR_Done, |
| 3100 |
// Label 310: @5451 |
3100 |
// Label 310: @5451 |
| 3101 |
GIM_Try, /*On fail goto*//*Label 311*/ 5474, // Rule ID 1149 // |
3101 |
GIM_Try, /*On fail goto*//*Label 311*/ 5474, // Rule ID 1149 // |
| 3102 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
3102 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
| 3103 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
3103 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 3104 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
3104 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 3105 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
3105 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 3106 |
// (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) |
3106 |
// (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) |
| 3107 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MM, |
3107 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MM, |
| 3108 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
3108 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3109 |
// GIR_Coverage, 1149, |
3109 |
// GIR_Coverage, 1149, |
| 3110 |
GIR_Done, |
3110 |
GIR_Done, |
| 3111 |
// Label 311: @5474 |
3111 |
// Label 311: @5474 |
| 3112 |
GIM_Try, /*On fail goto*//*Label 312*/ 5497, // Rule ID 1163 // |
3112 |
GIM_Try, /*On fail goto*//*Label 312*/ 5497, // Rule ID 1163 // |
| 3113 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
3113 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 3114 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
3114 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 3115 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
3115 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 3116 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
3116 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 3117 |
// (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) |
3117 |
// (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) |
| 3118 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MMR6, |
3118 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MMR6, |
| 3119 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
3119 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3120 |
// GIR_Coverage, 1163, |
3120 |
// GIR_Coverage, 1163, |
| 3121 |
GIR_Done, |
3121 |
GIR_Done, |
| 3122 |
// Label 312: @5497 |
3122 |
// Label 312: @5497 |
| 3123 |
GIM_Try, /*On fail goto*//*Label 313*/ 5520, // Rule ID 1164 // |
3123 |
GIM_Try, /*On fail goto*//*Label 313*/ 5520, // Rule ID 1164 // |
| 3124 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
3124 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 3125 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
3125 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 3126 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
3126 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 3127 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
3127 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 3128 |
// (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) |
3128 |
// (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) |
| 3129 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MMR6, |
3129 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MMR6, |
| 3130 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
3130 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3131 |
// GIR_Coverage, 1164, |
3131 |
// GIR_Coverage, 1164, |
| 3132 |
GIR_Done, |
3132 |
GIR_Done, |
| 3133 |
// Label 313: @5520 |
3133 |
// Label 313: @5520 |
| 3134 |
GIM_Try, /*On fail goto*//*Label 314*/ 5545, // Rule ID 1869 // |
3134 |
GIM_Try, /*On fail goto*//*Label 314*/ 5545, // Rule ID 1869 // |
| 3135 |
GIM_CheckFeatures, GIFBS_HasDSP, |
3135 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 3136 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
3136 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
| 3137 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
3137 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 3138 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
3138 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 3139 |
// (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] }) |
3139 |
// (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] }) |
| 3140 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3140 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3141 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR32RegClassID, |
3141 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR32RegClassID, |
| 3142 |
// GIR_Coverage, 1869, |
3142 |
// GIR_Coverage, 1869, |
| 3143 |
GIR_Done, |
3143 |
GIR_Done, |
| 3144 |
// Label 314: @5545 |
3144 |
// Label 314: @5545 |
| 3145 |
GIM_Try, /*On fail goto*//*Label 315*/ 5570, // Rule ID 1870 // |
3145 |
GIM_Try, /*On fail goto*//*Label 315*/ 5570, // Rule ID 1870 // |
| 3146 |
GIM_CheckFeatures, GIFBS_HasDSP, |
3146 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 3147 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
3147 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
| 3148 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
3148 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 3149 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
3149 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 3150 |
// (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] }) |
3150 |
// (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] }) |
| 3151 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3151 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3152 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR32RegClassID, |
3152 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR32RegClassID, |
| 3153 |
// GIR_Coverage, 1870, |
3153 |
// GIR_Coverage, 1870, |
| 3154 |
GIR_Done, |
3154 |
GIR_Done, |
| 3155 |
// Label 315: @5570 |
3155 |
// Label 315: @5570 |
| 3156 |
GIM_Try, /*On fail goto*//*Label 316*/ 5595, // Rule ID 1873 // |
3156 |
GIM_Try, /*On fail goto*//*Label 316*/ 5595, // Rule ID 1873 // |
| 3157 |
GIM_CheckFeatures, GIFBS_HasDSP, |
3157 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 3158 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
3158 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
| 3159 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
3159 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 3160 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
3160 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 3161 |
// (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] }) |
3161 |
// (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] }) |
| 3162 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3162 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3163 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::FGR32RegClassID, |
3163 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::FGR32RegClassID, |
| 3164 |
// GIR_Coverage, 1873, |
3164 |
// GIR_Coverage, 1873, |
| 3165 |
GIR_Done, |
3165 |
GIR_Done, |
| 3166 |
// Label 316: @5595 |
3166 |
// Label 316: @5595 |
| 3167 |
GIM_Try, /*On fail goto*//*Label 317*/ 5620, // Rule ID 1874 // |
3167 |
GIM_Try, /*On fail goto*//*Label 317*/ 5620, // Rule ID 1874 // |
| 3168 |
GIM_CheckFeatures, GIFBS_HasDSP, |
3168 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 3169 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
3169 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
| 3170 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
3170 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 3171 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
3171 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 3172 |
// (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] }) |
3172 |
// (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] }) |
| 3173 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3173 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3174 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::FGR32RegClassID, |
3174 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::FGR32RegClassID, |
| 3175 |
// GIR_Coverage, 1874, |
3175 |
// GIR_Coverage, 1874, |
| 3176 |
GIR_Done, |
3176 |
GIR_Done, |
| 3177 |
// Label 317: @5620 |
3177 |
// Label 317: @5620 |
| 3178 |
GIM_Reject, |
3178 |
GIM_Reject, |
| 3179 |
// Label 300: @5621 |
3179 |
// Label 300: @5621 |
| 3180 |
GIM_Try, /*On fail goto*//*Label 318*/ 5666, |
3180 |
GIM_Try, /*On fail goto*//*Label 318*/ 5666, |
| 3181 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
3181 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 3182 |
GIM_Try, /*On fail goto*//*Label 319*/ 5646, // Rule ID 131 // |
3182 |
GIM_Try, /*On fail goto*//*Label 319*/ 5646, // Rule ID 131 // |
| 3183 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
3183 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 3184 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
3184 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 3185 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
3185 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 3186 |
// (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) => (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) |
3186 |
// (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) => (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) |
| 3187 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMTC1, |
3187 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMTC1, |
| 3188 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
3188 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3189 |
// GIR_Coverage, 131, |
3189 |
// GIR_Coverage, 131, |
| 3190 |
GIR_Done, |
3190 |
GIR_Done, |
| 3191 |
// Label 319: @5646 |
3191 |
// Label 319: @5646 |
| 3192 |
GIM_Try, /*On fail goto*//*Label 320*/ 5665, // Rule ID 132 // |
3192 |
GIM_Try, /*On fail goto*//*Label 320*/ 5665, // Rule ID 132 // |
| 3193 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
3193 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 3194 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
3194 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 3195 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
3195 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 3196 |
// (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) => (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) |
3196 |
// (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) => (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) |
| 3197 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMFC1, |
3197 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMFC1, |
| 3198 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
3198 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 3199 |
// GIR_Coverage, 132, |
3199 |
// GIR_Coverage, 132, |
| 3200 |
GIR_Done, |
3200 |
GIR_Done, |
| 3201 |
// Label 320: @5665 |
3201 |
// Label 320: @5665 |
| 3202 |
GIM_Reject, |
3202 |
GIM_Reject, |
| 3203 |
// Label 318: @5666 |
3203 |
// Label 318: @5666 |
| 3204 |
GIM_Reject, |
3204 |
GIM_Reject, |
| 3205 |
// Label 301: @5667 |
3205 |
// Label 301: @5667 |
| 3206 |
GIM_Try, /*On fail goto*//*Label 321*/ 5712, |
3206 |
GIM_Try, /*On fail goto*//*Label 321*/ 5712, |
| 3207 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
3207 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 3208 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
3208 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 3209 |
GIM_Try, /*On fail goto*//*Label 322*/ 5694, // Rule ID 1871 // |
3209 |
GIM_Try, /*On fail goto*//*Label 322*/ 5694, // Rule ID 1871 // |
| 3210 |
GIM_CheckFeatures, GIFBS_HasDSP, |
3210 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 3211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
3211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 3212 |
// (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] }) |
3212 |
// (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] }) |
| 3213 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3213 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3214 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::DSPRRegClassID, |
3214 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::DSPRRegClassID, |
| 3215 |
// GIR_Coverage, 1871, |
3215 |
// GIR_Coverage, 1871, |
| 3216 |
GIR_Done, |
3216 |
GIR_Done, |
| 3217 |
// Label 322: @5694 |
3217 |
// Label 322: @5694 |
| 3218 |
GIM_Try, /*On fail goto*//*Label 323*/ 5711, // Rule ID 1875 // |
3218 |
GIM_Try, /*On fail goto*//*Label 323*/ 5711, // Rule ID 1875 // |
| 3219 |
GIM_CheckFeatures, GIFBS_HasDSP, |
3219 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 3220 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
3220 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 3221 |
// (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] }) |
3221 |
// (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] }) |
| 3222 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3222 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3223 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::DSPRRegClassID, |
3223 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::DSPRRegClassID, |
| 3224 |
// GIR_Coverage, 1875, |
3224 |
// GIR_Coverage, 1875, |
| 3225 |
GIR_Done, |
3225 |
GIR_Done, |
| 3226 |
// Label 323: @5711 |
3226 |
// Label 323: @5711 |
| 3227 |
GIM_Reject, |
3227 |
GIM_Reject, |
| 3228 |
// Label 321: @5712 |
3228 |
// Label 321: @5712 |
| 3229 |
GIM_Reject, |
3229 |
GIM_Reject, |
| 3230 |
// Label 302: @5713 |
3230 |
// Label 302: @5713 |
| 3231 |
GIM_Try, /*On fail goto*//*Label 324*/ 5734, // Rule ID 1956 // |
3231 |
GIM_Try, /*On fail goto*//*Label 324*/ 5734, // Rule ID 1956 // |
| 3232 |
GIM_CheckFeatures, GIFBS_HasMSA, |
3232 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 3233 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
3233 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3235 |
// (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] }) |
3235 |
// (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] }) |
| 3236 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3236 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3237 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3237 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3238 |
// GIR_Coverage, 1956, |
3238 |
// GIR_Coverage, 1956, |
| 3239 |
GIR_Done, |
3239 |
GIR_Done, |
| 3240 |
// Label 324: @5734 |
3240 |
// Label 324: @5734 |
| 3241 |
GIM_Try, /*On fail goto*//*Label 325*/ 5755, // Rule ID 1959 // |
3241 |
GIM_Try, /*On fail goto*//*Label 325*/ 5755, // Rule ID 1959 // |
| 3242 |
GIM_CheckFeatures, GIFBS_HasMSA, |
3242 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 3243 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
3243 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3244 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3244 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3245 |
// (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] }) |
3245 |
// (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] }) |
| 3246 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3246 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3247 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3247 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3248 |
// GIR_Coverage, 1959, |
3248 |
// GIR_Coverage, 1959, |
| 3249 |
GIR_Done, |
3249 |
GIR_Done, |
| 3250 |
// Label 325: @5755 |
3250 |
// Label 325: @5755 |
| 3251 |
GIM_Try, /*On fail goto*//*Label 326*/ 5776, // Rule ID 1976 // |
3251 |
GIM_Try, /*On fail goto*//*Label 326*/ 5776, // Rule ID 1976 // |
| 3252 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3252 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3253 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
3253 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3254 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3254 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3255 |
// (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] }) |
3255 |
// (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] }) |
| 3256 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3256 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3257 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3257 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3258 |
// GIR_Coverage, 1976, |
3258 |
// GIR_Coverage, 1976, |
| 3259 |
GIR_Done, |
3259 |
GIR_Done, |
| 3260 |
// Label 326: @5776 |
3260 |
// Label 326: @5776 |
| 3261 |
GIM_Try, /*On fail goto*//*Label 327*/ 5797, // Rule ID 1977 // |
3261 |
GIM_Try, /*On fail goto*//*Label 327*/ 5797, // Rule ID 1977 // |
| 3262 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3262 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3263 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3263 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3264 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3264 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3265 |
// (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] }) |
3265 |
// (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] }) |
| 3266 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3266 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3267 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3267 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3268 |
// GIR_Coverage, 1977, |
3268 |
// GIR_Coverage, 1977, |
| 3269 |
GIR_Done, |
3269 |
GIR_Done, |
| 3270 |
// Label 327: @5797 |
3270 |
// Label 327: @5797 |
| 3271 |
GIM_Try, /*On fail goto*//*Label 328*/ 5818, // Rule ID 1978 // |
3271 |
GIM_Try, /*On fail goto*//*Label 328*/ 5818, // Rule ID 1978 // |
| 3272 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3272 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3273 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
3273 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3274 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3274 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3275 |
// (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] }) |
3275 |
// (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] }) |
| 3276 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3276 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3277 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3277 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3278 |
// GIR_Coverage, 1978, |
3278 |
// GIR_Coverage, 1978, |
| 3279 |
GIR_Done, |
3279 |
GIR_Done, |
| 3280 |
// Label 328: @5818 |
3280 |
// Label 328: @5818 |
| 3281 |
GIM_Try, /*On fail goto*//*Label 329*/ 5839, // Rule ID 1979 // |
3281 |
GIM_Try, /*On fail goto*//*Label 329*/ 5839, // Rule ID 1979 // |
| 3282 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3282 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3283 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3283 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3284 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3284 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3285 |
// (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] }) |
3285 |
// (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] }) |
| 3286 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3286 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3287 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3287 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3288 |
// GIR_Coverage, 1979, |
3288 |
// GIR_Coverage, 1979, |
| 3289 |
GIR_Done, |
3289 |
GIR_Done, |
| 3290 |
// Label 329: @5839 |
3290 |
// Label 329: @5839 |
| 3291 |
GIM_Try, /*On fail goto*//*Label 330*/ 5860, // Rule ID 1980 // |
3291 |
GIM_Try, /*On fail goto*//*Label 330*/ 5860, // Rule ID 1980 // |
| 3292 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3292 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3293 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
3293 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3294 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3294 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3295 |
// (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] }) |
3295 |
// (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] }) |
| 3296 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3296 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3297 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3297 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3298 |
// GIR_Coverage, 1980, |
3298 |
// GIR_Coverage, 1980, |
| 3299 |
GIR_Done, |
3299 |
GIR_Done, |
| 3300 |
// Label 330: @5860 |
3300 |
// Label 330: @5860 |
| 3301 |
GIM_Try, /*On fail goto*//*Label 331*/ 5881, // Rule ID 1986 // |
3301 |
GIM_Try, /*On fail goto*//*Label 331*/ 5881, // Rule ID 1986 // |
| 3302 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3302 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3303 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
3303 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3304 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3304 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3305 |
// (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] }) |
3305 |
// (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] }) |
| 3306 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3306 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3307 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3307 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3308 |
// GIR_Coverage, 1986, |
3308 |
// GIR_Coverage, 1986, |
| 3309 |
GIR_Done, |
3309 |
GIR_Done, |
| 3310 |
// Label 331: @5881 |
3310 |
// Label 331: @5881 |
| 3311 |
GIM_Try, /*On fail goto*//*Label 332*/ 5902, // Rule ID 1987 // |
3311 |
GIM_Try, /*On fail goto*//*Label 332*/ 5902, // Rule ID 1987 // |
| 3312 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3312 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3313 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3313 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3314 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3314 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3315 |
// (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] }) |
3315 |
// (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] }) |
| 3316 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3316 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3317 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3317 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3318 |
// GIR_Coverage, 1987, |
3318 |
// GIR_Coverage, 1987, |
| 3319 |
GIR_Done, |
3319 |
GIR_Done, |
| 3320 |
// Label 332: @5902 |
3320 |
// Label 332: @5902 |
| 3321 |
GIM_Try, /*On fail goto*//*Label 333*/ 5923, // Rule ID 1988 // |
3321 |
GIM_Try, /*On fail goto*//*Label 333*/ 5923, // Rule ID 1988 // |
| 3322 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3322 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3323 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
3323 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3325 |
// (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] }) |
3325 |
// (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] }) |
| 3326 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3326 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3327 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3327 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3328 |
// GIR_Coverage, 1988, |
3328 |
// GIR_Coverage, 1988, |
| 3329 |
GIR_Done, |
3329 |
GIR_Done, |
| 3330 |
// Label 333: @5923 |
3330 |
// Label 333: @5923 |
| 3331 |
GIM_Try, /*On fail goto*//*Label 334*/ 5944, // Rule ID 1989 // |
3331 |
GIM_Try, /*On fail goto*//*Label 334*/ 5944, // Rule ID 1989 // |
| 3332 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3332 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3333 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3333 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3334 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3334 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3335 |
// (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] }) |
3335 |
// (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] }) |
| 3336 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3336 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3337 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3337 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3338 |
// GIR_Coverage, 1989, |
3338 |
// GIR_Coverage, 1989, |
| 3339 |
GIR_Done, |
3339 |
GIR_Done, |
| 3340 |
// Label 334: @5944 |
3340 |
// Label 334: @5944 |
| 3341 |
GIM_Try, /*On fail goto*//*Label 335*/ 5965, // Rule ID 1990 // |
3341 |
GIM_Try, /*On fail goto*//*Label 335*/ 5965, // Rule ID 1990 // |
| 3342 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3342 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3343 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
3343 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3344 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3344 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3345 |
// (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] }) |
3345 |
// (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] }) |
| 3346 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3346 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3347 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3347 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3348 |
// GIR_Coverage, 1990, |
3348 |
// GIR_Coverage, 1990, |
| 3349 |
GIR_Done, |
3349 |
GIR_Done, |
| 3350 |
// Label 335: @5965 |
3350 |
// Label 335: @5965 |
| 3351 |
GIM_Try, /*On fail goto*//*Label 336*/ 6065, // Rule ID 1995 // |
3351 |
GIM_Try, /*On fail goto*//*Label 336*/ 6065, // Rule ID 1995 // |
| 3352 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3352 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3353 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
3353 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3354 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3354 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3355 |
// (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) |
3355 |
// (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) |
| 3356 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
3356 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3357 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
3357 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 3358 |
GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, |
3358 |
GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, |
| 3359 |
GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, |
3359 |
GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, |
| 3360 |
GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY, |
3360 |
GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY, |
| 3361 |
GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
3361 |
GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 3362 |
GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src |
3362 |
GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3363 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
3363 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 3364 |
GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B, |
3364 |
GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B, |
| 3365 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
3365 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 3366 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
3366 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 3367 |
GIR_AddImm, /*InsnID*/3, /*Imm*/27, |
3367 |
GIR_AddImm, /*InsnID*/3, /*Imm*/27, |
| 3368 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
3368 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 3369 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3369 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3370 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3370 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3371 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
3371 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 3372 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3372 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3373 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
3373 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
| 3374 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3374 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3375 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3375 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3376 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3376 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3377 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3377 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3378 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3378 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3379 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3379 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3380 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3380 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3381 |
GIR_EraseFromParent, /*InsnID*/0, |
3381 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3382 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3382 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3383 |
// GIR_Coverage, 1995, |
3383 |
// GIR_Coverage, 1995, |
| 3384 |
GIR_Done, |
3384 |
GIR_Done, |
| 3385 |
// Label 336: @6065 |
3385 |
// Label 336: @6065 |
| 3386 |
GIM_Try, /*On fail goto*//*Label 337*/ 6165, // Rule ID 1996 // |
3386 |
GIM_Try, /*On fail goto*//*Label 337*/ 6165, // Rule ID 1996 // |
| 3387 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3387 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3388 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
3388 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3389 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3389 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3390 |
// (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) |
3390 |
// (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) |
| 3391 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
3391 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3392 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
3392 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 3393 |
GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, |
3393 |
GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, |
| 3394 |
GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, |
3394 |
GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, |
| 3395 |
GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY, |
3395 |
GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY, |
| 3396 |
GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
3396 |
GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 3397 |
GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src |
3397 |
GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3398 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
3398 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 3399 |
GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B, |
3399 |
GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B, |
| 3400 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
3400 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 3401 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
3401 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 3402 |
GIR_AddImm, /*InsnID*/3, /*Imm*/27, |
3402 |
GIR_AddImm, /*InsnID*/3, /*Imm*/27, |
| 3403 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
3403 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 3404 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3404 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3405 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3405 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3406 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
3406 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 3407 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3407 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3408 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
3408 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
| 3409 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3409 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3410 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3410 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3411 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3411 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3412 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3412 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3413 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3413 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3414 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3414 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3415 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3415 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3416 |
GIR_EraseFromParent, /*InsnID*/0, |
3416 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3417 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3417 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3418 |
// GIR_Coverage, 1996, |
3418 |
// GIR_Coverage, 1996, |
| 3419 |
GIR_Done, |
3419 |
GIR_Done, |
| 3420 |
// Label 337: @6165 |
3420 |
// Label 337: @6165 |
| 3421 |
GIM_Try, /*On fail goto*//*Label 338*/ 6230, // Rule ID 2000 // |
3421 |
GIM_Try, /*On fail goto*//*Label 338*/ 6230, // Rule ID 2000 // |
| 3422 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3422 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3423 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3423 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3424 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3424 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3425 |
// (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] }) |
3425 |
// (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] }) |
| 3426 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
3426 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 3427 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
3427 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 3428 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3428 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3429 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3429 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3430 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3430 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3431 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3431 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3432 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
3432 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 3433 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3433 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3434 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3434 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3435 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
3435 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
| 3436 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3436 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3437 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3437 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3438 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3438 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3439 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3439 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3440 |
GIR_EraseFromParent, /*InsnID*/0, |
3440 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3441 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3441 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3442 |
// GIR_Coverage, 2000, |
3442 |
// GIR_Coverage, 2000, |
| 3443 |
GIR_Done, |
3443 |
GIR_Done, |
| 3444 |
// Label 338: @6230 |
3444 |
// Label 338: @6230 |
| 3445 |
GIM_Try, /*On fail goto*//*Label 339*/ 6295, // Rule ID 2001 // |
3445 |
GIM_Try, /*On fail goto*//*Label 339*/ 6295, // Rule ID 2001 // |
| 3446 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3446 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3447 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3447 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3448 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3448 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3449 |
// (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] }) |
3449 |
// (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] }) |
| 3450 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
3450 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 3451 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
3451 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 3452 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3452 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3453 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3453 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3454 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3454 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3455 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3455 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3456 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
3456 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 3457 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3457 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3458 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3458 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3459 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
3459 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
| 3460 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3460 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3461 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3461 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3462 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3462 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3463 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3463 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3464 |
GIR_EraseFromParent, /*InsnID*/0, |
3464 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3465 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3465 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3466 |
// GIR_Coverage, 2001, |
3466 |
// GIR_Coverage, 2001, |
| 3467 |
GIR_Done, |
3467 |
GIR_Done, |
| 3468 |
// Label 339: @6295 |
3468 |
// Label 339: @6295 |
| 3469 |
GIM_Try, /*On fail goto*//*Label 340*/ 6360, // Rule ID 2005 // |
3469 |
GIM_Try, /*On fail goto*//*Label 340*/ 6360, // Rule ID 2005 // |
| 3470 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3470 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3471 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3471 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3472 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3472 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3473 |
// (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] }) |
3473 |
// (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] }) |
| 3474 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
3474 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 3475 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
3475 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 3476 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3476 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3477 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3477 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3478 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3478 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3479 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3479 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3480 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
3480 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 3481 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3481 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3482 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3482 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3483 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
3483 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
| 3484 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3484 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3485 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3485 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3486 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3486 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3487 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3487 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3488 |
GIR_EraseFromParent, /*InsnID*/0, |
3488 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3489 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3489 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3490 |
// GIR_Coverage, 2005, |
3490 |
// GIR_Coverage, 2005, |
| 3491 |
GIR_Done, |
3491 |
GIR_Done, |
| 3492 |
// Label 340: @6360 |
3492 |
// Label 340: @6360 |
| 3493 |
GIM_Try, /*On fail goto*//*Label 341*/ 6425, // Rule ID 2006 // |
3493 |
GIM_Try, /*On fail goto*//*Label 341*/ 6425, // Rule ID 2006 // |
| 3494 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3494 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3495 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3495 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3496 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3496 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3497 |
// (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] }) |
3497 |
// (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] }) |
| 3498 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
3498 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 3499 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
3499 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 3500 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3500 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3501 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3501 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3502 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3502 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3503 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3503 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3504 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
3504 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 3505 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3505 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3506 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3506 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3507 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
3507 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
| 3508 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3508 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3509 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3509 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3510 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3510 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3511 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3511 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3512 |
GIR_EraseFromParent, /*InsnID*/0, |
3512 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3513 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3513 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3514 |
// GIR_Coverage, 2006, |
3514 |
// GIR_Coverage, 2006, |
| 3515 |
GIR_Done, |
3515 |
GIR_Done, |
| 3516 |
// Label 341: @6425 |
3516 |
// Label 341: @6425 |
| 3517 |
GIM_Try, /*On fail goto*//*Label 342*/ 6490, // Rule ID 2010 // |
3517 |
GIM_Try, /*On fail goto*//*Label 342*/ 6490, // Rule ID 2010 // |
| 3518 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3518 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3519 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
3519 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3520 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3520 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3521 |
// (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) |
3521 |
// (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) |
| 3522 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
3522 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3523 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
3523 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 3524 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3524 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3525 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3525 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3526 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3526 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3527 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3527 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3528 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
3528 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
| 3529 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3529 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3530 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3530 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3531 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3531 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3532 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3532 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3533 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3533 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3534 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3534 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3535 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3535 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3536 |
GIR_EraseFromParent, /*InsnID*/0, |
3536 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3537 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3537 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3538 |
// GIR_Coverage, 2010, |
3538 |
// GIR_Coverage, 2010, |
| 3539 |
GIR_Done, |
3539 |
GIR_Done, |
| 3540 |
// Label 342: @6490 |
3540 |
// Label 342: @6490 |
| 3541 |
GIM_Try, /*On fail goto*//*Label 343*/ 6555, // Rule ID 2011 // |
3541 |
GIM_Try, /*On fail goto*//*Label 343*/ 6555, // Rule ID 2011 // |
| 3542 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3542 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3543 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
3543 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3544 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3544 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3545 |
// (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) |
3545 |
// (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) |
| 3546 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
3546 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3547 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
3547 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 3548 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3548 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3549 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3549 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3550 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3550 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3551 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3551 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3552 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
3552 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
| 3553 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3553 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3554 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3554 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3555 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3555 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3556 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3556 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3557 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3557 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3558 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3558 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3559 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3559 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3560 |
GIR_EraseFromParent, /*InsnID*/0, |
3560 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3561 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3561 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3562 |
// GIR_Coverage, 2011, |
3562 |
// GIR_Coverage, 2011, |
| 3563 |
GIR_Done, |
3563 |
GIR_Done, |
| 3564 |
// Label 343: @6555 |
3564 |
// Label 343: @6555 |
| 3565 |
GIM_Try, /*On fail goto*//*Label 344*/ 6620, // Rule ID 2015 // |
3565 |
GIM_Try, /*On fail goto*//*Label 344*/ 6620, // Rule ID 2015 // |
| 3566 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3566 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3567 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
3567 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3568 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3568 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3569 |
// (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) |
3569 |
// (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) |
| 3570 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
3570 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3571 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
3571 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 3572 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3572 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3573 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3573 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3574 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3574 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3575 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3575 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3576 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
3576 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
| 3577 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3577 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3578 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3578 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3579 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3579 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3580 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3580 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3581 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3581 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3582 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3582 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3583 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3583 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3584 |
GIR_EraseFromParent, /*InsnID*/0, |
3584 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3585 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3585 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3586 |
// GIR_Coverage, 2015, |
3586 |
// GIR_Coverage, 2015, |
| 3587 |
GIR_Done, |
3587 |
GIR_Done, |
| 3588 |
// Label 344: @6620 |
3588 |
// Label 344: @6620 |
| 3589 |
GIM_Try, /*On fail goto*//*Label 345*/ 6685, // Rule ID 2016 // |
3589 |
GIM_Try, /*On fail goto*//*Label 345*/ 6685, // Rule ID 2016 // |
| 3590 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3590 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3591 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
3591 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3592 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
3592 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 3593 |
// (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) |
3593 |
// (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] }) |
| 3594 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
3594 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3595 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
3595 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 3596 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3596 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3597 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3597 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3598 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3598 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3599 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3599 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3600 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
3600 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
| 3601 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3601 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3602 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3602 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3603 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3603 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3604 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3604 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3605 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3605 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3606 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3606 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3607 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3607 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3608 |
GIR_EraseFromParent, /*InsnID*/0, |
3608 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3609 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
3609 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128DRegClassID, |
| 3610 |
// GIR_Coverage, 2016, |
3610 |
// GIR_Coverage, 2016, |
| 3611 |
GIR_Done, |
3611 |
GIR_Done, |
| 3612 |
// Label 345: @6685 |
3612 |
// Label 345: @6685 |
| 3613 |
GIM_Reject, |
3613 |
GIM_Reject, |
| 3614 |
// Label 303: @6686 |
3614 |
// Label 303: @6686 |
| 3615 |
GIM_Try, /*On fail goto*//*Label 346*/ 6731, |
3615 |
GIM_Try, /*On fail goto*//*Label 346*/ 6731, |
| 3616 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
3616 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 3617 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
3617 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 3618 |
GIM_Try, /*On fail goto*//*Label 347*/ 6713, // Rule ID 1872 // |
3618 |
GIM_Try, /*On fail goto*//*Label 347*/ 6713, // Rule ID 1872 // |
| 3619 |
GIM_CheckFeatures, GIFBS_HasDSP, |
3619 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 3620 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
3620 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 3621 |
// (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] }) |
3621 |
// (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] }) |
| 3622 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3622 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3623 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::DSPRRegClassID, |
3623 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::DSPRRegClassID, |
| 3624 |
// GIR_Coverage, 1872, |
3624 |
// GIR_Coverage, 1872, |
| 3625 |
GIR_Done, |
3625 |
GIR_Done, |
| 3626 |
// Label 347: @6713 |
3626 |
// Label 347: @6713 |
| 3627 |
GIM_Try, /*On fail goto*//*Label 348*/ 6730, // Rule ID 1876 // |
3627 |
GIM_Try, /*On fail goto*//*Label 348*/ 6730, // Rule ID 1876 // |
| 3628 |
GIM_CheckFeatures, GIFBS_HasDSP, |
3628 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 3629 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
3629 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 3630 |
// (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] }) |
3630 |
// (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] }) |
| 3631 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3631 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3632 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::DSPRRegClassID, |
3632 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::DSPRRegClassID, |
| 3633 |
// GIR_Coverage, 1876, |
3633 |
// GIR_Coverage, 1876, |
| 3634 |
GIR_Done, |
3634 |
GIR_Done, |
| 3635 |
// Label 348: @6730 |
3635 |
// Label 348: @6730 |
| 3636 |
GIM_Reject, |
3636 |
GIM_Reject, |
| 3637 |
// Label 346: @6731 |
3637 |
// Label 346: @6731 |
| 3638 |
GIM_Reject, |
3638 |
GIM_Reject, |
| 3639 |
// Label 304: @6732 |
3639 |
// Label 304: @6732 |
| 3640 |
GIM_Try, /*On fail goto*//*Label 349*/ 6753, // Rule ID 1955 // |
3640 |
GIM_Try, /*On fail goto*//*Label 349*/ 6753, // Rule ID 1955 // |
| 3641 |
GIM_CheckFeatures, GIFBS_HasMSA, |
3641 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 3642 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
3642 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3643 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3643 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3644 |
// (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }) |
3644 |
// (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }) |
| 3645 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3645 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3646 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3646 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3647 |
// GIR_Coverage, 1955, |
3647 |
// GIR_Coverage, 1955, |
| 3648 |
GIR_Done, |
3648 |
GIR_Done, |
| 3649 |
// Label 349: @6753 |
3649 |
// Label 349: @6753 |
| 3650 |
GIM_Try, /*On fail goto*//*Label 350*/ 6774, // Rule ID 1958 // |
3650 |
GIM_Try, /*On fail goto*//*Label 350*/ 6774, // Rule ID 1958 // |
| 3651 |
GIM_CheckFeatures, GIFBS_HasMSA, |
3651 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 3652 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
3652 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3653 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3653 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3654 |
// (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }) |
3654 |
// (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }) |
| 3655 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3655 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3656 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3656 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3657 |
// GIR_Coverage, 1958, |
3657 |
// GIR_Coverage, 1958, |
| 3658 |
GIR_Done, |
3658 |
GIR_Done, |
| 3659 |
// Label 350: @6774 |
3659 |
// Label 350: @6774 |
| 3660 |
GIM_Try, /*On fail goto*//*Label 351*/ 6795, // Rule ID 1971 // |
3660 |
GIM_Try, /*On fail goto*//*Label 351*/ 6795, // Rule ID 1971 // |
| 3661 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3661 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3662 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
3662 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3663 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3663 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3664 |
// (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] }) |
3664 |
// (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] }) |
| 3665 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3665 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3666 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3666 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3667 |
// GIR_Coverage, 1971, |
3667 |
// GIR_Coverage, 1971, |
| 3668 |
GIR_Done, |
3668 |
GIR_Done, |
| 3669 |
// Label 351: @6795 |
3669 |
// Label 351: @6795 |
| 3670 |
GIM_Try, /*On fail goto*//*Label 352*/ 6816, // Rule ID 1972 // |
3670 |
GIM_Try, /*On fail goto*//*Label 352*/ 6816, // Rule ID 1972 // |
| 3671 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3671 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3672 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3672 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3673 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3673 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3674 |
// (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] }) |
3674 |
// (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] }) |
| 3675 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3675 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3676 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3676 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3677 |
// GIR_Coverage, 1972, |
3677 |
// GIR_Coverage, 1972, |
| 3678 |
GIR_Done, |
3678 |
GIR_Done, |
| 3679 |
// Label 352: @6816 |
3679 |
// Label 352: @6816 |
| 3680 |
GIM_Try, /*On fail goto*//*Label 353*/ 6837, // Rule ID 1973 // |
3680 |
GIM_Try, /*On fail goto*//*Label 353*/ 6837, // Rule ID 1973 // |
| 3681 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3681 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3682 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
3682 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3683 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3683 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3684 |
// (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }) |
3684 |
// (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }) |
| 3685 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3685 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3686 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3686 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3687 |
// GIR_Coverage, 1973, |
3687 |
// GIR_Coverage, 1973, |
| 3688 |
GIR_Done, |
3688 |
GIR_Done, |
| 3689 |
// Label 353: @6837 |
3689 |
// Label 353: @6837 |
| 3690 |
GIM_Try, /*On fail goto*//*Label 354*/ 6858, // Rule ID 1974 // |
3690 |
GIM_Try, /*On fail goto*//*Label 354*/ 6858, // Rule ID 1974 // |
| 3691 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3691 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3692 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3692 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3693 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3693 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3694 |
// (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] }) |
3694 |
// (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] }) |
| 3695 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3695 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3696 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3696 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3697 |
// GIR_Coverage, 1974, |
3697 |
// GIR_Coverage, 1974, |
| 3698 |
GIR_Done, |
3698 |
GIR_Done, |
| 3699 |
// Label 354: @6858 |
3699 |
// Label 354: @6858 |
| 3700 |
GIM_Try, /*On fail goto*//*Label 355*/ 6879, // Rule ID 1975 // |
3700 |
GIM_Try, /*On fail goto*//*Label 355*/ 6879, // Rule ID 1975 // |
| 3701 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3701 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3702 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
3702 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3703 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3703 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3704 |
// (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }) |
3704 |
// (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }) |
| 3705 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3705 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3706 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3706 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3707 |
// GIR_Coverage, 1975, |
3707 |
// GIR_Coverage, 1975, |
| 3708 |
GIR_Done, |
3708 |
GIR_Done, |
| 3709 |
// Label 355: @6879 |
3709 |
// Label 355: @6879 |
| 3710 |
GIM_Try, /*On fail goto*//*Label 356*/ 6900, // Rule ID 1981 // |
3710 |
GIM_Try, /*On fail goto*//*Label 356*/ 6900, // Rule ID 1981 // |
| 3711 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3711 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3712 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
3712 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3713 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3713 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3714 |
// (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] }) |
3714 |
// (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] }) |
| 3715 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3715 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3716 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3716 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3717 |
// GIR_Coverage, 1981, |
3717 |
// GIR_Coverage, 1981, |
| 3718 |
GIR_Done, |
3718 |
GIR_Done, |
| 3719 |
// Label 356: @6900 |
3719 |
// Label 356: @6900 |
| 3720 |
GIM_Try, /*On fail goto*//*Label 357*/ 6921, // Rule ID 1982 // |
3720 |
GIM_Try, /*On fail goto*//*Label 357*/ 6921, // Rule ID 1982 // |
| 3721 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3721 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3722 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3722 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3723 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3723 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3724 |
// (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] }) |
3724 |
// (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] }) |
| 3725 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3725 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3726 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3726 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3727 |
// GIR_Coverage, 1982, |
3727 |
// GIR_Coverage, 1982, |
| 3728 |
GIR_Done, |
3728 |
GIR_Done, |
| 3729 |
// Label 357: @6921 |
3729 |
// Label 357: @6921 |
| 3730 |
GIM_Try, /*On fail goto*//*Label 358*/ 6942, // Rule ID 1983 // |
3730 |
GIM_Try, /*On fail goto*//*Label 358*/ 6942, // Rule ID 1983 // |
| 3731 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3731 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3732 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
3732 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3733 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3733 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3734 |
// (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }) |
3734 |
// (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }) |
| 3735 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3735 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3736 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3736 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3737 |
// GIR_Coverage, 1983, |
3737 |
// GIR_Coverage, 1983, |
| 3738 |
GIR_Done, |
3738 |
GIR_Done, |
| 3739 |
// Label 358: @6942 |
3739 |
// Label 358: @6942 |
| 3740 |
GIM_Try, /*On fail goto*//*Label 359*/ 6963, // Rule ID 1984 // |
3740 |
GIM_Try, /*On fail goto*//*Label 359*/ 6963, // Rule ID 1984 // |
| 3741 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3741 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3742 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3742 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3743 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3743 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3744 |
// (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] }) |
3744 |
// (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] }) |
| 3745 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3745 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3746 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3746 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3747 |
// GIR_Coverage, 1984, |
3747 |
// GIR_Coverage, 1984, |
| 3748 |
GIR_Done, |
3748 |
GIR_Done, |
| 3749 |
// Label 359: @6963 |
3749 |
// Label 359: @6963 |
| 3750 |
GIM_Try, /*On fail goto*//*Label 360*/ 6984, // Rule ID 1985 // |
3750 |
GIM_Try, /*On fail goto*//*Label 360*/ 6984, // Rule ID 1985 // |
| 3751 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
3751 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 3752 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
3752 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3753 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3753 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3754 |
// (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }) |
3754 |
// (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }) |
| 3755 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3755 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3756 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3756 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3757 |
// GIR_Coverage, 1985, |
3757 |
// GIR_Coverage, 1985, |
| 3758 |
GIR_Done, |
3758 |
GIR_Done, |
| 3759 |
// Label 360: @6984 |
3759 |
// Label 360: @6984 |
| 3760 |
GIM_Try, /*On fail goto*//*Label 361*/ 7049, // Rule ID 1993 // |
3760 |
GIM_Try, /*On fail goto*//*Label 361*/ 7049, // Rule ID 1993 // |
| 3761 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3761 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3762 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
3762 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3763 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3763 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3764 |
// (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }) |
3764 |
// (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }) |
| 3765 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
3765 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 3766 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
3766 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 3767 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3767 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3768 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3768 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3769 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3769 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3770 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3770 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3771 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
3771 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
| 3772 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3772 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3773 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3773 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3774 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
3774 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
| 3775 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3775 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3776 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3776 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3777 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3777 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3778 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3778 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3779 |
GIR_EraseFromParent, /*InsnID*/0, |
3779 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3780 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3780 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3781 |
// GIR_Coverage, 1993, |
3781 |
// GIR_Coverage, 1993, |
| 3782 |
GIR_Done, |
3782 |
GIR_Done, |
| 3783 |
// Label 361: @7049 |
3783 |
// Label 361: @7049 |
| 3784 |
GIM_Try, /*On fail goto*//*Label 362*/ 7114, // Rule ID 1994 // |
3784 |
GIM_Try, /*On fail goto*//*Label 362*/ 7114, // Rule ID 1994 // |
| 3785 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3785 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3786 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
3786 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3787 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3787 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3788 |
// (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }) |
3788 |
// (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }) |
| 3789 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
3789 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 3790 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
3790 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 3791 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3791 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3792 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3792 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3793 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3793 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3794 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3794 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3795 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
3795 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
| 3796 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3796 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3797 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3797 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3798 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
3798 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
| 3799 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3799 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3800 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3800 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3801 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3801 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3802 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3802 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3803 |
GIR_EraseFromParent, /*InsnID*/0, |
3803 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3804 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3804 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3805 |
// GIR_Coverage, 1994, |
3805 |
// GIR_Coverage, 1994, |
| 3806 |
GIR_Done, |
3806 |
GIR_Done, |
| 3807 |
// Label 362: @7114 |
3807 |
// Label 362: @7114 |
| 3808 |
GIM_Try, /*On fail goto*//*Label 363*/ 7179, // Rule ID 1998 // |
3808 |
GIM_Try, /*On fail goto*//*Label 363*/ 7179, // Rule ID 1998 // |
| 3809 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3809 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3810 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3810 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3811 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3811 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3812 |
// (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
3812 |
// (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
| 3813 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
3813 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 3814 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
3814 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 3815 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3815 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3816 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3816 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3817 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3817 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3818 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3818 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3819 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
3819 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 3820 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3820 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3821 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3821 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3822 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3822 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3823 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3823 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3824 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3824 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3825 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3825 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3826 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3826 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3827 |
GIR_EraseFromParent, /*InsnID*/0, |
3827 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3828 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3828 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3829 |
// GIR_Coverage, 1998, |
3829 |
// GIR_Coverage, 1998, |
| 3830 |
GIR_Done, |
3830 |
GIR_Done, |
| 3831 |
// Label 363: @7179 |
3831 |
// Label 363: @7179 |
| 3832 |
GIM_Try, /*On fail goto*//*Label 364*/ 7244, // Rule ID 1999 // |
3832 |
GIM_Try, /*On fail goto*//*Label 364*/ 7244, // Rule ID 1999 // |
| 3833 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3833 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3834 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3834 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3835 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3835 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3836 |
// (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
3836 |
// (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
| 3837 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
3837 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 3838 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
3838 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 3839 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3839 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3840 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3840 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3841 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3841 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3842 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3842 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3843 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
3843 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 3844 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3844 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3845 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3845 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3846 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3846 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3847 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3847 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3848 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3848 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3849 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3849 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3850 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3850 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3851 |
GIR_EraseFromParent, /*InsnID*/0, |
3851 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3852 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3852 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3853 |
// GIR_Coverage, 1999, |
3853 |
// GIR_Coverage, 1999, |
| 3854 |
GIR_Done, |
3854 |
GIR_Done, |
| 3855 |
// Label 364: @7244 |
3855 |
// Label 364: @7244 |
| 3856 |
GIM_Try, /*On fail goto*//*Label 365*/ 7309, // Rule ID 2003 // |
3856 |
GIM_Try, /*On fail goto*//*Label 365*/ 7309, // Rule ID 2003 // |
| 3857 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3857 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3858 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3858 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3859 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3859 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3860 |
// (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
3860 |
// (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
| 3861 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
3861 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 3862 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
3862 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 3863 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3863 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3864 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3864 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3865 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3865 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3866 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3866 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3867 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
3867 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 3868 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3868 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3869 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3869 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3870 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3870 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3871 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3871 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3872 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3872 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3873 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3873 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3874 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3874 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3875 |
GIR_EraseFromParent, /*InsnID*/0, |
3875 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3876 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3876 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3877 |
// GIR_Coverage, 2003, |
3877 |
// GIR_Coverage, 2003, |
| 3878 |
GIR_Done, |
3878 |
GIR_Done, |
| 3879 |
// Label 365: @7309 |
3879 |
// Label 365: @7309 |
| 3880 |
GIM_Try, /*On fail goto*//*Label 366*/ 7374, // Rule ID 2004 // |
3880 |
GIM_Try, /*On fail goto*//*Label 366*/ 7374, // Rule ID 2004 // |
| 3881 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3881 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3882 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
3882 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3883 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3883 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3884 |
// (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
3884 |
// (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
| 3885 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
3885 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 3886 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
3886 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 3887 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3887 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3888 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3888 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3889 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3889 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3890 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3890 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3891 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
3891 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 3892 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3892 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3893 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3893 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3894 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3894 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3895 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3895 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3896 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3896 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3897 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3897 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3898 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3898 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3899 |
GIR_EraseFromParent, /*InsnID*/0, |
3899 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3900 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3900 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3901 |
// GIR_Coverage, 2004, |
3901 |
// GIR_Coverage, 2004, |
| 3902 |
GIR_Done, |
3902 |
GIR_Done, |
| 3903 |
// Label 366: @7374 |
3903 |
// Label 366: @7374 |
| 3904 |
GIM_Try, /*On fail goto*//*Label 367*/ 7439, // Rule ID 2020 // |
3904 |
GIM_Try, /*On fail goto*//*Label 367*/ 7439, // Rule ID 2020 // |
| 3905 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3905 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3906 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
3906 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3907 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3907 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3908 |
// (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
3908 |
// (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
| 3909 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
3909 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3910 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
3910 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 3911 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3911 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3912 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3912 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3913 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3913 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3914 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3914 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3915 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
3915 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
| 3916 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3916 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3917 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3917 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3918 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3918 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3919 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3919 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3920 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3920 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3921 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3921 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3922 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3922 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3923 |
GIR_EraseFromParent, /*InsnID*/0, |
3923 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3924 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3924 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3925 |
// GIR_Coverage, 2020, |
3925 |
// GIR_Coverage, 2020, |
| 3926 |
GIR_Done, |
3926 |
GIR_Done, |
| 3927 |
// Label 367: @7439 |
3927 |
// Label 367: @7439 |
| 3928 |
GIM_Try, /*On fail goto*//*Label 368*/ 7504, // Rule ID 2021 // |
3928 |
GIM_Try, /*On fail goto*//*Label 368*/ 7504, // Rule ID 2021 // |
| 3929 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3929 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3930 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
3930 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3931 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3931 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3932 |
// (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
3932 |
// (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
| 3933 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
3933 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3934 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
3934 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 3935 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3935 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3936 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3936 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3937 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3937 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3938 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3938 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3939 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
3939 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
| 3940 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3940 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3941 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3941 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3942 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3942 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3943 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3943 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3944 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3944 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3945 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3945 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3946 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3946 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3947 |
GIR_EraseFromParent, /*InsnID*/0, |
3947 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3948 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3948 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3949 |
// GIR_Coverage, 2021, |
3949 |
// GIR_Coverage, 2021, |
| 3950 |
GIR_Done, |
3950 |
GIR_Done, |
| 3951 |
// Label 368: @7504 |
3951 |
// Label 368: @7504 |
| 3952 |
GIM_Try, /*On fail goto*//*Label 369*/ 7569, // Rule ID 2025 // |
3952 |
GIM_Try, /*On fail goto*//*Label 369*/ 7569, // Rule ID 2025 // |
| 3953 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3953 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3954 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
3954 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3955 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3955 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3956 |
// (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
3956 |
// (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
| 3957 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
3957 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3958 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
3958 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 3959 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3959 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3960 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3960 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3961 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3961 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3962 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3962 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3963 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
3963 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
| 3964 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3964 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3965 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3965 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3966 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3966 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3967 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3967 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3968 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3968 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3969 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3969 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3970 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3970 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3971 |
GIR_EraseFromParent, /*InsnID*/0, |
3971 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3972 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3972 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3973 |
// GIR_Coverage, 2025, |
3973 |
// GIR_Coverage, 2025, |
| 3974 |
GIR_Done, |
3974 |
GIR_Done, |
| 3975 |
// Label 369: @7569 |
3975 |
// Label 369: @7569 |
| 3976 |
GIM_Try, /*On fail goto*//*Label 370*/ 7634, // Rule ID 2026 // |
3976 |
GIM_Try, /*On fail goto*//*Label 370*/ 7634, // Rule ID 2026 // |
| 3977 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
3977 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 3978 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
3978 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 3979 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
3979 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 3980 |
// (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
3980 |
// (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] }) |
| 3981 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
3981 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3982 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
3982 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 3983 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
3983 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 3984 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
3984 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 3985 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
3985 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 3986 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
3986 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 3987 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
3987 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
| 3988 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
3988 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 3989 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
3989 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 3990 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
3990 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 3991 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
3991 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3992 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
3992 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 3993 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
3993 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 3994 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
3994 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 3995 |
GIR_EraseFromParent, /*InsnID*/0, |
3995 |
GIR_EraseFromParent, /*InsnID*/0, |
| 3996 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
3996 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128WRegClassID, |
| 3997 |
// GIR_Coverage, 2026, |
3997 |
// GIR_Coverage, 2026, |
| 3998 |
GIR_Done, |
3998 |
GIR_Done, |
| 3999 |
// Label 370: @7634 |
3999 |
// Label 370: @7634 |
| 4000 |
GIM_Reject, |
4000 |
GIM_Reject, |
| 4001 |
// Label 305: @7635 |
4001 |
// Label 305: @7635 |
| 4002 |
GIM_Try, /*On fail goto*//*Label 371*/ 7656, // Rule ID 1954 // |
4002 |
GIM_Try, /*On fail goto*//*Label 371*/ 7656, // Rule ID 1954 // |
| 4003 |
GIM_CheckFeatures, GIFBS_HasMSA, |
4003 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 4004 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
4004 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4005 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4005 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4006 |
// (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }) |
4006 |
// (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }) |
| 4007 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4007 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4008 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4008 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4009 |
// GIR_Coverage, 1954, |
4009 |
// GIR_Coverage, 1954, |
| 4010 |
GIR_Done, |
4010 |
GIR_Done, |
| 4011 |
// Label 371: @7656 |
4011 |
// Label 371: @7656 |
| 4012 |
GIM_Try, /*On fail goto*//*Label 372*/ 7677, // Rule ID 1957 // |
4012 |
GIM_Try, /*On fail goto*//*Label 372*/ 7677, // Rule ID 1957 // |
| 4013 |
GIM_CheckFeatures, GIFBS_HasMSA, |
4013 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 4014 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
4014 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4015 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4015 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4016 |
// (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }) |
4016 |
// (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }) |
| 4017 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4017 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4018 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4018 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4019 |
// GIR_Coverage, 1957, |
4019 |
// GIR_Coverage, 1957, |
| 4020 |
GIR_Done, |
4020 |
GIR_Done, |
| 4021 |
// Label 372: @7677 |
4021 |
// Label 372: @7677 |
| 4022 |
GIM_Try, /*On fail goto*//*Label 373*/ 7698, // Rule ID 1966 // |
4022 |
GIM_Try, /*On fail goto*//*Label 373*/ 7698, // Rule ID 1966 // |
| 4023 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
4023 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 4024 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
4024 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 4025 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4025 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4026 |
// (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] }) |
4026 |
// (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] }) |
| 4027 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4027 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4028 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4028 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4029 |
// GIR_Coverage, 1966, |
4029 |
// GIR_Coverage, 1966, |
| 4030 |
GIR_Done, |
4030 |
GIR_Done, |
| 4031 |
// Label 373: @7698 |
4031 |
// Label 373: @7698 |
| 4032 |
GIM_Try, /*On fail goto*//*Label 374*/ 7719, // Rule ID 1967 // |
4032 |
GIM_Try, /*On fail goto*//*Label 374*/ 7719, // Rule ID 1967 // |
| 4033 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
4033 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 4034 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
4034 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4035 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4035 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4036 |
// (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }) |
4036 |
// (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }) |
| 4037 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4037 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4038 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4038 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4039 |
// GIR_Coverage, 1967, |
4039 |
// GIR_Coverage, 1967, |
| 4040 |
GIR_Done, |
4040 |
GIR_Done, |
| 4041 |
// Label 374: @7719 |
4041 |
// Label 374: @7719 |
| 4042 |
GIM_Try, /*On fail goto*//*Label 375*/ 7740, // Rule ID 1968 // |
4042 |
GIM_Try, /*On fail goto*//*Label 375*/ 7740, // Rule ID 1968 // |
| 4043 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
4043 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 4044 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
4044 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 4045 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4045 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4046 |
// (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }) |
4046 |
// (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }) |
| 4047 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4047 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4048 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4048 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4049 |
// GIR_Coverage, 1968, |
4049 |
// GIR_Coverage, 1968, |
| 4050 |
GIR_Done, |
4050 |
GIR_Done, |
| 4051 |
// Label 375: @7740 |
4051 |
// Label 375: @7740 |
| 4052 |
GIM_Try, /*On fail goto*//*Label 376*/ 7761, // Rule ID 1969 // |
4052 |
GIM_Try, /*On fail goto*//*Label 376*/ 7761, // Rule ID 1969 // |
| 4053 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
4053 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 4054 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
4054 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4055 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4055 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4056 |
// (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }) |
4056 |
// (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }) |
| 4057 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4057 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4058 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4058 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4059 |
// GIR_Coverage, 1969, |
4059 |
// GIR_Coverage, 1969, |
| 4060 |
GIR_Done, |
4060 |
GIR_Done, |
| 4061 |
// Label 376: @7761 |
4061 |
// Label 376: @7761 |
| 4062 |
GIM_Try, /*On fail goto*//*Label 377*/ 7782, // Rule ID 1970 // |
4062 |
GIM_Try, /*On fail goto*//*Label 377*/ 7782, // Rule ID 1970 // |
| 4063 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
4063 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 4064 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
4064 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 4065 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4065 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4066 |
// (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }) |
4066 |
// (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }) |
| 4067 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4067 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4068 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4068 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4069 |
// GIR_Coverage, 1970, |
4069 |
// GIR_Coverage, 1970, |
| 4070 |
GIR_Done, |
4070 |
GIR_Done, |
| 4071 |
// Label 377: @7782 |
4071 |
// Label 377: @7782 |
| 4072 |
GIM_Try, /*On fail goto*//*Label 378*/ 7847, // Rule ID 1991 // |
4072 |
GIM_Try, /*On fail goto*//*Label 378*/ 7847, // Rule ID 1991 // |
| 4073 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4073 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4074 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
4074 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 4075 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4075 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4076 |
// (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) |
4076 |
// (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) |
| 4077 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
4077 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 4078 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
4078 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 4079 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4079 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4080 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4080 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4081 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4081 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4082 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4082 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4083 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
4083 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
| 4084 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4084 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4085 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4085 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4086 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
4086 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 4087 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4087 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4088 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4088 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4089 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4089 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4090 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4090 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4091 |
GIR_EraseFromParent, /*InsnID*/0, |
4091 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4092 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4092 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4093 |
// GIR_Coverage, 1991, |
4093 |
// GIR_Coverage, 1991, |
| 4094 |
GIR_Done, |
4094 |
GIR_Done, |
| 4095 |
// Label 378: @7847 |
4095 |
// Label 378: @7847 |
| 4096 |
GIM_Try, /*On fail goto*//*Label 379*/ 7912, // Rule ID 1992 // |
4096 |
GIM_Try, /*On fail goto*//*Label 379*/ 7912, // Rule ID 1992 // |
| 4097 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4097 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4098 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
4098 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 4099 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4099 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4100 |
// (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) |
4100 |
// (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) |
| 4101 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
4101 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 4102 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
4102 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 4103 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4103 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4104 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4104 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4105 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4105 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4106 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4106 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4107 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
4107 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
| 4108 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4108 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4109 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4109 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4110 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
4110 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 4111 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4111 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4112 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4112 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4113 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4113 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4114 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4114 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4115 |
GIR_EraseFromParent, /*InsnID*/0, |
4115 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4116 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4116 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4117 |
// GIR_Coverage, 1992, |
4117 |
// GIR_Coverage, 1992, |
| 4118 |
GIR_Done, |
4118 |
GIR_Done, |
| 4119 |
// Label 379: @7912 |
4119 |
// Label 379: @7912 |
| 4120 |
GIM_Try, /*On fail goto*//*Label 380*/ 7977, // Rule ID 2008 // |
4120 |
GIM_Try, /*On fail goto*//*Label 380*/ 7977, // Rule ID 2008 // |
| 4121 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4121 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4122 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
4122 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4123 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4123 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4124 |
// (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) |
4124 |
// (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) |
| 4125 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
4125 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 4126 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
4126 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 4127 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4127 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4128 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4128 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4129 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4129 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4130 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4130 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4131 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
4131 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 4132 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4132 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4133 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4133 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4134 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
4134 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 4135 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4135 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4136 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4136 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4137 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4137 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4138 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4138 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4139 |
GIR_EraseFromParent, /*InsnID*/0, |
4139 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4140 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4140 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4141 |
// GIR_Coverage, 2008, |
4141 |
// GIR_Coverage, 2008, |
| 4142 |
GIR_Done, |
4142 |
GIR_Done, |
| 4143 |
// Label 380: @7977 |
4143 |
// Label 380: @7977 |
| 4144 |
GIM_Try, /*On fail goto*//*Label 381*/ 8042, // Rule ID 2009 // |
4144 |
GIM_Try, /*On fail goto*//*Label 381*/ 8042, // Rule ID 2009 // |
| 4145 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4145 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4146 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
4146 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4147 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4147 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4148 |
// (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) |
4148 |
// (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) |
| 4149 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
4149 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 4150 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
4150 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 4151 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4151 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4152 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4152 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4153 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4153 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4154 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4154 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4155 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
4155 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 4156 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4156 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4157 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4157 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4158 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
4158 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 4159 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4159 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4160 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4160 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4161 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4161 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4162 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4162 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4163 |
GIR_EraseFromParent, /*InsnID*/0, |
4163 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4164 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4164 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4165 |
// GIR_Coverage, 2009, |
4165 |
// GIR_Coverage, 2009, |
| 4166 |
GIR_Done, |
4166 |
GIR_Done, |
| 4167 |
// Label 381: @8042 |
4167 |
// Label 381: @8042 |
| 4168 |
GIM_Try, /*On fail goto*//*Label 382*/ 8107, // Rule ID 2013 // |
4168 |
GIM_Try, /*On fail goto*//*Label 382*/ 8107, // Rule ID 2013 // |
| 4169 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4169 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4170 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
4170 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4171 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4171 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4172 |
// (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) |
4172 |
// (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) |
| 4173 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
4173 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 4174 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
4174 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 4175 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4175 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4176 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4176 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4177 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4177 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4178 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4178 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4179 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
4179 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 4180 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4180 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4181 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4181 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4182 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
4182 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 4183 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4183 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4184 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4184 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4185 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4185 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4186 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4186 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4187 |
GIR_EraseFromParent, /*InsnID*/0, |
4187 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4188 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4188 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4189 |
// GIR_Coverage, 2013, |
4189 |
// GIR_Coverage, 2013, |
| 4190 |
GIR_Done, |
4190 |
GIR_Done, |
| 4191 |
// Label 382: @8107 |
4191 |
// Label 382: @8107 |
| 4192 |
GIM_Try, /*On fail goto*//*Label 383*/ 8172, // Rule ID 2014 // |
4192 |
GIM_Try, /*On fail goto*//*Label 383*/ 8172, // Rule ID 2014 // |
| 4193 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4193 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4194 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
4194 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4195 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4195 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4196 |
// (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) |
4196 |
// (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] }) |
| 4197 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
4197 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 4198 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
4198 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 4199 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4199 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4200 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4200 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4201 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4201 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4202 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4202 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4203 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
4203 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 4204 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4204 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4205 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4205 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4206 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
4206 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 4207 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4207 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4208 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4208 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4209 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4209 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4210 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4210 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4211 |
GIR_EraseFromParent, /*InsnID*/0, |
4211 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4212 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4212 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4213 |
// GIR_Coverage, 2014, |
4213 |
// GIR_Coverage, 2014, |
| 4214 |
GIR_Done, |
4214 |
GIR_Done, |
| 4215 |
// Label 383: @8172 |
4215 |
// Label 383: @8172 |
| 4216 |
GIM_Try, /*On fail goto*//*Label 384*/ 8237, // Rule ID 2018 // |
4216 |
GIM_Try, /*On fail goto*//*Label 384*/ 8237, // Rule ID 2018 // |
| 4217 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4217 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4218 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
4218 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 4219 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4219 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4220 |
// (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] }) |
4220 |
// (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] }) |
| 4221 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
4221 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 4222 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
4222 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 4223 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4223 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4224 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4224 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4225 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4225 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4226 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4226 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4227 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
4227 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 4228 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4228 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4229 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4229 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4230 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
4230 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
| 4231 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4231 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4232 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4232 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4233 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4233 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4234 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4234 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4235 |
GIR_EraseFromParent, /*InsnID*/0, |
4235 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4236 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4236 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4237 |
// GIR_Coverage, 2018, |
4237 |
// GIR_Coverage, 2018, |
| 4238 |
GIR_Done, |
4238 |
GIR_Done, |
| 4239 |
// Label 384: @8237 |
4239 |
// Label 384: @8237 |
| 4240 |
GIM_Try, /*On fail goto*//*Label 385*/ 8302, // Rule ID 2019 // |
4240 |
GIM_Try, /*On fail goto*//*Label 385*/ 8302, // Rule ID 2019 // |
| 4241 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4241 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4242 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
4242 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 4243 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4243 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4244 |
// (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] }) |
4244 |
// (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] }) |
| 4245 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
4245 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 4246 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
4246 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 4247 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4247 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4248 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4248 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4249 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4249 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4250 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4250 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4251 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
4251 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 4252 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4252 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4253 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4253 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4254 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
4254 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
| 4255 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4255 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4256 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4256 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4257 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4257 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4258 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4258 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4259 |
GIR_EraseFromParent, /*InsnID*/0, |
4259 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4260 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4260 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4261 |
// GIR_Coverage, 2019, |
4261 |
// GIR_Coverage, 2019, |
| 4262 |
GIR_Done, |
4262 |
GIR_Done, |
| 4263 |
// Label 385: @8302 |
4263 |
// Label 385: @8302 |
| 4264 |
GIM_Try, /*On fail goto*//*Label 386*/ 8367, // Rule ID 2023 // |
4264 |
GIM_Try, /*On fail goto*//*Label 386*/ 8367, // Rule ID 2023 // |
| 4265 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4265 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4266 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
4266 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 4267 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4267 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4268 |
// (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] }) |
4268 |
// (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] }) |
| 4269 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
4269 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 4270 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
4270 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 4271 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4271 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4272 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4272 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4273 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4273 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4274 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4274 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4275 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
4275 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 4276 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4276 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4277 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4277 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4278 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
4278 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
| 4279 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4279 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4280 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4280 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4281 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4281 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4282 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4282 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4283 |
GIR_EraseFromParent, /*InsnID*/0, |
4283 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4284 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4284 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4285 |
// GIR_Coverage, 2023, |
4285 |
// GIR_Coverage, 2023, |
| 4286 |
GIR_Done, |
4286 |
GIR_Done, |
| 4287 |
// Label 386: @8367 |
4287 |
// Label 386: @8367 |
| 4288 |
GIM_Try, /*On fail goto*//*Label 387*/ 8432, // Rule ID 2024 // |
4288 |
GIM_Try, /*On fail goto*//*Label 387*/ 8432, // Rule ID 2024 // |
| 4289 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4289 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4290 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
4290 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 4291 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
4291 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 4292 |
// (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] }) |
4292 |
// (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] }) |
| 4293 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
4293 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 4294 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
4294 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 4295 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4295 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4296 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4296 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4297 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4297 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4298 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4298 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4299 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
4299 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H, |
| 4300 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4300 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4301 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4301 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4302 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
4302 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
| 4303 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4303 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4304 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4304 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4305 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4305 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4306 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4306 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4307 |
GIR_EraseFromParent, /*InsnID*/0, |
4307 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4308 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
4308 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128HRegClassID, |
| 4309 |
// GIR_Coverage, 2024, |
4309 |
// GIR_Coverage, 2024, |
| 4310 |
GIR_Done, |
4310 |
GIR_Done, |
| 4311 |
// Label 387: @8432 |
4311 |
// Label 387: @8432 |
| 4312 |
GIM_Reject, |
4312 |
GIM_Reject, |
| 4313 |
// Label 306: @8433 |
4313 |
// Label 306: @8433 |
| 4314 |
GIM_Try, /*On fail goto*//*Label 388*/ 8454, // Rule ID 1960 // |
4314 |
GIM_Try, /*On fail goto*//*Label 388*/ 8454, // Rule ID 1960 // |
| 4315 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
4315 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 4316 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
4316 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4317 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
4317 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 4318 |
// (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }) |
4318 |
// (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }) |
| 4319 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4319 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4320 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
4320 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
| 4321 |
// GIR_Coverage, 1960, |
4321 |
// GIR_Coverage, 1960, |
| 4322 |
GIR_Done, |
4322 |
GIR_Done, |
| 4323 |
// Label 388: @8454 |
4323 |
// Label 388: @8454 |
| 4324 |
GIM_Try, /*On fail goto*//*Label 389*/ 8475, // Rule ID 1961 // |
4324 |
GIM_Try, /*On fail goto*//*Label 389*/ 8475, // Rule ID 1961 // |
| 4325 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
4325 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 4326 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
4326 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4327 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
4327 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 4328 |
// (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }) |
4328 |
// (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }) |
| 4329 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4329 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4330 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
4330 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
| 4331 |
// GIR_Coverage, 1961, |
4331 |
// GIR_Coverage, 1961, |
| 4332 |
GIR_Done, |
4332 |
GIR_Done, |
| 4333 |
// Label 389: @8475 |
4333 |
// Label 389: @8475 |
| 4334 |
GIM_Try, /*On fail goto*//*Label 390*/ 8496, // Rule ID 1962 // |
4334 |
GIM_Try, /*On fail goto*//*Label 390*/ 8496, // Rule ID 1962 // |
| 4335 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
4335 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 4336 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
4336 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 4337 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
4337 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 4338 |
// (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }) |
4338 |
// (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }) |
| 4339 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4339 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4340 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
4340 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
| 4341 |
// GIR_Coverage, 1962, |
4341 |
// GIR_Coverage, 1962, |
| 4342 |
GIR_Done, |
4342 |
GIR_Done, |
| 4343 |
// Label 390: @8496 |
4343 |
// Label 390: @8496 |
| 4344 |
GIM_Try, /*On fail goto*//*Label 391*/ 8517, // Rule ID 1963 // |
4344 |
GIM_Try, /*On fail goto*//*Label 391*/ 8517, // Rule ID 1963 // |
| 4345 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
4345 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 4346 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
4346 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4347 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
4347 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 4348 |
// (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }) |
4348 |
// (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }) |
| 4349 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4349 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4350 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
4350 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
| 4351 |
// GIR_Coverage, 1963, |
4351 |
// GIR_Coverage, 1963, |
| 4352 |
GIR_Done, |
4352 |
GIR_Done, |
| 4353 |
// Label 391: @8517 |
4353 |
// Label 391: @8517 |
| 4354 |
GIM_Try, /*On fail goto*//*Label 392*/ 8538, // Rule ID 1964 // |
4354 |
GIM_Try, /*On fail goto*//*Label 392*/ 8538, // Rule ID 1964 // |
| 4355 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
4355 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 4356 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
4356 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4357 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
4357 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 4358 |
// (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }) |
4358 |
// (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }) |
| 4359 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4359 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4360 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
4360 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
| 4361 |
// GIR_Coverage, 1964, |
4361 |
// GIR_Coverage, 1964, |
| 4362 |
GIR_Done, |
4362 |
GIR_Done, |
| 4363 |
// Label 392: @8538 |
4363 |
// Label 392: @8538 |
| 4364 |
GIM_Try, /*On fail goto*//*Label 393*/ 8559, // Rule ID 1965 // |
4364 |
GIM_Try, /*On fail goto*//*Label 393*/ 8559, // Rule ID 1965 // |
| 4365 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
4365 |
GIM_CheckFeatures, GIFBS_HasMSA_IsLE, |
| 4366 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
4366 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 4367 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
4367 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 4368 |
// (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }) |
4368 |
// (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }) |
| 4369 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4369 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4370 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
4370 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
| 4371 |
// GIR_Coverage, 1965, |
4371 |
// GIR_Coverage, 1965, |
| 4372 |
GIR_Done, |
4372 |
GIR_Done, |
| 4373 |
// Label 393: @8559 |
4373 |
// Label 393: @8559 |
| 4374 |
GIM_Try, /*On fail goto*//*Label 394*/ 8624, // Rule ID 1997 // |
4374 |
GIM_Try, /*On fail goto*//*Label 394*/ 8624, // Rule ID 1997 // |
| 4375 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4375 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4376 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
4376 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4377 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
4377 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 4378 |
// (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] }) |
4378 |
// (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] }) |
| 4379 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
4379 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 4380 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
4380 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 4381 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4381 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4382 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4382 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4383 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4383 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4384 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4384 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4385 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
4385 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
| 4386 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4386 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4387 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4387 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4388 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
4388 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 4389 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4389 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4390 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4390 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4391 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4391 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4392 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4392 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4393 |
GIR_EraseFromParent, /*InsnID*/0, |
4393 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4394 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
4394 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
| 4395 |
// GIR_Coverage, 1997, |
4395 |
// GIR_Coverage, 1997, |
| 4396 |
GIR_Done, |
4396 |
GIR_Done, |
| 4397 |
// Label 394: @8624 |
4397 |
// Label 394: @8624 |
| 4398 |
GIM_Try, /*On fail goto*//*Label 395*/ 8689, // Rule ID 2002 // |
4398 |
GIM_Try, /*On fail goto*//*Label 395*/ 8689, // Rule ID 2002 // |
| 4399 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4399 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4400 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
4400 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 4401 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
4401 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 4402 |
// (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] }) |
4402 |
// (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] }) |
| 4403 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
4403 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 4404 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
4404 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 4405 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4405 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4406 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4406 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4407 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4407 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4408 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4408 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4409 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
4409 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
| 4410 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4410 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4411 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4411 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4412 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
4412 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 4413 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4413 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4414 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4414 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4415 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4415 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4416 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4416 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4417 |
GIR_EraseFromParent, /*InsnID*/0, |
4417 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4418 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
4418 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
| 4419 |
// GIR_Coverage, 2002, |
4419 |
// GIR_Coverage, 2002, |
| 4420 |
GIR_Done, |
4420 |
GIR_Done, |
| 4421 |
// Label 395: @8689 |
4421 |
// Label 395: @8689 |
| 4422 |
GIM_Try, /*On fail goto*//*Label 396*/ 8754, // Rule ID 2007 // |
4422 |
GIM_Try, /*On fail goto*//*Label 396*/ 8754, // Rule ID 2007 // |
| 4423 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4423 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4424 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
4424 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4425 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
4425 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 4426 |
// (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] }) |
4426 |
// (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] }) |
| 4427 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
4427 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 4428 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
4428 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 4429 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4429 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4430 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4430 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4431 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4431 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4432 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4432 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4433 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
4433 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
| 4434 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4434 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4435 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4435 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4436 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
4436 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
| 4437 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4437 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4438 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4438 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4439 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4439 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4440 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4440 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4441 |
GIR_EraseFromParent, /*InsnID*/0, |
4441 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4442 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
4442 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
| 4443 |
// GIR_Coverage, 2007, |
4443 |
// GIR_Coverage, 2007, |
| 4444 |
GIR_Done, |
4444 |
GIR_Done, |
| 4445 |
// Label 396: @8754 |
4445 |
// Label 396: @8754 |
| 4446 |
GIM_Try, /*On fail goto*//*Label 397*/ 8819, // Rule ID 2012 // |
4446 |
GIM_Try, /*On fail goto*//*Label 397*/ 8819, // Rule ID 2012 // |
| 4447 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4447 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4448 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
4448 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4449 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
4449 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 4450 |
// (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] }) |
4450 |
// (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] }) |
| 4451 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
4451 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 4452 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
4452 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 4453 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4453 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4454 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4454 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4455 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
4455 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4456 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4456 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4457 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
4457 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B, |
| 4458 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4458 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4459 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4459 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4460 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
4460 |
GIR_AddImm, /*InsnID*/1, /*Imm*/27, |
| 4461 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4461 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4462 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4462 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4463 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4463 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4464 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4464 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4465 |
GIR_EraseFromParent, /*InsnID*/0, |
4465 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4466 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
4466 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
| 4467 |
// GIR_Coverage, 2012, |
4467 |
// GIR_Coverage, 2012, |
| 4468 |
GIR_Done, |
4468 |
GIR_Done, |
| 4469 |
// Label 397: @8819 |
4469 |
// Label 397: @8819 |
| 4470 |
GIM_Try, /*On fail goto*//*Label 398*/ 8919, // Rule ID 2017 // |
4470 |
GIM_Try, /*On fail goto*//*Label 398*/ 8919, // Rule ID 2017 // |
| 4471 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4471 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4472 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
4472 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 4473 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
4473 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 4474 |
// (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] }) |
4474 |
// (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] }) |
| 4475 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
4475 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 4476 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
4476 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 4477 |
GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, |
4477 |
GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, |
| 4478 |
GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, |
4478 |
GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, |
| 4479 |
GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY, |
4479 |
GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY, |
| 4480 |
GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
4480 |
GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 4481 |
GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src |
4481 |
GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4482 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
4482 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 4483 |
GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B, |
4483 |
GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B, |
| 4484 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
4484 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 4485 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
4485 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 4486 |
GIR_AddImm, /*InsnID*/3, /*Imm*/27, |
4486 |
GIR_AddImm, /*InsnID*/3, /*Imm*/27, |
| 4487 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
4487 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 4488 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4488 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4489 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4489 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4490 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
4490 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 4491 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4491 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4492 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
4492 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
| 4493 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4493 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4494 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4494 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4495 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
4495 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 4496 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4496 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4497 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4497 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4498 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4498 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4499 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4499 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4500 |
GIR_EraseFromParent, /*InsnID*/0, |
4500 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4501 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
4501 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
| 4502 |
// GIR_Coverage, 2017, |
4502 |
// GIR_Coverage, 2017, |
| 4503 |
GIR_Done, |
4503 |
GIR_Done, |
| 4504 |
// Label 398: @8919 |
4504 |
// Label 398: @8919 |
| 4505 |
GIM_Try, /*On fail goto*//*Label 399*/ 9019, // Rule ID 2022 // |
4505 |
GIM_Try, /*On fail goto*//*Label 399*/ 9019, // Rule ID 2022 // |
| 4506 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
4506 |
GIM_CheckFeatures, GIFBS_HasMSA_IsBE, |
| 4507 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
4507 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 4508 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
4508 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 4509 |
// (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] }) |
4509 |
// (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] }) |
| 4510 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
4510 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 4511 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
4511 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 4512 |
GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, |
4512 |
GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, |
| 4513 |
GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, |
4513 |
GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, |
| 4514 |
GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY, |
4514 |
GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY, |
| 4515 |
GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
4515 |
GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 4516 |
GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src |
4516 |
GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 4517 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
4517 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 4518 |
GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B, |
4518 |
GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B, |
| 4519 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
4519 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 4520 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
4520 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 4521 |
GIR_AddImm, /*InsnID*/3, /*Imm*/27, |
4521 |
GIR_AddImm, /*InsnID*/3, /*Imm*/27, |
| 4522 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
4522 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 4523 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
4523 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, |
| 4524 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
4524 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 4525 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
4525 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0, |
| 4526 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
4526 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4527 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
4527 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W, |
| 4528 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
4528 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 4529 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
4529 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 4530 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
4530 |
GIR_AddImm, /*InsnID*/1, /*Imm*/177, |
| 4531 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
4531 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4532 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
4532 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 4533 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
4533 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 4534 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
4534 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 4535 |
GIR_EraseFromParent, /*InsnID*/0, |
4535 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4536 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
4536 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::MSA128BRegClassID, |
| 4537 |
// GIR_Coverage, 2022, |
4537 |
// GIR_Coverage, 2022, |
| 4538 |
GIR_Done, |
4538 |
GIR_Done, |
| 4539 |
// Label 399: @9019 |
4539 |
// Label 399: @9019 |
| 4540 |
GIM_Reject, |
4540 |
GIM_Reject, |
| 4541 |
// Label 307: @9020 |
4541 |
// Label 307: @9020 |
| 4542 |
GIM_Reject, |
4542 |
GIM_Reject, |
| 4543 |
// Label 13: @9021 |
4543 |
// Label 13: @9021 |
| 4544 |
GIM_Try, /*On fail goto*//*Label 400*/ 9086, // Rule ID 1945 // |
4544 |
GIM_Try, /*On fail goto*//*Label 400*/ 9086, // Rule ID 1945 // |
| 4545 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4545 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4546 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
4546 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 4547 |
GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
4547 |
GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 4548 |
GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
4548 |
GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 4549 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
4549 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 4550 |
// MIs[0] Operand 1 |
4550 |
// MIs[0] Operand 1 |
| 4551 |
GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
4551 |
GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 4552 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
4552 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4553 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, |
4553 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, |
| 4554 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
4554 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4555 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
4555 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4556 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
4556 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4557 |
// (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<><> => (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index) |
4557 |
// (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<><> => (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index) |
| 4558 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LWX, |
4558 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LWX, |
| 4559 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4559 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4560 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base |
4560 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base |
| 4561 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index |
4561 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index |
| 4562 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
4562 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 4563 |
GIR_EraseFromParent, /*InsnID*/0, |
4563 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4564 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4564 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4565 |
// GIR_Coverage, 1945, |
4565 |
// GIR_Coverage, 1945, |
| 4566 |
GIR_Done, |
4566 |
GIR_Done, |
| 4567 |
// Label 400: @9086 |
4567 |
// Label 400: @9086 |
| 4568 |
GIM_Reject, |
4568 |
GIM_Reject, |
| 4569 |
// Label 14: @9087 |
4569 |
// Label 14: @9087 |
| 4570 |
GIM_Try, /*On fail goto*//*Label 401*/ 9152, // Rule ID 1944 // |
4570 |
GIM_Try, /*On fail goto*//*Label 401*/ 9152, // Rule ID 1944 // |
| 4571 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4571 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4572 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
4572 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 4573 |
GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
4573 |
GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, |
| 4574 |
GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
4574 |
GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 4575 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
4575 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 4576 |
// MIs[0] Operand 1 |
4576 |
// MIs[0] Operand 1 |
| 4577 |
GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
4577 |
GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 4578 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
4578 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4579 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, |
4579 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, |
| 4580 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
4580 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4581 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
4581 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4582 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
4582 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4583 |
// (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<><><> => (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index) |
4583 |
// (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<><><> => (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index) |
| 4584 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LHX, |
4584 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LHX, |
| 4585 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4585 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4586 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base |
4586 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base |
| 4587 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index |
4587 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index |
| 4588 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
4588 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 4589 |
GIR_EraseFromParent, /*InsnID*/0, |
4589 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4590 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4590 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4591 |
// GIR_Coverage, 1944, |
4591 |
// GIR_Coverage, 1944, |
| 4592 |
GIR_Done, |
4592 |
GIR_Done, |
| 4593 |
// Label 401: @9152 |
4593 |
// Label 401: @9152 |
| 4594 |
GIM_Reject, |
4594 |
GIM_Reject, |
| 4595 |
// Label 15: @9153 |
4595 |
// Label 15: @9153 |
| 4596 |
GIM_Try, /*On fail goto*//*Label 402*/ 9218, // Rule ID 1943 // |
4596 |
GIM_Try, /*On fail goto*//*Label 402*/ 9218, // Rule ID 1943 // |
| 4597 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4597 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4598 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
4598 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 4599 |
GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
4599 |
GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, |
| 4600 |
GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
4600 |
GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, |
| 4601 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
4601 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 4602 |
// MIs[0] Operand 1 |
4602 |
// MIs[0] Operand 1 |
| 4603 |
GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
4603 |
GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 4604 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
4604 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4605 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, |
4605 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, |
| 4606 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
4606 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4607 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
4607 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4608 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
4608 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4609 |
// (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<><><> => (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index) |
4609 |
// (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<><><> => (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index) |
| 4610 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LBUX, |
4610 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LBUX, |
| 4611 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4611 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4612 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base |
4612 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base |
| 4613 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index |
4613 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index |
| 4614 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
4614 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 4615 |
GIR_EraseFromParent, /*InsnID*/0, |
4615 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4616 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4616 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4617 |
// GIR_Coverage, 1943, |
4617 |
// GIR_Coverage, 1943, |
| 4618 |
GIR_Done, |
4618 |
GIR_Done, |
| 4619 |
// Label 402: @9218 |
4619 |
// Label 402: @9218 |
| 4620 |
GIM_Reject, |
4620 |
GIM_Reject, |
| 4621 |
// Label 16: @9219 |
4621 |
// Label 16: @9219 |
| 4622 |
GIM_Try, /*On fail goto*//*Label 403*/ 11413, |
4622 |
GIM_Try, /*On fail goto*//*Label 403*/ 11413, |
| 4623 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
4623 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 4624 |
GIM_Try, /*On fail goto*//*Label 404*/ 9271, // Rule ID 416 // |
4624 |
GIM_Try, /*On fail goto*//*Label 404*/ 9271, // Rule ID 416 // |
| 4625 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4625 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4626 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb, |
4626 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb, |
| 4627 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
4627 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 4628 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
4628 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 4629 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4629 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4630 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
4630 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4631 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
4631 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 4632 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt8, |
4632 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt8, |
| 4633 |
// MIs[1] Operand 1 |
4633 |
// MIs[1] Operand 1 |
| 4634 |
// No operand predicates |
4634 |
// No operand predicates |
| 4635 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
4635 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4636 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5769:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm) => (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm) |
4636 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5769:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm) => (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm) |
| 4637 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB, |
4637 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB, |
| 4638 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4638 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4639 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
4639 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4640 |
GIR_EraseFromParent, /*InsnID*/0, |
4640 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4641 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4641 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4642 |
// GIR_Coverage, 416, |
4642 |
// GIR_Coverage, 416, |
| 4643 |
GIR_Done, |
4643 |
GIR_Done, |
| 4644 |
// Label 404: @9271 |
4644 |
// Label 404: @9271 |
| 4645 |
GIM_Try, /*On fail goto*//*Label 405*/ 9318, // Rule ID 417 // |
4645 |
GIM_Try, /*On fail goto*//*Label 405*/ 9318, // Rule ID 417 // |
| 4646 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4646 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4647 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph, |
4647 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph, |
| 4648 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
4648 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 4649 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
4649 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 4650 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4650 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4651 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
4651 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4652 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
4652 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 4653 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immSExt10, |
4653 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immSExt10, |
| 4654 |
// MIs[1] Operand 1 |
4654 |
// MIs[1] Operand 1 |
| 4655 |
// No operand predicates |
4655 |
// No operand predicates |
| 4656 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
4656 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4657 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5768:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm) => (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm) |
4657 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5768:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm) => (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm) |
| 4658 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH, |
4658 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH, |
| 4659 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4659 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4660 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
4660 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4661 |
GIR_EraseFromParent, /*InsnID*/0, |
4661 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4662 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4662 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4663 |
// GIR_Coverage, 417, |
4663 |
// GIR_Coverage, 417, |
| 4664 |
GIR_Done, |
4664 |
GIR_Done, |
| 4665 |
// Label 405: @9318 |
4665 |
// Label 405: @9318 |
| 4666 |
GIM_Try, /*On fail goto*//*Label 406*/ 9365, // Rule ID 1276 // |
4666 |
GIM_Try, /*On fail goto*//*Label 406*/ 9365, // Rule ID 1276 // |
| 4667 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
4667 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 4668 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph, |
4668 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph, |
| 4669 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
4669 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 4670 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
4670 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 4671 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4671 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4672 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
4672 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4673 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
4673 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 4674 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immSExt10, |
4674 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immSExt10, |
| 4675 |
// MIs[1] Operand 1 |
4675 |
// MIs[1] Operand 1 |
| 4676 |
// No operand predicates |
4676 |
// No operand predicates |
| 4677 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
4677 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4678 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5768:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm) => (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm) |
4678 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5768:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm) => (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm) |
| 4679 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH_MM, |
4679 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH_MM, |
| 4680 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4680 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4681 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
4681 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4682 |
GIR_EraseFromParent, /*InsnID*/0, |
4682 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4683 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4683 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4684 |
// GIR_Coverage, 1276, |
4684 |
// GIR_Coverage, 1276, |
| 4685 |
GIR_Done, |
4685 |
GIR_Done, |
| 4686 |
// Label 406: @9365 |
4686 |
// Label 406: @9365 |
| 4687 |
GIM_Try, /*On fail goto*//*Label 407*/ 9412, // Rule ID 1277 // |
4687 |
GIM_Try, /*On fail goto*//*Label 407*/ 9412, // Rule ID 1277 // |
| 4688 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
4688 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 4689 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb, |
4689 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb, |
| 4690 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
4690 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 4691 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
4691 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 4692 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4692 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4693 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
4693 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4694 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
4694 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 4695 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt8, |
4695 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt8, |
| 4696 |
// MIs[1] Operand 1 |
4696 |
// MIs[1] Operand 1 |
| 4697 |
// No operand predicates |
4697 |
// No operand predicates |
| 4698 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
4698 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 4699 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5769:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm) => (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm) |
4699 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5769:{ *:[iPTR] }, (imm:{ *:[i32] })<>:$imm) => (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm) |
| 4700 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB_MM, |
4700 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB_MM, |
| 4701 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
4701 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 4702 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
4702 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4703 |
GIR_EraseFromParent, /*InsnID*/0, |
4703 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4704 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4704 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4705 |
// GIR_Coverage, 1277, |
4705 |
// GIR_Coverage, 1277, |
| 4706 |
GIR_Done, |
4706 |
GIR_Done, |
| 4707 |
// Label 407: @9412 |
4707 |
// Label 407: @9412 |
| 4708 |
GIM_Try, /*On fail goto*//*Label 408*/ 9452, // Rule ID 350 // |
4708 |
GIM_Try, /*On fail goto*//*Label 408*/ 9452, // Rule ID 350 // |
| 4709 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4709 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4710 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb, |
4710 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb, |
| 4711 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
4711 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 4712 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
4712 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 4713 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
4713 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 4714 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
4714 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 4715 |
// (intrinsic_wo_chain:{ *:[i32] } 5766:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs) |
4715 |
// (intrinsic_wo_chain:{ *:[i32] } 5766:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs) |
| 4716 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB, |
4716 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB, |
| 4717 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4717 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4718 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
4718 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 4719 |
GIR_EraseFromParent, /*InsnID*/0, |
4719 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4720 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4720 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4721 |
// GIR_Coverage, 350, |
4721 |
// GIR_Coverage, 350, |
| 4722 |
GIR_Done, |
4722 |
GIR_Done, |
| 4723 |
// Label 408: @9452 |
4723 |
// Label 408: @9452 |
| 4724 |
GIM_Try, /*On fail goto*//*Label 409*/ 9492, // Rule ID 357 // |
4724 |
GIM_Try, /*On fail goto*//*Label 409*/ 9492, // Rule ID 357 // |
| 4725 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4725 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4726 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl, |
4726 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl, |
| 4727 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
4727 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 4728 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
4728 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 4729 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
4729 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 4730 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
4730 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 4731 |
// (intrinsic_wo_chain:{ *:[i32] } 5748:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt) |
4731 |
// (intrinsic_wo_chain:{ *:[i32] } 5748:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt) |
| 4732 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL, |
4732 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL, |
| 4733 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4733 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4734 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
4734 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 4735 |
GIR_EraseFromParent, /*InsnID*/0, |
4735 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4736 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4736 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4737 |
// GIR_Coverage, 357, |
4737 |
// GIR_Coverage, 357, |
| 4738 |
GIR_Done, |
4738 |
GIR_Done, |
| 4739 |
// Label 409: @9492 |
4739 |
// Label 409: @9492 |
| 4740 |
GIM_Try, /*On fail goto*//*Label 410*/ 9532, // Rule ID 358 // |
4740 |
GIM_Try, /*On fail goto*//*Label 410*/ 9532, // Rule ID 358 // |
| 4741 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4741 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4742 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr, |
4742 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr, |
| 4743 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
4743 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 4744 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
4744 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 4745 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
4745 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 4746 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
4746 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 4747 |
// (intrinsic_wo_chain:{ *:[i32] } 5749:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt) |
4747 |
// (intrinsic_wo_chain:{ *:[i32] } 5749:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt) |
| 4748 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR, |
4748 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR, |
| 4749 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4749 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4750 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
4750 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 4751 |
GIR_EraseFromParent, /*InsnID*/0, |
4751 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4752 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4752 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4753 |
// GIR_Coverage, 358, |
4753 |
// GIR_Coverage, 358, |
| 4754 |
GIR_Done, |
4754 |
GIR_Done, |
| 4755 |
// Label 410: @9532 |
4755 |
// Label 410: @9532 |
| 4756 |
GIM_Try, /*On fail goto*//*Label 411*/ 9572, // Rule ID 359 // |
4756 |
GIM_Try, /*On fail goto*//*Label 411*/ 9572, // Rule ID 359 // |
| 4757 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4757 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4758 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl, |
4758 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl, |
| 4759 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
4759 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 4760 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
4760 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 4761 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4761 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4762 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
4762 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 4763 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5750:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
4763 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5750:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
| 4764 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL, |
4764 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL, |
| 4765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4766 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
4766 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 4767 |
GIR_EraseFromParent, /*InsnID*/0, |
4767 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4768 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4768 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4769 |
// GIR_Coverage, 359, |
4769 |
// GIR_Coverage, 359, |
| 4770 |
GIR_Done, |
4770 |
GIR_Done, |
| 4771 |
// Label 411: @9572 |
4771 |
// Label 411: @9572 |
| 4772 |
GIM_Try, /*On fail goto*//*Label 412*/ 9612, // Rule ID 360 // |
4772 |
GIM_Try, /*On fail goto*//*Label 412*/ 9612, // Rule ID 360 // |
| 4773 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4773 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4774 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr, |
4774 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr, |
| 4775 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
4775 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 4776 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
4776 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 4777 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4777 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
4778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 4779 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5752:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
4779 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5752:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
| 4780 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR, |
4780 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR, |
| 4781 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4781 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4782 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
4782 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 4783 |
GIR_EraseFromParent, /*InsnID*/0, |
4783 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4784 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4784 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4785 |
// GIR_Coverage, 360, |
4785 |
// GIR_Coverage, 360, |
| 4786 |
GIR_Done, |
4786 |
GIR_Done, |
| 4787 |
// Label 412: @9612 |
4787 |
// Label 412: @9612 |
| 4788 |
GIM_Try, /*On fail goto*//*Label 413*/ 9652, // Rule ID 361 // |
4788 |
GIM_Try, /*On fail goto*//*Label 413*/ 9652, // Rule ID 361 // |
| 4789 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4789 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4790 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla, |
4790 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla, |
| 4791 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
4791 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 4792 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
4792 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 4793 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4793 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4794 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
4794 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 4795 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5751:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
4795 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5751:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
| 4796 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA, |
4796 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA, |
| 4797 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4797 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4798 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
4798 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 4799 |
GIR_EraseFromParent, /*InsnID*/0, |
4799 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4800 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4800 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4801 |
// GIR_Coverage, 361, |
4801 |
// GIR_Coverage, 361, |
| 4802 |
GIR_Done, |
4802 |
GIR_Done, |
| 4803 |
// Label 413: @9652 |
4803 |
// Label 413: @9652 |
| 4804 |
GIM_Try, /*On fail goto*//*Label 414*/ 9692, // Rule ID 362 // |
4804 |
GIM_Try, /*On fail goto*//*Label 414*/ 9692, // Rule ID 362 // |
| 4805 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4805 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4806 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra, |
4806 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra, |
| 4807 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
4807 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 4808 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
4808 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 4809 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4809 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4810 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
4810 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 4811 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5753:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
4811 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5753:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
| 4812 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA, |
4812 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA, |
| 4813 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4813 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4814 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
4814 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 4815 |
GIR_EraseFromParent, /*InsnID*/0, |
4815 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4816 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4816 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4817 |
// GIR_Coverage, 362, |
4817 |
// GIR_Coverage, 362, |
| 4818 |
GIR_Done, |
4818 |
GIR_Done, |
| 4819 |
// Label 414: @9692 |
4819 |
// Label 414: @9692 |
| 4820 |
GIM_Try, /*On fail goto*//*Label 415*/ 9732, // Rule ID 363 // |
4820 |
GIM_Try, /*On fail goto*//*Label 415*/ 9732, // Rule ID 363 // |
| 4821 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4821 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4822 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl, |
4822 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl, |
| 4823 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
4823 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 4824 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
4824 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 4825 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4825 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4826 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
4826 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 4827 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5754:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
4827 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5754:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
| 4828 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL, |
4828 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL, |
| 4829 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4829 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4830 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
4830 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 4831 |
GIR_EraseFromParent, /*InsnID*/0, |
4831 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4832 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4832 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4833 |
// GIR_Coverage, 363, |
4833 |
// GIR_Coverage, 363, |
| 4834 |
GIR_Done, |
4834 |
GIR_Done, |
| 4835 |
// Label 415: @9732 |
4835 |
// Label 415: @9732 |
| 4836 |
GIM_Try, /*On fail goto*//*Label 416*/ 9772, // Rule ID 364 // |
4836 |
GIM_Try, /*On fail goto*//*Label 416*/ 9772, // Rule ID 364 // |
| 4837 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4837 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4838 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr, |
4838 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr, |
| 4839 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
4839 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 4840 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
4840 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 4841 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4841 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
4842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 4843 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5756:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
4843 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5756:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
| 4844 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR, |
4844 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR, |
| 4845 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4845 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4846 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
4846 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 4847 |
GIR_EraseFromParent, /*InsnID*/0, |
4847 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4848 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4848 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4849 |
// GIR_Coverage, 364, |
4849 |
// GIR_Coverage, 364, |
| 4850 |
GIR_Done, |
4850 |
GIR_Done, |
| 4851 |
// Label 416: @9772 |
4851 |
// Label 416: @9772 |
| 4852 |
GIM_Try, /*On fail goto*//*Label 417*/ 9812, // Rule ID 365 // |
4852 |
GIM_Try, /*On fail goto*//*Label 417*/ 9812, // Rule ID 365 // |
| 4853 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4853 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4854 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla, |
4854 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla, |
| 4855 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
4855 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 4856 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
4856 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 4857 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4857 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4858 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
4858 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 4859 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5755:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
4859 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5755:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
| 4860 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA, |
4860 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA, |
| 4861 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4861 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4862 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
4862 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 4863 |
GIR_EraseFromParent, /*InsnID*/0, |
4863 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4864 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4864 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4865 |
// GIR_Coverage, 365, |
4865 |
// GIR_Coverage, 365, |
| 4866 |
GIR_Done, |
4866 |
GIR_Done, |
| 4867 |
// Label 417: @9812 |
4867 |
// Label 417: @9812 |
| 4868 |
GIM_Try, /*On fail goto*//*Label 418*/ 9852, // Rule ID 366 // |
4868 |
GIM_Try, /*On fail goto*//*Label 418*/ 9852, // Rule ID 366 // |
| 4869 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4869 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4870 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra, |
4870 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra, |
| 4871 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
4871 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 4872 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
4872 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 4873 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4873 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4874 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
4874 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 4875 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5757:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
4875 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5757:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt) |
| 4876 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA, |
4876 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA, |
| 4877 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4877 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4878 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
4878 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 4879 |
GIR_EraseFromParent, /*InsnID*/0, |
4879 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4880 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4880 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4881 |
// GIR_Coverage, 366, |
4881 |
// GIR_Coverage, 366, |
| 4882 |
GIR_Done, |
4882 |
GIR_Done, |
| 4883 |
// Label 418: @9852 |
4883 |
// Label 418: @9852 |
| 4884 |
GIM_Try, /*On fail goto*//*Label 419*/ 9892, // Rule ID 414 // |
4884 |
GIM_Try, /*On fail goto*//*Label 419*/ 9892, // Rule ID 414 // |
| 4885 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4885 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4886 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev, |
4886 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev, |
| 4887 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
4887 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 4888 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
4888 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 4889 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
4889 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 4890 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
4890 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 4891 |
// (intrinsic_wo_chain:{ *:[i32] } 5322:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt) |
4891 |
// (intrinsic_wo_chain:{ *:[i32] } 5322:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt) |
| 4892 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV, |
4892 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV, |
| 4893 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4893 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4894 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
4894 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 4895 |
GIR_EraseFromParent, /*InsnID*/0, |
4895 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4896 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4896 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4897 |
// GIR_Coverage, 414, |
4897 |
// GIR_Coverage, 414, |
| 4898 |
GIR_Done, |
4898 |
GIR_Done, |
| 4899 |
// Label 419: @9892 |
4899 |
// Label 419: @9892 |
| 4900 |
GIM_Try, /*On fail goto*//*Label 420*/ 9932, // Rule ID 418 // |
4900 |
GIM_Try, /*On fail goto*//*Label 420*/ 9932, // Rule ID 418 // |
| 4901 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4901 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4902 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb, |
4902 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb, |
| 4903 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
4903 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 4904 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
4904 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 4905 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4905 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4906 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
4906 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 4907 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5769:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt) |
4907 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5769:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt) |
| 4908 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB, |
4908 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB, |
| 4909 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4909 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4910 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
4910 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 4911 |
GIR_EraseFromParent, /*InsnID*/0, |
4911 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4912 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4912 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4913 |
// GIR_Coverage, 418, |
4913 |
// GIR_Coverage, 418, |
| 4914 |
GIR_Done, |
4914 |
GIR_Done, |
| 4915 |
// Label 420: @9932 |
4915 |
// Label 420: @9932 |
| 4916 |
GIM_Try, /*On fail goto*//*Label 421*/ 9972, // Rule ID 419 // |
4916 |
GIM_Try, /*On fail goto*//*Label 421*/ 9972, // Rule ID 419 // |
| 4917 |
GIM_CheckFeatures, GIFBS_HasDSP, |
4917 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 4918 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph, |
4918 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph, |
| 4919 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
4919 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 4920 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
4920 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 4921 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
4921 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 4922 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
4922 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 4923 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5768:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt) |
4923 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5768:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt) |
| 4924 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH, |
4924 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH, |
| 4925 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
4925 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 4926 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
4926 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 4927 |
GIR_EraseFromParent, /*InsnID*/0, |
4927 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4928 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4928 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4929 |
// GIR_Coverage, 419, |
4929 |
// GIR_Coverage, 419, |
| 4930 |
GIR_Done, |
4930 |
GIR_Done, |
| 4931 |
// Label 421: @9972 |
4931 |
// Label 421: @9972 |
| 4932 |
GIM_Try, /*On fail goto*//*Label 422*/ 10012, // Rule ID 668 // |
4932 |
GIM_Try, /*On fail goto*//*Label 422*/ 10012, // Rule ID 668 // |
| 4933 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
4933 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 4934 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_w, |
4934 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_w, |
| 4935 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
4935 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4936 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
4936 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4937 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
4937 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 4938 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
4938 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 4939 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5474:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
4939 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5474:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
| 4940 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_W, |
4940 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_W, |
| 4941 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
4941 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 4942 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
4942 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 4943 |
GIR_EraseFromParent, /*InsnID*/0, |
4943 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4944 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4944 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4945 |
// GIR_Coverage, 668, |
4945 |
// GIR_Coverage, 668, |
| 4946 |
GIR_Done, |
4946 |
GIR_Done, |
| 4947 |
// Label 422: @10012 |
4947 |
// Label 422: @10012 |
| 4948 |
GIM_Try, /*On fail goto*//*Label 423*/ 10052, // Rule ID 669 // |
4948 |
GIM_Try, /*On fail goto*//*Label 423*/ 10052, // Rule ID 669 // |
| 4949 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
4949 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 4950 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_d, |
4950 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_d, |
| 4951 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
4951 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4952 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
4952 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4953 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
4953 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 4954 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
4954 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 4955 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5473:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
4955 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5473:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
| 4956 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_D, |
4956 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_D, |
| 4957 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
4957 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 4958 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
4958 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 4959 |
GIR_EraseFromParent, /*InsnID*/0, |
4959 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4960 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4960 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4961 |
// GIR_Coverage, 669, |
4961 |
// GIR_Coverage, 669, |
| 4962 |
GIR_Done, |
4962 |
GIR_Done, |
| 4963 |
// Label 423: @10052 |
4963 |
// Label 423: @10052 |
| 4964 |
GIM_Try, /*On fail goto*//*Label 424*/ 10092, // Rule ID 692 // |
4964 |
GIM_Try, /*On fail goto*//*Label 424*/ 10092, // Rule ID 692 // |
| 4965 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
4965 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 4966 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_w, |
4966 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_w, |
| 4967 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
4967 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 4968 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
4968 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 4969 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
4969 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 4970 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
4970 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 4971 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5500:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws) |
4971 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5500:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws) |
| 4972 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_W, |
4972 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_W, |
| 4973 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
4973 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 4974 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
4974 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 4975 |
GIR_EraseFromParent, /*InsnID*/0, |
4975 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4976 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4976 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4977 |
// GIR_Coverage, 692, |
4977 |
// GIR_Coverage, 692, |
| 4978 |
GIR_Done, |
4978 |
GIR_Done, |
| 4979 |
// Label 424: @10092 |
4979 |
// Label 424: @10092 |
| 4980 |
GIM_Try, /*On fail goto*//*Label 425*/ 10132, // Rule ID 693 // |
4980 |
GIM_Try, /*On fail goto*//*Label 425*/ 10132, // Rule ID 693 // |
| 4981 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
4981 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 4982 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_d, |
4982 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_d, |
| 4983 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
4983 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 4984 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
4984 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4985 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
4985 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 4986 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
4986 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 4987 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5499:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
4987 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5499:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
| 4988 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_D, |
4988 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_D, |
| 4989 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
4989 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 4990 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
4990 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 4991 |
GIR_EraseFromParent, /*InsnID*/0, |
4991 |
GIR_EraseFromParent, /*InsnID*/0, |
| 4992 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
4992 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 4993 |
// GIR_Coverage, 693, |
4993 |
// GIR_Coverage, 693, |
| 4994 |
GIR_Done, |
4994 |
GIR_Done, |
| 4995 |
// Label 425: @10132 |
4995 |
// Label 425: @10132 |
| 4996 |
GIM_Try, /*On fail goto*//*Label 426*/ 10172, // Rule ID 694 // |
4996 |
GIM_Try, /*On fail goto*//*Label 426*/ 10172, // Rule ID 694 // |
| 4997 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
4997 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 4998 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_w, |
4998 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_w, |
| 4999 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
4999 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5000 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
5000 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5001 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
5001 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 5002 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
5002 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 5003 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5502:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws) |
5003 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5502:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws) |
| 5004 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_W, |
5004 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_W, |
| 5005 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5005 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5006 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5006 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5007 |
GIR_EraseFromParent, /*InsnID*/0, |
5007 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5008 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5008 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5009 |
// GIR_Coverage, 694, |
5009 |
// GIR_Coverage, 694, |
| 5010 |
GIR_Done, |
5010 |
GIR_Done, |
| 5011 |
// Label 426: @10172 |
5011 |
// Label 426: @10172 |
| 5012 |
GIM_Try, /*On fail goto*//*Label 427*/ 10212, // Rule ID 695 // |
5012 |
GIM_Try, /*On fail goto*//*Label 427*/ 10212, // Rule ID 695 // |
| 5013 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5013 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5014 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_d, |
5014 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_d, |
| 5015 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
5015 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5016 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
5016 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5017 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
5017 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 5018 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
5018 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 5019 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5501:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
5019 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5501:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
| 5020 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_D, |
5020 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_D, |
| 5021 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5021 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5022 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5022 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5023 |
GIR_EraseFromParent, /*InsnID*/0, |
5023 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5024 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5024 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5025 |
// GIR_Coverage, 695, |
5025 |
// GIR_Coverage, 695, |
| 5026 |
GIR_Done, |
5026 |
GIR_Done, |
| 5027 |
// Label 427: @10212 |
5027 |
// Label 427: @10212 |
| 5028 |
GIM_Try, /*On fail goto*//*Label 428*/ 10252, // Rule ID 700 // |
5028 |
GIM_Try, /*On fail goto*//*Label 428*/ 10252, // Rule ID 700 // |
| 5029 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5029 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5030 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_w, |
5030 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_w, |
| 5031 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
5031 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5032 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
5032 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5033 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
5033 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 5034 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
5034 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 5035 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5508:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws) |
5035 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5508:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws) |
| 5036 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_W, |
5036 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_W, |
| 5037 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5037 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5038 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5038 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5039 |
GIR_EraseFromParent, /*InsnID*/0, |
5039 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5040 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5040 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5041 |
// GIR_Coverage, 700, |
5041 |
// GIR_Coverage, 700, |
| 5042 |
GIR_Done, |
5042 |
GIR_Done, |
| 5043 |
// Label 428: @10252 |
5043 |
// Label 428: @10252 |
| 5044 |
GIM_Try, /*On fail goto*//*Label 429*/ 10292, // Rule ID 701 // |
5044 |
GIM_Try, /*On fail goto*//*Label 429*/ 10292, // Rule ID 701 // |
| 5045 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5045 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5046 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_d, |
5046 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_d, |
| 5047 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
5047 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5048 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
5048 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5049 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
5049 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 5050 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
5050 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 5051 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5507:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
5051 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5507:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
| 5052 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_D, |
5052 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_D, |
| 5053 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5053 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5054 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5054 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5055 |
GIR_EraseFromParent, /*InsnID*/0, |
5055 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5056 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5056 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5057 |
// GIR_Coverage, 701, |
5057 |
// GIR_Coverage, 701, |
| 5058 |
GIR_Done, |
5058 |
GIR_Done, |
| 5059 |
// Label 429: @10292 |
5059 |
// Label 429: @10292 |
| 5060 |
GIM_Try, /*On fail goto*//*Label 430*/ 10332, // Rule ID 702 // |
5060 |
GIM_Try, /*On fail goto*//*Label 430*/ 10332, // Rule ID 702 // |
| 5061 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5061 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5062 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_w, |
5062 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_w, |
| 5063 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
5063 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5064 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
5064 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5065 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
5065 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 5066 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
5066 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 5067 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5510:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws) |
5067 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5510:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws) |
| 5068 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_W, |
5068 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_W, |
| 5069 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5069 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5070 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5070 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5071 |
GIR_EraseFromParent, /*InsnID*/0, |
5071 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5072 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5072 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5073 |
// GIR_Coverage, 702, |
5073 |
// GIR_Coverage, 702, |
| 5074 |
GIR_Done, |
5074 |
GIR_Done, |
| 5075 |
// Label 430: @10332 |
5075 |
// Label 430: @10332 |
| 5076 |
GIM_Try, /*On fail goto*//*Label 431*/ 10372, // Rule ID 703 // |
5076 |
GIM_Try, /*On fail goto*//*Label 431*/ 10372, // Rule ID 703 // |
| 5077 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5077 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5078 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_d, |
5078 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_d, |
| 5079 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
5079 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5080 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
5080 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5081 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
5081 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 5082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
5082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 5083 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5509:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
5083 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5509:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
| 5084 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_D, |
5084 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_D, |
| 5085 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5085 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5087 |
GIR_EraseFromParent, /*InsnID*/0, |
5087 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5088 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5088 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5089 |
// GIR_Coverage, 703, |
5089 |
// GIR_Coverage, 703, |
| 5090 |
GIR_Done, |
5090 |
GIR_Done, |
| 5091 |
// Label 431: @10372 |
5091 |
// Label 431: @10372 |
| 5092 |
GIM_Try, /*On fail goto*//*Label 432*/ 10412, // Rule ID 728 // |
5092 |
GIM_Try, /*On fail goto*//*Label 432*/ 10412, // Rule ID 728 // |
| 5093 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5093 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5094 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_w, |
5094 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_w, |
| 5095 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
5095 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5096 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
5096 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5097 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
5097 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 5098 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
5098 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 5099 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5532:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
5099 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5532:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
| 5100 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_W, |
5100 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_W, |
| 5101 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5101 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5102 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5102 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5103 |
GIR_EraseFromParent, /*InsnID*/0, |
5103 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5104 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5104 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5105 |
// GIR_Coverage, 728, |
5105 |
// GIR_Coverage, 728, |
| 5106 |
GIR_Done, |
5106 |
GIR_Done, |
| 5107 |
// Label 432: @10412 |
5107 |
// Label 432: @10412 |
| 5108 |
GIM_Try, /*On fail goto*//*Label 433*/ 10452, // Rule ID 729 // |
5108 |
GIM_Try, /*On fail goto*//*Label 433*/ 10452, // Rule ID 729 // |
| 5109 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5109 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5110 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_d, |
5110 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_d, |
| 5111 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
5111 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5112 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
5112 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5113 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
5113 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 5114 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
5114 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 5115 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5531:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
5115 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5531:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
| 5116 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_D, |
5116 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_D, |
| 5117 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5117 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5118 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5118 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5119 |
GIR_EraseFromParent, /*InsnID*/0, |
5119 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5120 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5120 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5121 |
// GIR_Coverage, 729, |
5121 |
// GIR_Coverage, 729, |
| 5122 |
GIR_Done, |
5122 |
GIR_Done, |
| 5123 |
// Label 433: @10452 |
5123 |
// Label 433: @10452 |
| 5124 |
GIM_Try, /*On fail goto*//*Label 434*/ 10492, // Rule ID 730 // |
5124 |
GIM_Try, /*On fail goto*//*Label 434*/ 10492, // Rule ID 730 // |
| 5125 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5125 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5126 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_w, |
5126 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_w, |
| 5127 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
5127 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5128 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
5128 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5129 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
5129 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 5130 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
5130 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 5131 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5536:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
5131 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5536:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
| 5132 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_W, |
5132 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_W, |
| 5133 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5133 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5134 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5134 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5135 |
GIR_EraseFromParent, /*InsnID*/0, |
5135 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5136 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5136 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5137 |
// GIR_Coverage, 730, |
5137 |
// GIR_Coverage, 730, |
| 5138 |
GIR_Done, |
5138 |
GIR_Done, |
| 5139 |
// Label 434: @10492 |
5139 |
// Label 434: @10492 |
| 5140 |
GIM_Try, /*On fail goto*//*Label 435*/ 10532, // Rule ID 731 // |
5140 |
GIM_Try, /*On fail goto*//*Label 435*/ 10532, // Rule ID 731 // |
| 5141 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5141 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5142 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_d, |
5142 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_d, |
| 5143 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
5143 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5144 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
5144 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5145 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
5145 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 5146 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
5146 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 5147 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5535:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
5147 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5535:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
| 5148 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_D, |
5148 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_D, |
| 5149 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5149 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5150 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5150 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5151 |
GIR_EraseFromParent, /*InsnID*/0, |
5151 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5152 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5152 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5153 |
// GIR_Coverage, 731, |
5153 |
// GIR_Coverage, 731, |
| 5154 |
GIR_Done, |
5154 |
GIR_Done, |
| 5155 |
// Label 435: @10532 |
5155 |
// Label 435: @10532 |
| 5156 |
GIM_Try, /*On fail goto*//*Label 436*/ 10572, // Rule ID 758 // |
5156 |
GIM_Try, /*On fail goto*//*Label 436*/ 10572, // Rule ID 758 // |
| 5157 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5157 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5158 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_w, |
5158 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_w, |
| 5159 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
5159 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5160 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
5160 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5161 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
5161 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 5162 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
5162 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 5163 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5564:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
5163 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5564:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
| 5164 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_W, |
5164 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_W, |
| 5165 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5165 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5166 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5166 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5167 |
GIR_EraseFromParent, /*InsnID*/0, |
5167 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5168 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5168 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5169 |
// GIR_Coverage, 758, |
5169 |
// GIR_Coverage, 758, |
| 5170 |
GIR_Done, |
5170 |
GIR_Done, |
| 5171 |
// Label 436: @10572 |
5171 |
// Label 436: @10572 |
| 5172 |
GIM_Try, /*On fail goto*//*Label 437*/ 10612, // Rule ID 759 // |
5172 |
GIM_Try, /*On fail goto*//*Label 437*/ 10612, // Rule ID 759 // |
| 5173 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5173 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5174 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_d, |
5174 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_d, |
| 5175 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
5175 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5176 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
5176 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5177 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
5177 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 5178 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
5178 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 5179 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5563:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
5179 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5563:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
| 5180 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_D, |
5180 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_D, |
| 5181 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5181 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5182 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5182 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5183 |
GIR_EraseFromParent, /*InsnID*/0, |
5183 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5184 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5184 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5185 |
// GIR_Coverage, 759, |
5185 |
// GIR_Coverage, 759, |
| 5186 |
GIR_Done, |
5186 |
GIR_Done, |
| 5187 |
// Label 437: @10612 |
5187 |
// Label 437: @10612 |
| 5188 |
GIM_Try, /*On fail goto*//*Label 438*/ 10652, // Rule ID 760 // |
5188 |
GIM_Try, /*On fail goto*//*Label 438*/ 10652, // Rule ID 760 // |
| 5189 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5189 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5190 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_w, |
5190 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_w, |
| 5191 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
5191 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5192 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
5192 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5193 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
5193 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 5194 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
5194 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 5195 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5566:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
5195 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5566:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
| 5196 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_W, |
5196 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_W, |
| 5197 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5197 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5198 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5198 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5199 |
GIR_EraseFromParent, /*InsnID*/0, |
5199 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5200 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5200 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5201 |
// GIR_Coverage, 760, |
5201 |
// GIR_Coverage, 760, |
| 5202 |
GIR_Done, |
5202 |
GIR_Done, |
| 5203 |
// Label 438: @10652 |
5203 |
// Label 438: @10652 |
| 5204 |
GIM_Try, /*On fail goto*//*Label 439*/ 10692, // Rule ID 761 // |
5204 |
GIM_Try, /*On fail goto*//*Label 439*/ 10692, // Rule ID 761 // |
| 5205 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5205 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5206 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_d, |
5206 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_d, |
| 5207 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
5207 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5208 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
5208 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5209 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
5209 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 5210 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
5210 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 5211 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5565:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
5211 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5565:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
| 5212 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_D, |
5212 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_D, |
| 5213 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5213 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5214 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5214 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5215 |
GIR_EraseFromParent, /*InsnID*/0, |
5215 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5216 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5216 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5217 |
// GIR_Coverage, 761, |
5217 |
// GIR_Coverage, 761, |
| 5218 |
GIR_Done, |
5218 |
GIR_Done, |
| 5219 |
// Label 439: @10692 |
5219 |
// Label 439: @10692 |
| 5220 |
GIM_Try, /*On fail goto*//*Label 440*/ 10732, // Rule ID 896 // |
5220 |
GIM_Try, /*On fail goto*//*Label 440*/ 10732, // Rule ID 896 // |
| 5221 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5221 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5222 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_b, |
5222 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_b, |
| 5223 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
5223 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 5224 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
5224 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5225 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
5225 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 5226 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
5226 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 5227 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5721:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) |
5227 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5721:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) |
| 5228 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_B, |
5228 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_B, |
| 5229 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5229 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5230 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5230 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5231 |
GIR_EraseFromParent, /*InsnID*/0, |
5231 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5232 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5232 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5233 |
// GIR_Coverage, 896, |
5233 |
// GIR_Coverage, 896, |
| 5234 |
GIR_Done, |
5234 |
GIR_Done, |
| 5235 |
// Label 440: @10732 |
5235 |
// Label 440: @10732 |
| 5236 |
GIM_Try, /*On fail goto*//*Label 441*/ 10772, // Rule ID 897 // |
5236 |
GIM_Try, /*On fail goto*//*Label 441*/ 10772, // Rule ID 897 // |
| 5237 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5237 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5238 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_h, |
5238 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_h, |
| 5239 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
5239 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 5240 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
5240 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5241 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
5241 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 5242 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
5242 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 5243 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5723:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) |
5243 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5723:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) |
| 5244 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_H, |
5244 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_H, |
| 5245 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5245 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5246 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5246 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5247 |
GIR_EraseFromParent, /*InsnID*/0, |
5247 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5248 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5248 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5249 |
// GIR_Coverage, 897, |
5249 |
// GIR_Coverage, 897, |
| 5250 |
GIR_Done, |
5250 |
GIR_Done, |
| 5251 |
// Label 441: @10772 |
5251 |
// Label 441: @10772 |
| 5252 |
GIM_Try, /*On fail goto*//*Label 442*/ 10812, // Rule ID 898 // |
5252 |
GIM_Try, /*On fail goto*//*Label 442*/ 10812, // Rule ID 898 // |
| 5253 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5253 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5254 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_w, |
5254 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_w, |
| 5255 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
5255 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5256 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
5256 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5257 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
5257 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 5258 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
5258 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 5259 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5724:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
5259 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5724:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
| 5260 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_W, |
5260 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_W, |
| 5261 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5261 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5262 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5262 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5263 |
GIR_EraseFromParent, /*InsnID*/0, |
5263 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5264 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5264 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5265 |
// GIR_Coverage, 898, |
5265 |
// GIR_Coverage, 898, |
| 5266 |
GIR_Done, |
5266 |
GIR_Done, |
| 5267 |
// Label 442: @10812 |
5267 |
// Label 442: @10812 |
| 5268 |
GIM_Try, /*On fail goto*//*Label 443*/ 10852, // Rule ID 899 // |
5268 |
GIM_Try, /*On fail goto*//*Label 443*/ 10852, // Rule ID 899 // |
| 5269 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5269 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5270 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_d, |
5270 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_d, |
| 5271 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
5271 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5272 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
5272 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5273 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
5273 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 5274 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
5274 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 5275 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5722:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) |
5275 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5722:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) |
| 5276 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_D, |
5276 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_D, |
| 5277 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5277 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5278 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5278 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5279 |
GIR_EraseFromParent, /*InsnID*/0, |
5279 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5280 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5280 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5281 |
// GIR_Coverage, 899, |
5281 |
// GIR_Coverage, 899, |
| 5282 |
GIR_Done, |
5282 |
GIR_Done, |
| 5283 |
// Label 443: @10852 |
5283 |
// Label 443: @10852 |
| 5284 |
GIM_Try, /*On fail goto*//*Label 444*/ 10892, // Rule ID 1239 // |
5284 |
GIM_Try, /*On fail goto*//*Label 444*/ 10892, // Rule ID 1239 // |
| 5285 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5285 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5286 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl, |
5286 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl, |
| 5287 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
5287 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 5288 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
5288 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 5289 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
5289 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 5290 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5290 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5291 |
// (intrinsic_wo_chain:{ *:[i32] } 5748:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs) |
5291 |
// (intrinsic_wo_chain:{ *:[i32] } 5748:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs) |
| 5292 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL_MM, |
5292 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL_MM, |
| 5293 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5293 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5294 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5294 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5295 |
GIR_EraseFromParent, /*InsnID*/0, |
5295 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5296 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5296 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5297 |
// GIR_Coverage, 1239, |
5297 |
// GIR_Coverage, 1239, |
| 5298 |
GIR_Done, |
5298 |
GIR_Done, |
| 5299 |
// Label 444: @10892 |
5299 |
// Label 444: @10892 |
| 5300 |
GIM_Try, /*On fail goto*//*Label 445*/ 10932, // Rule ID 1240 // |
5300 |
GIM_Try, /*On fail goto*//*Label 445*/ 10932, // Rule ID 1240 // |
| 5301 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5301 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5302 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr, |
5302 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr, |
| 5303 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
5303 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 5304 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
5304 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 5305 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
5305 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 5306 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5306 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5307 |
// (intrinsic_wo_chain:{ *:[i32] } 5749:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs) |
5307 |
// (intrinsic_wo_chain:{ *:[i32] } 5749:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs) |
| 5308 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR_MM, |
5308 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR_MM, |
| 5309 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5309 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5310 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5310 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5311 |
GIR_EraseFromParent, /*InsnID*/0, |
5311 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5312 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5312 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5313 |
// GIR_Coverage, 1240, |
5313 |
// GIR_Coverage, 1240, |
| 5314 |
GIR_Done, |
5314 |
GIR_Done, |
| 5315 |
// Label 445: @10932 |
5315 |
// Label 445: @10932 |
| 5316 |
GIM_Try, /*On fail goto*//*Label 446*/ 10972, // Rule ID 1241 // |
5316 |
GIM_Try, /*On fail goto*//*Label 446*/ 10972, // Rule ID 1241 // |
| 5317 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5317 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5318 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl, |
5318 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl, |
| 5319 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
5319 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 5320 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
5320 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 5321 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5321 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5322 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5322 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5323 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5750:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
5323 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5750:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
| 5324 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL_MM, |
5324 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL_MM, |
| 5325 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5325 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5326 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5326 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5327 |
GIR_EraseFromParent, /*InsnID*/0, |
5327 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5329 |
// GIR_Coverage, 1241, |
5329 |
// GIR_Coverage, 1241, |
| 5330 |
GIR_Done, |
5330 |
GIR_Done, |
| 5331 |
// Label 446: @10972 |
5331 |
// Label 446: @10972 |
| 5332 |
GIM_Try, /*On fail goto*//*Label 447*/ 11012, // Rule ID 1242 // |
5332 |
GIM_Try, /*On fail goto*//*Label 447*/ 11012, // Rule ID 1242 // |
| 5333 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5333 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5334 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla, |
5334 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla, |
| 5335 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
5335 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 5336 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
5336 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 5337 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5337 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5338 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5338 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5339 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5751:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
5339 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5751:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
| 5340 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA_MM, |
5340 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA_MM, |
| 5341 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5341 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5342 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5342 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5343 |
GIR_EraseFromParent, /*InsnID*/0, |
5343 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5344 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5344 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5345 |
// GIR_Coverage, 1242, |
5345 |
// GIR_Coverage, 1242, |
| 5346 |
GIR_Done, |
5346 |
GIR_Done, |
| 5347 |
// Label 447: @11012 |
5347 |
// Label 447: @11012 |
| 5348 |
GIM_Try, /*On fail goto*//*Label 448*/ 11052, // Rule ID 1243 // |
5348 |
GIM_Try, /*On fail goto*//*Label 448*/ 11052, // Rule ID 1243 // |
| 5349 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5349 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5350 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr, |
5350 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr, |
| 5351 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
5351 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 5352 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
5352 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 5353 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5353 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5354 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5354 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5355 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5752:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
5355 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5752:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
| 5356 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR_MM, |
5356 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR_MM, |
| 5357 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5357 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5358 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5358 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5359 |
GIR_EraseFromParent, /*InsnID*/0, |
5359 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5360 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5360 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5361 |
// GIR_Coverage, 1243, |
5361 |
// GIR_Coverage, 1243, |
| 5362 |
GIR_Done, |
5362 |
GIR_Done, |
| 5363 |
// Label 448: @11052 |
5363 |
// Label 448: @11052 |
| 5364 |
GIM_Try, /*On fail goto*//*Label 449*/ 11092, // Rule ID 1244 // |
5364 |
GIM_Try, /*On fail goto*//*Label 449*/ 11092, // Rule ID 1244 // |
| 5365 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5365 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5366 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra, |
5366 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra, |
| 5367 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
5367 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 5368 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
5368 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 5369 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5369 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5370 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5370 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5371 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5753:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
5371 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5753:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
| 5372 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA_MM, |
5372 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA_MM, |
| 5373 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5373 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5374 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5374 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5375 |
GIR_EraseFromParent, /*InsnID*/0, |
5375 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5376 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5376 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5377 |
// GIR_Coverage, 1244, |
5377 |
// GIR_Coverage, 1244, |
| 5378 |
GIR_Done, |
5378 |
GIR_Done, |
| 5379 |
// Label 449: @11092 |
5379 |
// Label 449: @11092 |
| 5380 |
GIM_Try, /*On fail goto*//*Label 450*/ 11132, // Rule ID 1245 // |
5380 |
GIM_Try, /*On fail goto*//*Label 450*/ 11132, // Rule ID 1245 // |
| 5381 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5381 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5382 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl, |
5382 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl, |
| 5383 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
5383 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 5384 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
5384 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 5385 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5385 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5386 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5386 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5387 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5754:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
5387 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5754:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
| 5388 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL_MM, |
5388 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL_MM, |
| 5389 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5389 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5390 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5390 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5391 |
GIR_EraseFromParent, /*InsnID*/0, |
5391 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5392 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5392 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5393 |
// GIR_Coverage, 1245, |
5393 |
// GIR_Coverage, 1245, |
| 5394 |
GIR_Done, |
5394 |
GIR_Done, |
| 5395 |
// Label 450: @11132 |
5395 |
// Label 450: @11132 |
| 5396 |
GIM_Try, /*On fail goto*//*Label 451*/ 11172, // Rule ID 1246 // |
5396 |
GIM_Try, /*On fail goto*//*Label 451*/ 11172, // Rule ID 1246 // |
| 5397 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5397 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5398 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla, |
5398 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla, |
| 5399 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
5399 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 5400 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
5400 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 5401 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5401 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5402 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5402 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5403 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5755:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
5403 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5755:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
| 5404 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA_MM, |
5404 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA_MM, |
| 5405 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5405 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5406 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5406 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5407 |
GIR_EraseFromParent, /*InsnID*/0, |
5407 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5408 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5408 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5409 |
// GIR_Coverage, 1246, |
5409 |
// GIR_Coverage, 1246, |
| 5410 |
GIR_Done, |
5410 |
GIR_Done, |
| 5411 |
// Label 451: @11172 |
5411 |
// Label 451: @11172 |
| 5412 |
GIM_Try, /*On fail goto*//*Label 452*/ 11212, // Rule ID 1247 // |
5412 |
GIM_Try, /*On fail goto*//*Label 452*/ 11212, // Rule ID 1247 // |
| 5413 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5413 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5414 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr, |
5414 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr, |
| 5415 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
5415 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 5416 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
5416 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 5417 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5417 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5418 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5418 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5419 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5756:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
5419 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5756:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
| 5420 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR_MM, |
5420 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR_MM, |
| 5421 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5421 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5422 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5422 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5423 |
GIR_EraseFromParent, /*InsnID*/0, |
5423 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5424 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5424 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5425 |
// GIR_Coverage, 1247, |
5425 |
// GIR_Coverage, 1247, |
| 5426 |
GIR_Done, |
5426 |
GIR_Done, |
| 5427 |
// Label 452: @11212 |
5427 |
// Label 452: @11212 |
| 5428 |
GIM_Try, /*On fail goto*//*Label 453*/ 11252, // Rule ID 1248 // |
5428 |
GIM_Try, /*On fail goto*//*Label 453*/ 11252, // Rule ID 1248 // |
| 5429 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5429 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5430 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra, |
5430 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra, |
| 5431 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
5431 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 5432 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
5432 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 5433 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5433 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5434 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5434 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5435 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5757:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
5435 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5757:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs) |
| 5436 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA_MM, |
5436 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA_MM, |
| 5437 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5437 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5438 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5438 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5439 |
GIR_EraseFromParent, /*InsnID*/0, |
5439 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5440 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5440 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5441 |
// GIR_Coverage, 1248, |
5441 |
// GIR_Coverage, 1248, |
| 5442 |
GIR_Done, |
5442 |
GIR_Done, |
| 5443 |
// Label 453: @11252 |
5443 |
// Label 453: @11252 |
| 5444 |
GIM_Try, /*On fail goto*//*Label 454*/ 11292, // Rule ID 1274 // |
5444 |
GIM_Try, /*On fail goto*//*Label 454*/ 11292, // Rule ID 1274 // |
| 5445 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5445 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5446 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb, |
5446 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb, |
| 5447 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
5447 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 5448 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
5448 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 5449 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
5449 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 5450 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5450 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5451 |
// (intrinsic_wo_chain:{ *:[i32] } 5766:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs) |
5451 |
// (intrinsic_wo_chain:{ *:[i32] } 5766:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs) |
| 5452 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB_MM, |
5452 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB_MM, |
| 5453 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5453 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5454 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5454 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5455 |
GIR_EraseFromParent, /*InsnID*/0, |
5455 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5456 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5456 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5457 |
// GIR_Coverage, 1274, |
5457 |
// GIR_Coverage, 1274, |
| 5458 |
GIR_Done, |
5458 |
GIR_Done, |
| 5459 |
// Label 454: @11292 |
5459 |
// Label 454: @11292 |
| 5460 |
GIM_Try, /*On fail goto*//*Label 455*/ 11332, // Rule ID 1278 // |
5460 |
GIM_Try, /*On fail goto*//*Label 455*/ 11332, // Rule ID 1278 // |
| 5461 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5461 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5462 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph, |
5462 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph, |
| 5463 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
5463 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 5464 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
5464 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 5465 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5465 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5466 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
5466 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 5467 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5768:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs) |
5467 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5768:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs) |
| 5468 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH_MM, |
5468 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH_MM, |
| 5469 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5469 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5470 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5470 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5471 |
GIR_EraseFromParent, /*InsnID*/0, |
5471 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5472 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5472 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5473 |
// GIR_Coverage, 1278, |
5473 |
// GIR_Coverage, 1278, |
| 5474 |
GIR_Done, |
5474 |
GIR_Done, |
| 5475 |
// Label 455: @11332 |
5475 |
// Label 455: @11332 |
| 5476 |
GIM_Try, /*On fail goto*//*Label 456*/ 11372, // Rule ID 1279 // |
5476 |
GIM_Try, /*On fail goto*//*Label 456*/ 11372, // Rule ID 1279 // |
| 5477 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5477 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5478 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb, |
5478 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb, |
| 5479 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
5479 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 5480 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
5480 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 5481 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5481 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5482 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
5482 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 5483 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5769:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs) |
5483 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5769:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs) |
| 5484 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB_MM, |
5484 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB_MM, |
| 5485 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5485 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5486 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5486 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5487 |
GIR_EraseFromParent, /*InsnID*/0, |
5487 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5488 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5488 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5489 |
// GIR_Coverage, 1279, |
5489 |
// GIR_Coverage, 1279, |
| 5490 |
GIR_Done, |
5490 |
GIR_Done, |
| 5491 |
// Label 456: @11372 |
5491 |
// Label 456: @11372 |
| 5492 |
GIM_Try, /*On fail goto*//*Label 457*/ 11412, // Rule ID 1289 // |
5492 |
GIM_Try, /*On fail goto*//*Label 457*/ 11412, // Rule ID 1289 // |
| 5493 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5493 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5494 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev, |
5494 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev, |
| 5495 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
5495 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 5496 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
5496 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 5497 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
5497 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 5498 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
5498 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 5499 |
// (intrinsic_wo_chain:{ *:[i32] } 5322:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
5499 |
// (intrinsic_wo_chain:{ *:[i32] } 5322:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
| 5500 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV_MM, |
5500 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV_MM, |
| 5501 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5501 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5502 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5502 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5503 |
GIR_EraseFromParent, /*InsnID*/0, |
5503 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5504 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5504 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5505 |
// GIR_Coverage, 1289, |
5505 |
// GIR_Coverage, 1289, |
| 5506 |
GIR_Done, |
5506 |
GIR_Done, |
| 5507 |
// Label 457: @11412 |
5507 |
// Label 457: @11412 |
| 5508 |
GIM_Reject, |
5508 |
GIM_Reject, |
| 5509 |
// Label 403: @11413 |
5509 |
// Label 403: @11413 |
| 5510 |
GIM_Try, /*On fail goto*//*Label 458*/ 22553, |
5510 |
GIM_Try, /*On fail goto*//*Label 458*/ 22553, |
| 5511 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
5511 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 5512 |
GIM_Try, /*On fail goto*//*Label 459*/ 11469, // Rule ID 926 // |
5512 |
GIM_Try, /*On fail goto*//*Label 459*/ 11469, // Rule ID 926 // |
| 5513 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5513 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5514 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_b, |
5514 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_b, |
| 5515 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
5515 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 5516 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
5516 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5517 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
5517 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 5518 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
5518 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 5519 |
// MIs[0] m |
5519 |
// MIs[0] m |
| 5520 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5520 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5521 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt3, |
5521 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt3, |
| 5522 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5770:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m) |
5522 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5770:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m) |
| 5523 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_B, |
5523 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_B, |
| 5524 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5524 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5525 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5525 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5526 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5526 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5527 |
GIR_EraseFromParent, /*InsnID*/0, |
5527 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5528 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5528 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5529 |
// GIR_Coverage, 926, |
5529 |
// GIR_Coverage, 926, |
| 5530 |
GIR_Done, |
5530 |
GIR_Done, |
| 5531 |
// Label 459: @11469 |
5531 |
// Label 459: @11469 |
| 5532 |
GIM_Try, /*On fail goto*//*Label 460*/ 11520, // Rule ID 927 // |
5532 |
GIM_Try, /*On fail goto*//*Label 460*/ 11520, // Rule ID 927 // |
| 5533 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5533 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5534 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_h, |
5534 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_h, |
| 5535 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
5535 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 5536 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
5536 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5537 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
5537 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 5538 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
5538 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 5539 |
// MIs[0] m |
5539 |
// MIs[0] m |
| 5540 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5540 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5541 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt4, |
5541 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt4, |
| 5542 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5772:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m) |
5542 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5772:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m) |
| 5543 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_H, |
5543 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_H, |
| 5544 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5544 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5545 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5545 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5546 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5546 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5547 |
GIR_EraseFromParent, /*InsnID*/0, |
5547 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5548 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5548 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5549 |
// GIR_Coverage, 927, |
5549 |
// GIR_Coverage, 927, |
| 5550 |
GIR_Done, |
5550 |
GIR_Done, |
| 5551 |
// Label 460: @11520 |
5551 |
// Label 460: @11520 |
| 5552 |
GIM_Try, /*On fail goto*//*Label 461*/ 11571, // Rule ID 928 // |
5552 |
GIM_Try, /*On fail goto*//*Label 461*/ 11571, // Rule ID 928 // |
| 5553 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5553 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5554 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_w, |
5554 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_w, |
| 5555 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
5555 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5556 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
5556 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5557 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
5557 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 5558 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
5558 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 5559 |
// MIs[0] m |
5559 |
// MIs[0] m |
| 5560 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5560 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5561 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
5561 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
| 5562 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5773:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m) |
5562 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5773:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m) |
| 5563 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_W, |
5563 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_W, |
| 5564 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5564 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5565 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5565 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5566 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5566 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5567 |
GIR_EraseFromParent, /*InsnID*/0, |
5567 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5568 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5568 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5569 |
// GIR_Coverage, 928, |
5569 |
// GIR_Coverage, 928, |
| 5570 |
GIR_Done, |
5570 |
GIR_Done, |
| 5571 |
// Label 461: @11571 |
5571 |
// Label 461: @11571 |
| 5572 |
GIM_Try, /*On fail goto*//*Label 462*/ 11622, // Rule ID 929 // |
5572 |
GIM_Try, /*On fail goto*//*Label 462*/ 11622, // Rule ID 929 // |
| 5573 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5573 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5574 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_d, |
5574 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_d, |
| 5575 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
5575 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5576 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
5576 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5577 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
5577 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 5578 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
5578 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 5579 |
// MIs[0] m |
5579 |
// MIs[0] m |
| 5580 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5580 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5581 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt6, |
5581 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt6, |
| 5582 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5771:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m) |
5582 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5771:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m) |
| 5583 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_D, |
5583 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_D, |
| 5584 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5584 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5585 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5585 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5586 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5586 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5587 |
GIR_EraseFromParent, /*InsnID*/0, |
5587 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5588 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5588 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5589 |
// GIR_Coverage, 929, |
5589 |
// GIR_Coverage, 929, |
| 5590 |
GIR_Done, |
5590 |
GIR_Done, |
| 5591 |
// Label 462: @11622 |
5591 |
// Label 462: @11622 |
| 5592 |
GIM_Try, /*On fail goto*//*Label 463*/ 11673, // Rule ID 930 // |
5592 |
GIM_Try, /*On fail goto*//*Label 463*/ 11673, // Rule ID 930 // |
| 5593 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5593 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5594 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_b, |
5594 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_b, |
| 5595 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
5595 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 5596 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
5596 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5597 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
5597 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 5598 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
5598 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 5599 |
// MIs[0] m |
5599 |
// MIs[0] m |
| 5600 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5600 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5601 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt3, |
5601 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt3, |
| 5602 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5774:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m) |
5602 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5774:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m) |
| 5603 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_B, |
5603 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_B, |
| 5604 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5604 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5605 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5605 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5606 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5606 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5607 |
GIR_EraseFromParent, /*InsnID*/0, |
5607 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5608 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5608 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5609 |
// GIR_Coverage, 930, |
5609 |
// GIR_Coverage, 930, |
| 5610 |
GIR_Done, |
5610 |
GIR_Done, |
| 5611 |
// Label 463: @11673 |
5611 |
// Label 463: @11673 |
| 5612 |
GIM_Try, /*On fail goto*//*Label 464*/ 11724, // Rule ID 931 // |
5612 |
GIM_Try, /*On fail goto*//*Label 464*/ 11724, // Rule ID 931 // |
| 5613 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5613 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5614 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_h, |
5614 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_h, |
| 5615 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
5615 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 5616 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
5616 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5617 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
5617 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 5618 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
5618 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 5619 |
// MIs[0] m |
5619 |
// MIs[0] m |
| 5620 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5620 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5621 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt4, |
5621 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt4, |
| 5622 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5776:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m) |
5622 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5776:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m) |
| 5623 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_H, |
5623 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_H, |
| 5624 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5624 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5625 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5625 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5626 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5626 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5627 |
GIR_EraseFromParent, /*InsnID*/0, |
5627 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5628 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5628 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5629 |
// GIR_Coverage, 931, |
5629 |
// GIR_Coverage, 931, |
| 5630 |
GIR_Done, |
5630 |
GIR_Done, |
| 5631 |
// Label 464: @11724 |
5631 |
// Label 464: @11724 |
| 5632 |
GIM_Try, /*On fail goto*//*Label 465*/ 11775, // Rule ID 932 // |
5632 |
GIM_Try, /*On fail goto*//*Label 465*/ 11775, // Rule ID 932 // |
| 5633 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5633 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5634 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_w, |
5634 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_w, |
| 5635 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
5635 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5636 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
5636 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5637 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
5637 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 5638 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
5638 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 5639 |
// MIs[0] m |
5639 |
// MIs[0] m |
| 5640 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5640 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5641 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
5641 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
| 5642 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5777:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m) |
5642 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5777:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m) |
| 5643 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_W, |
5643 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_W, |
| 5644 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5644 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5645 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5645 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5646 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5646 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5647 |
GIR_EraseFromParent, /*InsnID*/0, |
5647 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5648 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5648 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5649 |
// GIR_Coverage, 932, |
5649 |
// GIR_Coverage, 932, |
| 5650 |
GIR_Done, |
5650 |
GIR_Done, |
| 5651 |
// Label 465: @11775 |
5651 |
// Label 465: @11775 |
| 5652 |
GIM_Try, /*On fail goto*//*Label 466*/ 11826, // Rule ID 933 // |
5652 |
GIM_Try, /*On fail goto*//*Label 466*/ 11826, // Rule ID 933 // |
| 5653 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5653 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5654 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_d, |
5654 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_d, |
| 5655 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
5655 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5656 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
5656 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5657 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
5657 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 5658 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
5658 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 5659 |
// MIs[0] m |
5659 |
// MIs[0] m |
| 5660 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5660 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5661 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt6, |
5661 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt6, |
| 5662 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5775:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m) |
5662 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5775:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<>:$m) => (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m) |
| 5663 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_D, |
5663 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_D, |
| 5664 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5664 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5665 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5665 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5666 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5666 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5667 |
GIR_EraseFromParent, /*InsnID*/0, |
5667 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5668 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5668 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5669 |
// GIR_Coverage, 933, |
5669 |
// GIR_Coverage, 933, |
| 5670 |
GIR_Done, |
5670 |
GIR_Done, |
| 5671 |
// Label 466: @11826 |
5671 |
// Label 466: @11826 |
| 5672 |
GIM_Try, /*On fail goto*//*Label 467*/ 11877, // Rule ID 973 // |
5672 |
GIM_Try, /*On fail goto*//*Label 467*/ 11877, // Rule ID 973 // |
| 5673 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5673 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5674 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_b, |
5674 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_b, |
| 5675 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
5675 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 5676 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
5676 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5677 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
5677 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 5678 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
5678 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 5679 |
// MIs[0] m |
5679 |
// MIs[0] m |
| 5680 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5680 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5681 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt3, |
5681 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt3, |
| 5682 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5829:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m) |
5682 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5829:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m) |
| 5683 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_B, |
5683 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_B, |
| 5684 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5684 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5685 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5685 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5686 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5686 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5687 |
GIR_EraseFromParent, /*InsnID*/0, |
5687 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5688 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5688 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5689 |
// GIR_Coverage, 973, |
5689 |
// GIR_Coverage, 973, |
| 5690 |
GIR_Done, |
5690 |
GIR_Done, |
| 5691 |
// Label 467: @11877 |
5691 |
// Label 467: @11877 |
| 5692 |
GIM_Try, /*On fail goto*//*Label 468*/ 11928, // Rule ID 974 // |
5692 |
GIM_Try, /*On fail goto*//*Label 468*/ 11928, // Rule ID 974 // |
| 5693 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5693 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5694 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_h, |
5694 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_h, |
| 5695 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
5695 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 5696 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
5696 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5697 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
5697 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 5698 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
5698 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 5699 |
// MIs[0] m |
5699 |
// MIs[0] m |
| 5700 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5700 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5701 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt4, |
5701 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt4, |
| 5702 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5831:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m) |
5702 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5831:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m) |
| 5703 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_H, |
5703 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_H, |
| 5704 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5704 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5705 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5705 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5706 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5706 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5707 |
GIR_EraseFromParent, /*InsnID*/0, |
5707 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5708 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5708 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5709 |
// GIR_Coverage, 974, |
5709 |
// GIR_Coverage, 974, |
| 5710 |
GIR_Done, |
5710 |
GIR_Done, |
| 5711 |
// Label 468: @11928 |
5711 |
// Label 468: @11928 |
| 5712 |
GIM_Try, /*On fail goto*//*Label 469*/ 11979, // Rule ID 975 // |
5712 |
GIM_Try, /*On fail goto*//*Label 469*/ 11979, // Rule ID 975 // |
| 5713 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5713 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5714 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_w, |
5714 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_w, |
| 5715 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
5715 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5716 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
5716 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5717 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
5717 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 5718 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
5718 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 5719 |
// MIs[0] m |
5719 |
// MIs[0] m |
| 5720 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5720 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5721 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
5721 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
| 5722 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5832:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m) |
5722 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5832:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m) |
| 5723 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_W, |
5723 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_W, |
| 5724 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5724 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5725 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5725 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5726 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5726 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5727 |
GIR_EraseFromParent, /*InsnID*/0, |
5727 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5728 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5728 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5729 |
// GIR_Coverage, 975, |
5729 |
// GIR_Coverage, 975, |
| 5730 |
GIR_Done, |
5730 |
GIR_Done, |
| 5731 |
// Label 469: @11979 |
5731 |
// Label 469: @11979 |
| 5732 |
GIM_Try, /*On fail goto*//*Label 470*/ 12030, // Rule ID 976 // |
5732 |
GIM_Try, /*On fail goto*//*Label 470*/ 12030, // Rule ID 976 // |
| 5733 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5733 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5734 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_d, |
5734 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_d, |
| 5735 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
5735 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5736 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
5736 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5737 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
5737 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 5738 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
5738 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 5739 |
// MIs[0] m |
5739 |
// MIs[0] m |
| 5740 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5740 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5741 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt6, |
5741 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt6, |
| 5742 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5830:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m) |
5742 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5830:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m) |
| 5743 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_D, |
5743 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_D, |
| 5744 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5744 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5745 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5745 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5746 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5746 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5747 |
GIR_EraseFromParent, /*InsnID*/0, |
5747 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5748 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5748 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5749 |
// GIR_Coverage, 976, |
5749 |
// GIR_Coverage, 976, |
| 5750 |
GIR_Done, |
5750 |
GIR_Done, |
| 5751 |
// Label 470: @12030 |
5751 |
// Label 470: @12030 |
| 5752 |
GIM_Try, /*On fail goto*//*Label 471*/ 12081, // Rule ID 989 // |
5752 |
GIM_Try, /*On fail goto*//*Label 471*/ 12081, // Rule ID 989 // |
| 5753 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5753 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5754 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_b, |
5754 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_b, |
| 5755 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
5755 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 5756 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
5756 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5757 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
5757 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 5758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
5758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 5759 |
// MIs[0] m |
5759 |
// MIs[0] m |
| 5760 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5760 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5761 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt3, |
5761 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt3, |
| 5762 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5845:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m) |
5762 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5845:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m) |
| 5763 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_B, |
5763 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_B, |
| 5764 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5764 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5766 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5766 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5767 |
GIR_EraseFromParent, /*InsnID*/0, |
5767 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5768 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5768 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5769 |
// GIR_Coverage, 989, |
5769 |
// GIR_Coverage, 989, |
| 5770 |
GIR_Done, |
5770 |
GIR_Done, |
| 5771 |
// Label 471: @12081 |
5771 |
// Label 471: @12081 |
| 5772 |
GIM_Try, /*On fail goto*//*Label 472*/ 12132, // Rule ID 990 // |
5772 |
GIM_Try, /*On fail goto*//*Label 472*/ 12132, // Rule ID 990 // |
| 5773 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5773 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5774 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_h, |
5774 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_h, |
| 5775 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
5775 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 5776 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
5776 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5777 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
5777 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 5778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
5778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 5779 |
// MIs[0] m |
5779 |
// MIs[0] m |
| 5780 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5780 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5781 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt4, |
5781 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt4, |
| 5782 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5847:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m) |
5782 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5847:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m) |
| 5783 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_H, |
5783 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_H, |
| 5784 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5784 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5785 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5785 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5786 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5786 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5787 |
GIR_EraseFromParent, /*InsnID*/0, |
5787 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5788 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5788 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5789 |
// GIR_Coverage, 990, |
5789 |
// GIR_Coverage, 990, |
| 5790 |
GIR_Done, |
5790 |
GIR_Done, |
| 5791 |
// Label 472: @12132 |
5791 |
// Label 472: @12132 |
| 5792 |
GIM_Try, /*On fail goto*//*Label 473*/ 12183, // Rule ID 991 // |
5792 |
GIM_Try, /*On fail goto*//*Label 473*/ 12183, // Rule ID 991 // |
| 5793 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5793 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5794 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_w, |
5794 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_w, |
| 5795 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
5795 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 5796 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
5796 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5797 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
5797 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 5798 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
5798 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 5799 |
// MIs[0] m |
5799 |
// MIs[0] m |
| 5800 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5800 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5801 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
5801 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
| 5802 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5848:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m) |
5802 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5848:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m) |
| 5803 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_W, |
5803 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_W, |
| 5804 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5804 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5805 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5805 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5806 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5806 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5807 |
GIR_EraseFromParent, /*InsnID*/0, |
5807 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5808 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5808 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5809 |
// GIR_Coverage, 991, |
5809 |
// GIR_Coverage, 991, |
| 5810 |
GIR_Done, |
5810 |
GIR_Done, |
| 5811 |
// Label 473: @12183 |
5811 |
// Label 473: @12183 |
| 5812 |
GIM_Try, /*On fail goto*//*Label 474*/ 12234, // Rule ID 992 // |
5812 |
GIM_Try, /*On fail goto*//*Label 474*/ 12234, // Rule ID 992 // |
| 5813 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
5813 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 5814 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_d, |
5814 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_d, |
| 5815 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
5815 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 5816 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
5816 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5817 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
5817 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 5818 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
5818 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 5819 |
// MIs[0] m |
5819 |
// MIs[0] m |
| 5820 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
5820 |
GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 5821 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt6, |
5821 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GICXXPred_I64_Predicate_timmZExt6, |
| 5822 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5846:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m) |
5822 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5846:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<>:$m) => (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m) |
| 5823 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_D, |
5823 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_D, |
| 5824 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
5824 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 5825 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
5825 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 5826 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
5826 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // m |
| 5827 |
GIR_EraseFromParent, /*InsnID*/0, |
5827 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5828 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5828 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5829 |
// GIR_Coverage, 992, |
5829 |
// GIR_Coverage, 992, |
| 5830 |
GIR_Done, |
5830 |
GIR_Done, |
| 5831 |
// Label 474: @12234 |
5831 |
// Label 474: @12234 |
| 5832 |
GIM_Try, /*On fail goto*//*Label 475*/ 12293, // Rule ID 373 // |
5832 |
GIM_Try, /*On fail goto*//*Label 475*/ 12293, // Rule ID 373 // |
| 5833 |
GIM_CheckFeatures, GIFBS_HasDSP, |
5833 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 5834 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph, |
5834 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph, |
| 5835 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
5835 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 5836 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
5836 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 5837 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
5837 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 5838 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5838 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5839 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5839 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5840 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
5840 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 5841 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
5841 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 5842 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
5842 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
| 5843 |
// MIs[1] Operand 1 |
5843 |
// MIs[1] Operand 1 |
| 5844 |
// No operand predicates |
5844 |
// No operand predicates |
| 5845 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
5845 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5846 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5788:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<>:$rs_sa) => (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa) |
5846 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5788:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<>:$rs_sa) => (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa) |
| 5847 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH, |
5847 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH, |
| 5848 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
5848 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 5849 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
5849 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 5850 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa |
5850 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa |
| 5851 |
GIR_EraseFromParent, /*InsnID*/0, |
5851 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5852 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5852 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5853 |
// GIR_Coverage, 373, |
5853 |
// GIR_Coverage, 373, |
| 5854 |
GIR_Done, |
5854 |
GIR_Done, |
| 5855 |
// Label 475: @12293 |
5855 |
// Label 475: @12293 |
| 5856 |
GIM_Try, /*On fail goto*//*Label 476*/ 12352, // Rule ID 377 // |
5856 |
GIM_Try, /*On fail goto*//*Label 476*/ 12352, // Rule ID 377 // |
| 5857 |
GIM_CheckFeatures, GIFBS_HasDSP, |
5857 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 5858 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w, |
5858 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w, |
| 5859 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
5859 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 5860 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
5860 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 5861 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
5861 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 5862 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
5862 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 5863 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
5863 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 5864 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
5864 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 5865 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
5865 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 5866 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
5866 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 5867 |
// MIs[1] Operand 1 |
5867 |
// MIs[1] Operand 1 |
| 5868 |
// No operand predicates |
5868 |
// No operand predicates |
| 5869 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
5869 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5870 |
// (intrinsic_wo_chain:{ *:[i32] } 5790:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$rs_sa) => (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa) |
5870 |
// (intrinsic_wo_chain:{ *:[i32] } 5790:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$rs_sa) => (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa) |
| 5871 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W, |
5871 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W, |
| 5872 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
5872 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 5873 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
5873 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 5874 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa |
5874 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa |
| 5875 |
GIR_EraseFromParent, /*InsnID*/0, |
5875 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5876 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5876 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5877 |
// GIR_Coverage, 377, |
5877 |
// GIR_Coverage, 377, |
| 5878 |
GIR_Done, |
5878 |
GIR_Done, |
| 5879 |
// Label 476: @12352 |
5879 |
// Label 476: @12352 |
| 5880 |
GIM_Try, /*On fail goto*//*Label 477*/ 12411, // Rule ID 468 // |
5880 |
GIM_Try, /*On fail goto*//*Label 477*/ 12411, // Rule ID 468 // |
| 5881 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
5881 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 5882 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb, |
5882 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb, |
| 5883 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
5883 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 5884 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
5884 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 5885 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
5885 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 5886 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5886 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5887 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5887 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5888 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
5888 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 5889 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
5889 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 5890 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt3, |
5890 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt3, |
| 5891 |
// MIs[1] Operand 1 |
5891 |
// MIs[1] Operand 1 |
| 5892 |
// No operand predicates |
5892 |
// No operand predicates |
| 5893 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
5893 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5894 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5789:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<>:$rs_sa) => (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa) |
5894 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5789:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<>:$rs_sa) => (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa) |
| 5895 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB, |
5895 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB, |
| 5896 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
5896 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 5897 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
5897 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 5898 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa |
5898 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa |
| 5899 |
GIR_EraseFromParent, /*InsnID*/0, |
5899 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5900 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5900 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5901 |
// GIR_Coverage, 468, |
5901 |
// GIR_Coverage, 468, |
| 5902 |
GIR_Done, |
5902 |
GIR_Done, |
| 5903 |
// Label 477: @12411 |
5903 |
// Label 477: @12411 |
| 5904 |
GIM_Try, /*On fail goto*//*Label 478*/ 12470, // Rule ID 1233 // |
5904 |
GIM_Try, /*On fail goto*//*Label 478*/ 12470, // Rule ID 1233 // |
| 5905 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5905 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5906 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph, |
5906 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph, |
| 5907 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
5907 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 5908 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
5908 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 5909 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
5909 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 5910 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5910 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5911 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5911 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5912 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
5912 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 5913 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
5913 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 5914 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
5914 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
| 5915 |
// MIs[1] Operand 1 |
5915 |
// MIs[1] Operand 1 |
| 5916 |
// No operand predicates |
5916 |
// No operand predicates |
| 5917 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
5917 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5918 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5788:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<>:$sa) => (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa) |
5918 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5788:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<>:$sa) => (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa) |
| 5919 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH_MM, |
5919 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH_MM, |
| 5920 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5920 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5921 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5921 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5922 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa |
5922 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa |
| 5923 |
GIR_EraseFromParent, /*InsnID*/0, |
5923 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5924 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5924 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5925 |
// GIR_Coverage, 1233, |
5925 |
// GIR_Coverage, 1233, |
| 5926 |
GIR_Done, |
5926 |
GIR_Done, |
| 5927 |
// Label 478: @12470 |
5927 |
// Label 478: @12470 |
| 5928 |
GIM_Try, /*On fail goto*//*Label 479*/ 12529, // Rule ID 1237 // |
5928 |
GIM_Try, /*On fail goto*//*Label 479*/ 12529, // Rule ID 1237 // |
| 5929 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
5929 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 5930 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w, |
5930 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w, |
| 5931 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
5931 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 5932 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
5932 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 5933 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
5933 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 5934 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
5934 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 5935 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
5935 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 5936 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
5936 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 5937 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
5937 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 5938 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
5938 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 5939 |
// MIs[1] Operand 1 |
5939 |
// MIs[1] Operand 1 |
| 5940 |
// No operand predicates |
5940 |
// No operand predicates |
| 5941 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
5941 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5942 |
// (intrinsic_wo_chain:{ *:[i32] } 5790:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$sa) => (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa) |
5942 |
// (intrinsic_wo_chain:{ *:[i32] } 5790:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$sa) => (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa) |
| 5943 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W_MM, |
5943 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W_MM, |
| 5944 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5944 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5945 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5945 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5946 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa |
5946 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa |
| 5947 |
GIR_EraseFromParent, /*InsnID*/0, |
5947 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5948 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5948 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5949 |
// GIR_Coverage, 1237, |
5949 |
// GIR_Coverage, 1237, |
| 5950 |
GIR_Done, |
5950 |
GIR_Done, |
| 5951 |
// Label 479: @12529 |
5951 |
// Label 479: @12529 |
| 5952 |
GIM_Try, /*On fail goto*//*Label 480*/ 12588, // Rule ID 1312 // |
5952 |
GIM_Try, /*On fail goto*//*Label 480*/ 12588, // Rule ID 1312 // |
| 5953 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
5953 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 5954 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb, |
5954 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb, |
| 5955 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
5955 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 5956 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
5956 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 5957 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
5957 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 5958 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5958 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5959 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
5959 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 5960 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
5960 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 5961 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
5961 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 5962 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt3, |
5962 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt3, |
| 5963 |
// MIs[1] Operand 1 |
5963 |
// MIs[1] Operand 1 |
| 5964 |
// No operand predicates |
5964 |
// No operand predicates |
| 5965 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
5965 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5966 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5789:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<>:$sa) => (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa) |
5966 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5789:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<>:$sa) => (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa) |
| 5967 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB_MMR2, |
5967 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB_MMR2, |
| 5968 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
5968 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 5969 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
5969 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 5970 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa |
5970 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa |
| 5971 |
GIR_EraseFromParent, /*InsnID*/0, |
5971 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5972 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5972 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5973 |
// GIR_Coverage, 1312, |
5973 |
// GIR_Coverage, 1312, |
| 5974 |
GIR_Done, |
5974 |
GIR_Done, |
| 5975 |
// Label 480: @12588 |
5975 |
// Label 480: @12588 |
| 5976 |
GIM_Try, /*On fail goto*//*Label 481*/ 12643, // Rule ID 1899 // |
5976 |
GIM_Try, /*On fail goto*//*Label 481*/ 12643, // Rule ID 1899 // |
| 5977 |
GIM_CheckFeatures, GIFBS_HasDSP, |
5977 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 5978 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph, |
5978 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph, |
| 5979 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
5979 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 5980 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
5980 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 5981 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
5981 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 5982 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
5982 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 5983 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
5983 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 5984 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
5984 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 5985 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
5985 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
| 5986 |
// MIs[1] Operand 1 |
5986 |
// MIs[1] Operand 1 |
| 5987 |
// No operand predicates |
5987 |
// No operand predicates |
| 5988 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
5988 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 5989 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5786:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<>:$shamt) => (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<>:$shamt) |
5989 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5786:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<>:$shamt) => (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<>:$shamt) |
| 5990 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_PH, |
5990 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_PH, |
| 5991 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
5991 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 5992 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
5992 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 5993 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
5993 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 5994 |
GIR_EraseFromParent, /*InsnID*/0, |
5994 |
GIR_EraseFromParent, /*InsnID*/0, |
| 5995 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
5995 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 5996 |
// GIR_Coverage, 1899, |
5996 |
// GIR_Coverage, 1899, |
| 5997 |
GIR_Done, |
5997 |
GIR_Done, |
| 5998 |
// Label 481: @12643 |
5998 |
// Label 481: @12643 |
| 5999 |
GIM_Try, /*On fail goto*//*Label 482*/ 12698, // Rule ID 1900 // |
5999 |
GIM_Try, /*On fail goto*//*Label 482*/ 12698, // Rule ID 1900 // |
| 6000 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6000 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6001 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph, |
6001 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph, |
| 6002 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
6002 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 6003 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
6003 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 6004 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6004 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6005 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6005 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6006 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
6006 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 6007 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
6007 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 6008 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
6008 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
| 6009 |
// MIs[1] Operand 1 |
6009 |
// MIs[1] Operand 1 |
| 6010 |
// No operand predicates |
6010 |
// No operand predicates |
| 6011 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
6011 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6012 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5791:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<>:$shamt) => (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<>:$shamt) |
6012 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5791:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<>:$shamt) => (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<>:$shamt) |
| 6013 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_PH, |
6013 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_PH, |
| 6014 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6014 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6015 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
6015 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 6016 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
6016 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 6017 |
GIR_EraseFromParent, /*InsnID*/0, |
6017 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6018 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6018 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6019 |
// GIR_Coverage, 1900, |
6019 |
// GIR_Coverage, 1900, |
| 6020 |
GIR_Done, |
6020 |
GIR_Done, |
| 6021 |
// Label 482: @12698 |
6021 |
// Label 482: @12698 |
| 6022 |
GIM_Try, /*On fail goto*//*Label 483*/ 12753, // Rule ID 1905 // |
6022 |
GIM_Try, /*On fail goto*//*Label 483*/ 12753, // Rule ID 1905 // |
| 6023 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6023 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6024 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb, |
6024 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb, |
| 6025 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
6025 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 6026 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
6026 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 6027 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6027 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6028 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6028 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6029 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
6029 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 6030 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
6030 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 6031 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt3, |
6031 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt3, |
| 6032 |
// MIs[1] Operand 1 |
6032 |
// MIs[1] Operand 1 |
| 6033 |
// No operand predicates |
6033 |
// No operand predicates |
| 6034 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
6034 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6035 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5787:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<>:$shamt) => (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<>:$shamt) |
6035 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5787:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<>:$shamt) => (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<>:$shamt) |
| 6036 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_QB, |
6036 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_QB, |
| 6037 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6037 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6038 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
6038 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 6039 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
6039 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 6040 |
GIR_EraseFromParent, /*InsnID*/0, |
6040 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6041 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6041 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6042 |
// GIR_Coverage, 1905, |
6042 |
// GIR_Coverage, 1905, |
| 6043 |
GIR_Done, |
6043 |
GIR_Done, |
| 6044 |
// Label 483: @12753 |
6044 |
// Label 483: @12753 |
| 6045 |
GIM_Try, /*On fail goto*//*Label 484*/ 12808, // Rule ID 1906 // |
6045 |
GIM_Try, /*On fail goto*//*Label 484*/ 12808, // Rule ID 1906 // |
| 6046 |
GIM_CheckFeatures, GIFBS_HasDSP, |
6046 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 6047 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb, |
6047 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb, |
| 6048 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
6048 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 6049 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
6049 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 6050 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6050 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6051 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6051 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6052 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
6052 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 6053 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
6053 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 6054 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt3, |
6054 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt3, |
| 6055 |
// MIs[1] Operand 1 |
6055 |
// MIs[1] Operand 1 |
| 6056 |
// No operand predicates |
6056 |
// No operand predicates |
| 6057 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
6057 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 6058 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5792:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<>:$shamt) => (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<>:$shamt) |
6058 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5792:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<>:$shamt) => (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<>:$shamt) |
| 6059 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_QB, |
6059 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_QB, |
| 6060 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6060 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6061 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
6061 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 6062 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
6062 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 6063 |
GIR_EraseFromParent, /*InsnID*/0, |
6063 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6064 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6064 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6065 |
// GIR_Coverage, 1906, |
6065 |
// GIR_Coverage, 1906, |
| 6066 |
GIR_Done, |
6066 |
GIR_Done, |
| 6067 |
// Label 484: @12808 |
6067 |
// Label 484: @12808 |
| 6068 |
GIM_Try, /*On fail goto*//*Label 485*/ 12860, // Rule ID 343 // |
6068 |
GIM_Try, /*On fail goto*//*Label 485*/ 12860, // Rule ID 343 // |
| 6069 |
GIM_CheckFeatures, GIFBS_HasDSP, |
6069 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 6070 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb, |
6070 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb, |
| 6071 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
6071 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 6072 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
6072 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 6073 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
6073 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 6074 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6074 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6075 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6075 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6076 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6076 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6077 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5258:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
6077 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5258:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 6078 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB, |
6078 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB, |
| 6079 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6079 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6080 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6080 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6081 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6081 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6082 |
GIR_EraseFromParent, /*InsnID*/0, |
6082 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6083 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6083 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6084 |
// GIR_Coverage, 343, |
6084 |
// GIR_Coverage, 343, |
| 6085 |
GIR_Done, |
6085 |
GIR_Done, |
| 6086 |
// Label 485: @12860 |
6086 |
// Label 485: @12860 |
| 6087 |
GIM_Try, /*On fail goto*//*Label 486*/ 12912, // Rule ID 344 // |
6087 |
GIM_Try, /*On fail goto*//*Label 486*/ 12912, // Rule ID 344 // |
| 6088 |
GIM_CheckFeatures, GIFBS_HasDSP, |
6088 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 6089 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb, |
6089 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb, |
| 6090 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
6090 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 6091 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
6091 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 6092 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
6092 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 6093 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6093 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6094 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6094 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6095 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6095 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6096 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5881:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
6096 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5881:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 6097 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB, |
6097 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB, |
| 6098 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6098 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6099 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6099 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6100 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6100 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6101 |
GIR_EraseFromParent, /*InsnID*/0, |
6101 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6102 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6102 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6103 |
// GIR_Coverage, 344, |
6103 |
// GIR_Coverage, 344, |
| 6104 |
GIR_Done, |
6104 |
GIR_Done, |
| 6105 |
// Label 486: @12912 |
6105 |
// Label 486: @12912 |
| 6106 |
GIM_Try, /*On fail goto*//*Label 487*/ 12964, // Rule ID 345 // |
6106 |
GIM_Try, /*On fail goto*//*Label 487*/ 12964, // Rule ID 345 // |
| 6107 |
GIM_CheckFeatures, GIFBS_HasDSP, |
6107 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 6108 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph, |
6108 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph, |
| 6109 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
6109 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 6110 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
6110 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 6111 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
6111 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 6112 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6112 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6113 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6113 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6114 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6114 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6115 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5236:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
6115 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5236:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 6116 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH, |
6116 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH, |
| 6117 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6117 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6118 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6118 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6119 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6119 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6120 |
GIR_EraseFromParent, /*InsnID*/0, |
6120 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6121 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6121 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6122 |
// GIR_Coverage, 345, |
6122 |
// GIR_Coverage, 345, |
| 6123 |
GIR_Done, |
6123 |
GIR_Done, |
| 6124 |
// Label 487: @12964 |
6124 |
// Label 487: @12964 |
| 6125 |
GIM_Try, /*On fail goto*//*Label 488*/ 13016, // Rule ID 346 // |
6125 |
GIM_Try, /*On fail goto*//*Label 488*/ 13016, // Rule ID 346 // |
| 6126 |
GIM_CheckFeatures, GIFBS_HasDSP, |
6126 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 6127 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph, |
6127 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph, |
| 6128 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
6128 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 6129 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
6129 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 6130 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
6130 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 6131 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6131 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6132 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6132 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6133 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6133 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6134 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5856:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
6134 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5856:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 6135 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH, |
6135 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH, |
| 6136 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6136 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6137 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6137 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6138 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6138 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6139 |
GIR_EraseFromParent, /*InsnID*/0, |
6139 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6140 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6140 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6141 |
// GIR_Coverage, 346, |
6141 |
// GIR_Coverage, 346, |
| 6142 |
GIR_Done, |
6142 |
GIR_Done, |
| 6143 |
// Label 488: @13016 |
6143 |
// Label 488: @13016 |
| 6144 |
GIM_Try, /*On fail goto*//*Label 489*/ 13068, // Rule ID 349 // |
6144 |
GIM_Try, /*On fail goto*//*Label 489*/ 13068, // Rule ID 349 // |
| 6145 |
GIM_CheckFeatures, GIFBS_HasDSP, |
6145 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 6146 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub, |
6146 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub, |
| 6147 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
6147 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 6148 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
6148 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 6149 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6149 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6150 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
6150 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 6151 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
6151 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 6152 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
6152 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 6153 |
// (intrinsic_wo_chain:{ *:[i32] } 5686:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
6153 |
// (intrinsic_wo_chain:{ *:[i32] } 5686:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 6154 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB, |
6154 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB, |
| 6155 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6155 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6156 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6156 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6157 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6157 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6158 |
GIR_EraseFromParent, /*InsnID*/0, |
6158 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6159 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6159 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6160 |
// GIR_Coverage, 349, |
6160 |
// GIR_Coverage, 349, |
| 6161 |
GIR_Done, |
6161 |
GIR_Done, |
| 6162 |
// Label 489: @13068 |
6162 |
// Label 489: @13068 |
| 6163 |
GIM_Try, /*On fail goto*//*Label 490*/ 13120, // Rule ID 353 // |
6163 |
GIM_Try, /*On fail goto*//*Label 490*/ 13120, // Rule ID 353 // |
| 6164 |
GIM_CheckFeatures, GIFBS_HasDSP, |
6164 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 6165 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph, |
6165 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph, |
| 6166 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
6166 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 6167 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
6167 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 6168 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
6168 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 6169 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6169 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6170 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6170 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6171 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6171 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6172 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5762:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
6172 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5762:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 6173 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH, |
6173 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH, |
| 6174 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6174 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6175 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6175 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6176 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6176 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6177 |
GIR_EraseFromParent, /*InsnID*/0, |
6177 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6178 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6178 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6179 |
// GIR_Coverage, 353, |
6179 |
// GIR_Coverage, 353, |
| 6180 |
GIR_Done, |
6180 |
GIR_Done, |
| 6181 |
// Label 490: @13120 |
6181 |
// Label 490: @13120 |
| 6182 |
GIM_Try, /*On fail goto*//*Label 491*/ 13172, // Rule ID 354 // |
6182 |
GIM_Try, /*On fail goto*//*Label 491*/ 13172, // Rule ID 354 // |
| 6183 |
GIM_CheckFeatures, GIFBS_HasDSP, |
6183 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 6184 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w, |
6184 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w, |
| 6185 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
6185 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 6186 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
6186 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 6187 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6187 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6188 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6188 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6189 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
6189 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 6190 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
6190 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 6191 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5761:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
6191 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5761:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 6192 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W, |
6192 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W, |
| 6193 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6193 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6194 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6194 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6195 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6195 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6196 |
GIR_EraseFromParent, /*InsnID*/0, |
6196 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6197 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6197 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6198 |
// GIR_Coverage, 354, |
6198 |
// GIR_Coverage, 354, |
| 6199 |
GIR_Done, |
6199 |
GIR_Done, |
| 6200 |
// Label 491: @13172 |
6200 |
// Label 491: @13172 |
| 6201 |
GIM_Try, /*On fail goto*//*Label 492*/ 13224, // Rule ID 368 // |
6201 |
GIM_Try, /*On fail goto*//*Label 492*/ 13224, // Rule ID 368 // |
| 6202 |
GIM_CheckFeatures, GIFBS_HasDSP, |
6202 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 6203 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb, |
6203 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb, |
| 6204 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
6204 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 6205 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
6205 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 6206 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6206 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6207 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6207 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6208 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6208 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6209 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
6209 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 6210 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5792:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
6210 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5792:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
| 6211 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB, |
6211 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB, |
| 6212 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6212 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6213 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
6213 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 6214 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
6214 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
| 6215 |
GIR_EraseFromParent, /*InsnID*/0, |
6215 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6216 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6216 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6217 |
// GIR_Coverage, 368, |
6217 |
// GIR_Coverage, 368, |
| 6218 |
GIR_Done, |
6218 |
GIR_Done, |
| 6219 |
// Label 492: @13224 |
6219 |
// Label 492: @13224 |
| 6220 |
GIM_Try, /*On fail goto*//*Label 493*/ 13276, // Rule ID 372 // |
6220 |
GIM_Try, /*On fail goto*//*Label 493*/ 13276, // Rule ID 372 // |
| 6221 |
GIM_CheckFeatures, GIFBS_HasDSP, |
6221 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 6222 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph, |
6222 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph, |
| 6223 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
6223 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 6224 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
6224 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 6225 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6225 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6226 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6226 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6227 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6227 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6228 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
6228 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 6229 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5786:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
6229 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5786:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
| 6230 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH, |
6230 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH, |
| 6231 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6231 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6232 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
6232 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 6233 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
6233 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
| 6234 |
GIR_EraseFromParent, /*InsnID*/0, |
6234 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6235 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6235 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6236 |
// GIR_Coverage, 372, |
6236 |
// GIR_Coverage, 372, |
| 6237 |
GIR_Done, |
6237 |
GIR_Done, |
| 6238 |
// Label 493: @13276 |
6238 |
// Label 493: @13276 |
| 6239 |
GIM_Try, /*On fail goto*//*Label 494*/ 13328, // Rule ID 374 // |
6239 |
GIM_Try, /*On fail goto*//*Label 494*/ 13328, // Rule ID 374 // |
| 6240 |
GIM_CheckFeatures, GIFBS_HasDSP, |
6240 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 6241 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph, |
6241 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph, |
| 6242 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
6242 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 6243 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
6243 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 6244 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6244 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6245 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6245 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6246 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6246 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6247 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
6247 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 6248 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5788:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
6248 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5788:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
| 6249 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH, |
6249 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH, |
| 6250 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6250 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6251 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
6251 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 6252 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
6252 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
| 6253 |
GIR_EraseFromParent, /*InsnID*/0, |
6253 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6254 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6254 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6255 |
// GIR_Coverage, 374, |
6255 |
// GIR_Coverage, 374, |
| 6256 |
GIR_Done, |
6256 |
GIR_Done, |
| 6257 |
// Label 494: @13328 |
6257 |
// Label 494: @13328 |
| 6258 |
GIM_Try, /*On fail goto*//*Label 495*/ 13380, // Rule ID 378 // |
6258 |
GIM_Try, /*On fail goto*//*Label 495*/ 13380, // Rule ID 378 // |
| 6259 |
GIM_CheckFeatures, GIFBS_HasDSP, |
6259 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 6260 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w, |
6260 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w, |
| 6261 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
6261 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 6262 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
6262 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 6263 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6263 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6264 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
6264 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 6265 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
6265 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 6266 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
6266 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 6267 |
// (intrinsic_wo_chain:{ *:[i32] } 5790:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
6267 |
// (intrinsic_wo_chain:{ *:[i32] } 5790:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
| 6268 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W, |
6268 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W, |
| 6269 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6269 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6270 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
6270 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 6271 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
6271 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
| 6272 |
GIR_EraseFromParent, /*InsnID*/0, |
6272 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6273 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6273 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6274 |
// GIR_Coverage, 378, |
6274 |
// GIR_Coverage, 378, |
| 6275 |
GIR_Done, |
6275 |
GIR_Done, |
| 6276 |
// Label 495: @13380 |
6276 |
// Label 495: @13380 |
| 6277 |
GIM_Try, /*On fail goto*//*Label 496*/ 13432, // Rule ID 415 // |
6277 |
GIM_Try, /*On fail goto*//*Label 496*/ 13432, // Rule ID 415 // |
| 6278 |
GIM_CheckFeatures, GIFBS_HasDSP, |
6278 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 6279 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph, |
6279 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph, |
| 6280 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
6280 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 6281 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
6281 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 6282 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
6282 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 6283 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6283 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6284 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6284 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6285 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6285 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6286 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5733:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
6286 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5733:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 6287 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH, |
6287 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH, |
| 6288 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6288 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6289 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6289 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6290 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6290 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6291 |
GIR_EraseFromParent, /*InsnID*/0, |
6291 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6292 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6292 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6293 |
// GIR_Coverage, 415, |
6293 |
// GIR_Coverage, 415, |
| 6294 |
GIR_Done, |
6294 |
GIR_Done, |
| 6295 |
// Label 496: @13432 |
6295 |
// Label 496: @13432 |
| 6296 |
GIM_Try, /*On fail goto*//*Label 497*/ 13484, // Rule ID 439 // |
6296 |
GIM_Try, /*On fail goto*//*Label 497*/ 13484, // Rule ID 439 // |
| 6297 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6297 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6298 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb, |
6298 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb, |
| 6299 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
6299 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 6300 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
6300 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 6301 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
6301 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 6302 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6302 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6303 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6303 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6304 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6304 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6305 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5259:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
6305 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5259:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 6306 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB, |
6306 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB, |
| 6307 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6307 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6308 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6308 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6309 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6309 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6310 |
GIR_EraseFromParent, /*InsnID*/0, |
6310 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6311 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6311 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6312 |
// GIR_Coverage, 439, |
6312 |
// GIR_Coverage, 439, |
| 6313 |
GIR_Done, |
6313 |
GIR_Done, |
| 6314 |
// Label 497: @13484 |
6314 |
// Label 497: @13484 |
| 6315 |
GIM_Try, /*On fail goto*//*Label 498*/ 13536, // Rule ID 440 // |
6315 |
GIM_Try, /*On fail goto*//*Label 498*/ 13536, // Rule ID 440 // |
| 6316 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6316 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6317 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb, |
6317 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb, |
| 6318 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
6318 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 6319 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
6319 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 6320 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
6320 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 6321 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6321 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6322 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6322 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6323 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6323 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6324 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5260:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
6324 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5260:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 6325 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB, |
6325 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB, |
| 6326 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6326 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6327 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6327 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6328 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6328 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6329 |
GIR_EraseFromParent, /*InsnID*/0, |
6329 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6330 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6330 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6331 |
// GIR_Coverage, 440, |
6331 |
// GIR_Coverage, 440, |
| 6332 |
GIR_Done, |
6332 |
GIR_Done, |
| 6333 |
// Label 498: @13536 |
6333 |
// Label 498: @13536 |
| 6334 |
GIM_Try, /*On fail goto*//*Label 499*/ 13588, // Rule ID 441 // |
6334 |
GIM_Try, /*On fail goto*//*Label 499*/ 13588, // Rule ID 441 // |
| 6335 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6335 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6336 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb, |
6336 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb, |
| 6337 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
6337 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 6338 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
6338 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 6339 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
6339 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 6340 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6340 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6341 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6341 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6342 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6342 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6343 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5882:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
6343 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5882:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 6344 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB, |
6344 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB, |
| 6345 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6345 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6346 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6346 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6347 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6347 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6348 |
GIR_EraseFromParent, /*InsnID*/0, |
6348 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6349 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6349 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6350 |
// GIR_Coverage, 441, |
6350 |
// GIR_Coverage, 441, |
| 6351 |
GIR_Done, |
6351 |
GIR_Done, |
| 6352 |
// Label 499: @13588 |
6352 |
// Label 499: @13588 |
| 6353 |
GIM_Try, /*On fail goto*//*Label 500*/ 13640, // Rule ID 442 // |
6353 |
GIM_Try, /*On fail goto*//*Label 500*/ 13640, // Rule ID 442 // |
| 6354 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6354 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6355 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb, |
6355 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb, |
| 6356 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
6356 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 6357 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
6357 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 6358 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
6358 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 6359 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6359 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6360 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6360 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6361 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6361 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6362 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5883:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
6362 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5883:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 6363 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB, |
6363 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB, |
| 6364 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6364 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6365 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6365 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6366 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6366 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6367 |
GIR_EraseFromParent, /*InsnID*/0, |
6367 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6368 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6368 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6369 |
// GIR_Coverage, 442, |
6369 |
// GIR_Coverage, 442, |
| 6370 |
GIR_Done, |
6370 |
GIR_Done, |
| 6371 |
// Label 500: @13640 |
6371 |
// Label 500: @13640 |
| 6372 |
GIM_Try, /*On fail goto*//*Label 501*/ 13692, // Rule ID 443 // |
6372 |
GIM_Try, /*On fail goto*//*Label 501*/ 13692, // Rule ID 443 // |
| 6373 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6373 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6374 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph, |
6374 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph, |
| 6375 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
6375 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 6376 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
6376 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 6377 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
6377 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 6378 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6378 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6379 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6379 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6380 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6380 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6381 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5238:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
6381 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5238:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 6382 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH, |
6382 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH, |
| 6383 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6383 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6384 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6384 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6385 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6385 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6386 |
GIR_EraseFromParent, /*InsnID*/0, |
6386 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6387 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6387 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6388 |
// GIR_Coverage, 443, |
6388 |
// GIR_Coverage, 443, |
| 6389 |
GIR_Done, |
6389 |
GIR_Done, |
| 6390 |
// Label 501: @13692 |
6390 |
// Label 501: @13692 |
| 6391 |
GIM_Try, /*On fail goto*//*Label 502*/ 13744, // Rule ID 444 // |
6391 |
GIM_Try, /*On fail goto*//*Label 502*/ 13744, // Rule ID 444 // |
| 6392 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6392 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6393 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph, |
6393 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph, |
| 6394 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
6394 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 6395 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
6395 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 6396 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
6396 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 6397 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6397 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6398 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6398 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6399 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6399 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6400 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5239:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
6400 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5239:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 6401 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH, |
6401 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH, |
| 6402 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6402 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6403 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6403 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6404 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6404 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6405 |
GIR_EraseFromParent, /*InsnID*/0, |
6405 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6406 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6406 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6407 |
// GIR_Coverage, 444, |
6407 |
// GIR_Coverage, 444, |
| 6408 |
GIR_Done, |
6408 |
GIR_Done, |
| 6409 |
// Label 502: @13744 |
6409 |
// Label 502: @13744 |
| 6410 |
GIM_Try, /*On fail goto*//*Label 503*/ 13796, // Rule ID 445 // |
6410 |
GIM_Try, /*On fail goto*//*Label 503*/ 13796, // Rule ID 445 // |
| 6411 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6411 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6412 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph, |
6412 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph, |
| 6413 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
6413 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 6414 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
6414 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 6415 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
6415 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 6416 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6416 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6417 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6417 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6418 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6418 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6419 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5858:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
6419 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5858:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 6420 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH, |
6420 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH, |
| 6421 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6421 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6422 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6422 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6423 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6423 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6424 |
GIR_EraseFromParent, /*InsnID*/0, |
6424 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6425 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6425 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6426 |
// GIR_Coverage, 445, |
6426 |
// GIR_Coverage, 445, |
| 6427 |
GIR_Done, |
6427 |
GIR_Done, |
| 6428 |
// Label 503: @13796 |
6428 |
// Label 503: @13796 |
| 6429 |
GIM_Try, /*On fail goto*//*Label 504*/ 13848, // Rule ID 446 // |
6429 |
GIM_Try, /*On fail goto*//*Label 504*/ 13848, // Rule ID 446 // |
| 6430 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6430 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6431 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph, |
6431 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph, |
| 6432 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
6432 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 6433 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
6433 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 6434 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
6434 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 6435 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6435 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6436 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6436 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6437 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
6437 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 6438 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5859:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
6438 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5859:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 6439 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH, |
6439 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH, |
| 6440 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6440 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6441 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6441 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6442 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6442 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6443 |
GIR_EraseFromParent, /*InsnID*/0, |
6443 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6444 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6444 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6445 |
// GIR_Coverage, 446, |
6445 |
// GIR_Coverage, 446, |
| 6446 |
GIR_Done, |
6446 |
GIR_Done, |
| 6447 |
// Label 504: @13848 |
6447 |
// Label 504: @13848 |
| 6448 |
GIM_Try, /*On fail goto*//*Label 505*/ 13900, // Rule ID 447 // |
6448 |
GIM_Try, /*On fail goto*//*Label 505*/ 13900, // Rule ID 447 // |
| 6449 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6449 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6450 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w, |
6450 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w, |
| 6451 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
6451 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 6452 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
6452 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 6453 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6453 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6454 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
6454 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 6455 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
6455 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 6456 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
6456 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 6457 |
// (intrinsic_wo_chain:{ *:[i32] } 5241:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
6457 |
// (intrinsic_wo_chain:{ *:[i32] } 5241:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 6458 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W, |
6458 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W, |
| 6459 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6459 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6460 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6460 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6461 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6461 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6462 |
GIR_EraseFromParent, /*InsnID*/0, |
6462 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6463 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6463 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6464 |
// GIR_Coverage, 447, |
6464 |
// GIR_Coverage, 447, |
| 6465 |
GIR_Done, |
6465 |
GIR_Done, |
| 6466 |
// Label 505: @13900 |
6466 |
// Label 505: @13900 |
| 6467 |
GIM_Try, /*On fail goto*//*Label 506*/ 13952, // Rule ID 448 // |
6467 |
GIM_Try, /*On fail goto*//*Label 506*/ 13952, // Rule ID 448 // |
| 6468 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6468 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6469 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w, |
6469 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w, |
| 6470 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
6470 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 6471 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
6471 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 6472 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6472 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6473 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
6473 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 6474 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
6474 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 6475 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
6475 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 6476 |
// (intrinsic_wo_chain:{ *:[i32] } 5240:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
6476 |
// (intrinsic_wo_chain:{ *:[i32] } 5240:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 6477 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W, |
6477 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W, |
| 6478 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6478 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6479 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6479 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6480 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6480 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6481 |
GIR_EraseFromParent, /*InsnID*/0, |
6481 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6482 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6482 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6483 |
// GIR_Coverage, 448, |
6483 |
// GIR_Coverage, 448, |
| 6484 |
GIR_Done, |
6484 |
GIR_Done, |
| 6485 |
// Label 506: @13952 |
6485 |
// Label 506: @13952 |
| 6486 |
GIM_Try, /*On fail goto*//*Label 507*/ 14004, // Rule ID 449 // |
6486 |
GIM_Try, /*On fail goto*//*Label 507*/ 14004, // Rule ID 449 // |
| 6487 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6487 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6488 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w, |
6488 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w, |
| 6489 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
6489 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 6490 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
6490 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 6491 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6491 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6492 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
6492 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 6493 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
6493 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 6494 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
6494 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 6495 |
// (intrinsic_wo_chain:{ *:[i32] } 5861:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
6495 |
// (intrinsic_wo_chain:{ *:[i32] } 5861:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 6496 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W, |
6496 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W, |
| 6497 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6497 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6498 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6498 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6499 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6499 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6500 |
GIR_EraseFromParent, /*InsnID*/0, |
6500 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6501 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6501 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6502 |
// GIR_Coverage, 449, |
6502 |
// GIR_Coverage, 449, |
| 6503 |
GIR_Done, |
6503 |
GIR_Done, |
| 6504 |
// Label 507: @14004 |
6504 |
// Label 507: @14004 |
| 6505 |
GIM_Try, /*On fail goto*//*Label 508*/ 14056, // Rule ID 450 // |
6505 |
GIM_Try, /*On fail goto*//*Label 508*/ 14056, // Rule ID 450 // |
| 6506 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6506 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6507 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w, |
6507 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w, |
| 6508 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
6508 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 6509 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
6509 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 6510 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6510 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6511 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
6511 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 6512 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
6512 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 6513 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
6513 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 6514 |
// (intrinsic_wo_chain:{ *:[i32] } 5860:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
6514 |
// (intrinsic_wo_chain:{ *:[i32] } 5860:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 6515 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W, |
6515 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W, |
| 6516 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6516 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6517 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
6517 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 6518 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
6518 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 6519 |
GIR_EraseFromParent, /*InsnID*/0, |
6519 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6520 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6520 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6521 |
// GIR_Coverage, 450, |
6521 |
// GIR_Coverage, 450, |
| 6522 |
GIR_Done, |
6522 |
GIR_Done, |
| 6523 |
// Label 508: @14056 |
6523 |
// Label 508: @14056 |
| 6524 |
GIM_Try, /*On fail goto*//*Label 509*/ 14108, // Rule ID 467 // |
6524 |
GIM_Try, /*On fail goto*//*Label 509*/ 14108, // Rule ID 467 // |
| 6525 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6525 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6526 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb, |
6526 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb, |
| 6527 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
6527 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 6528 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
6528 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 6529 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6529 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6530 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6530 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6531 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6531 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6532 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
6532 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 6533 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5787:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
6533 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5787:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
| 6534 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB, |
6534 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB, |
| 6535 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6535 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6536 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
6536 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 6537 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
6537 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
| 6538 |
GIR_EraseFromParent, /*InsnID*/0, |
6538 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6539 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6539 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6540 |
// GIR_Coverage, 467, |
6540 |
// GIR_Coverage, 467, |
| 6541 |
GIR_Done, |
6541 |
GIR_Done, |
| 6542 |
// Label 509: @14108 |
6542 |
// Label 509: @14108 |
| 6543 |
GIM_Try, /*On fail goto*//*Label 510*/ 14160, // Rule ID 469 // |
6543 |
GIM_Try, /*On fail goto*//*Label 510*/ 14160, // Rule ID 469 // |
| 6544 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6544 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6545 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb, |
6545 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb, |
| 6546 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
6546 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 6547 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
6547 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 6548 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6548 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6549 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6549 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6550 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6550 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6551 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
6551 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 6552 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5789:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
6552 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5789:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
| 6553 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB, |
6553 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB, |
| 6554 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6554 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6555 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
6555 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 6556 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
6556 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
| 6557 |
GIR_EraseFromParent, /*InsnID*/0, |
6557 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6558 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6558 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6559 |
// GIR_Coverage, 469, |
6559 |
// GIR_Coverage, 469, |
| 6560 |
GIR_Done, |
6560 |
GIR_Done, |
| 6561 |
// Label 510: @14160 |
6561 |
// Label 510: @14160 |
| 6562 |
GIM_Try, /*On fail goto*//*Label 511*/ 14212, // Rule ID 470 // |
6562 |
GIM_Try, /*On fail goto*//*Label 511*/ 14212, // Rule ID 470 // |
| 6563 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
6563 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 6564 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph, |
6564 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph, |
| 6565 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
6565 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 6566 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
6566 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 6567 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
6567 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 6568 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
6568 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 6569 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
6569 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 6570 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
6570 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 6571 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5791:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
6571 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5791:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
| 6572 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH, |
6572 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH, |
| 6573 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
6573 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 6574 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
6574 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 6575 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
6575 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
| 6576 |
GIR_EraseFromParent, /*InsnID*/0, |
6576 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6577 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6577 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6578 |
// GIR_Coverage, 470, |
6578 |
// GIR_Coverage, 470, |
| 6579 |
GIR_Done, |
6579 |
GIR_Done, |
| 6580 |
// Label 511: @14212 |
6580 |
// Label 511: @14212 |
| 6581 |
GIM_Try, /*On fail goto*//*Label 512*/ 14264, // Rule ID 479 // |
6581 |
GIM_Try, /*On fail goto*//*Label 512*/ 14264, // Rule ID 479 // |
| 6582 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6582 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6583 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_b, |
6583 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_b, |
| 6584 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
6584 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 6585 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
6585 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6586 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
6586 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 6587 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
6587 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 6588 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
6588 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 6589 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
6589 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 6590 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5231:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
6590 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5231:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 6591 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_B, |
6591 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_B, |
| 6592 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6592 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6593 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6593 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6594 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6594 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6595 |
GIR_EraseFromParent, /*InsnID*/0, |
6595 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6596 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6596 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6597 |
// GIR_Coverage, 479, |
6597 |
// GIR_Coverage, 479, |
| 6598 |
GIR_Done, |
6598 |
GIR_Done, |
| 6599 |
// Label 512: @14264 |
6599 |
// Label 512: @14264 |
| 6600 |
GIM_Try, /*On fail goto*//*Label 513*/ 14316, // Rule ID 480 // |
6600 |
GIM_Try, /*On fail goto*//*Label 513*/ 14316, // Rule ID 480 // |
| 6601 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6601 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6602 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_h, |
6602 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_h, |
| 6603 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
6603 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 6604 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
6604 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6605 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
6605 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 6606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
6606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 6607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
6607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 6608 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
6608 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 6609 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5233:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
6609 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5233:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 6610 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_H, |
6610 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_H, |
| 6611 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6611 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6612 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6612 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6613 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6613 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6614 |
GIR_EraseFromParent, /*InsnID*/0, |
6614 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6615 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6615 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6616 |
// GIR_Coverage, 480, |
6616 |
// GIR_Coverage, 480, |
| 6617 |
GIR_Done, |
6617 |
GIR_Done, |
| 6618 |
// Label 513: @14316 |
6618 |
// Label 513: @14316 |
| 6619 |
GIM_Try, /*On fail goto*//*Label 514*/ 14368, // Rule ID 481 // |
6619 |
GIM_Try, /*On fail goto*//*Label 514*/ 14368, // Rule ID 481 // |
| 6620 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6620 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6621 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_w, |
6621 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_w, |
| 6622 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
6622 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6623 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
6623 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6624 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
6624 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 6625 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
6625 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 6626 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
6626 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 6627 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
6627 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 6628 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5234:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
6628 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5234:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 6629 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_W, |
6629 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_W, |
| 6630 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6630 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6631 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6631 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6632 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6632 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6633 |
GIR_EraseFromParent, /*InsnID*/0, |
6633 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6634 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6634 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6635 |
// GIR_Coverage, 481, |
6635 |
// GIR_Coverage, 481, |
| 6636 |
GIR_Done, |
6636 |
GIR_Done, |
| 6637 |
// Label 514: @14368 |
6637 |
// Label 514: @14368 |
| 6638 |
GIM_Try, /*On fail goto*//*Label 515*/ 14420, // Rule ID 482 // |
6638 |
GIM_Try, /*On fail goto*//*Label 515*/ 14420, // Rule ID 482 // |
| 6639 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6639 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6640 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_d, |
6640 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_d, |
| 6641 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
6641 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 6642 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
6642 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 6643 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
6643 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 6644 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
6644 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 6645 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
6645 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 6646 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
6646 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 6647 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5232:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
6647 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5232:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 6648 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_D, |
6648 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_D, |
| 6649 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6649 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6650 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6650 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6651 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6651 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6652 |
GIR_EraseFromParent, /*InsnID*/0, |
6652 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6653 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6653 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6654 |
// GIR_Coverage, 482, |
6654 |
// GIR_Coverage, 482, |
| 6655 |
GIR_Done, |
6655 |
GIR_Done, |
| 6656 |
// Label 515: @14420 |
6656 |
// Label 515: @14420 |
| 6657 |
GIM_Try, /*On fail goto*//*Label 516*/ 14472, // Rule ID 483 // |
6657 |
GIM_Try, /*On fail goto*//*Label 516*/ 14472, // Rule ID 483 // |
| 6658 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6658 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6659 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_b, |
6659 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_b, |
| 6660 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
6660 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 6661 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
6661 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6662 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
6662 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 6663 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
6663 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 6664 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
6664 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 6665 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
6665 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 6666 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5242:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
6666 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5242:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 6667 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_B, |
6667 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_B, |
| 6668 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6668 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6669 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6669 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6670 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6670 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6671 |
GIR_EraseFromParent, /*InsnID*/0, |
6671 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6672 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6672 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6673 |
// GIR_Coverage, 483, |
6673 |
// GIR_Coverage, 483, |
| 6674 |
GIR_Done, |
6674 |
GIR_Done, |
| 6675 |
// Label 516: @14472 |
6675 |
// Label 516: @14472 |
| 6676 |
GIM_Try, /*On fail goto*//*Label 517*/ 14524, // Rule ID 484 // |
6676 |
GIM_Try, /*On fail goto*//*Label 517*/ 14524, // Rule ID 484 // |
| 6677 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6677 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6678 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_h, |
6678 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_h, |
| 6679 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
6679 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 6680 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
6680 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6681 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
6681 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 6682 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
6682 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 6683 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
6683 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 6684 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
6684 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 6685 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5244:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
6685 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5244:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 6686 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_H, |
6686 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_H, |
| 6687 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6687 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6688 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6688 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6689 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6689 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6690 |
GIR_EraseFromParent, /*InsnID*/0, |
6690 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6691 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6691 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6692 |
// GIR_Coverage, 484, |
6692 |
// GIR_Coverage, 484, |
| 6693 |
GIR_Done, |
6693 |
GIR_Done, |
| 6694 |
// Label 517: @14524 |
6694 |
// Label 517: @14524 |
| 6695 |
GIM_Try, /*On fail goto*//*Label 518*/ 14576, // Rule ID 485 // |
6695 |
GIM_Try, /*On fail goto*//*Label 518*/ 14576, // Rule ID 485 // |
| 6696 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6696 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6697 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_w, |
6697 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_w, |
| 6698 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
6698 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6699 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
6699 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6700 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
6700 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 6701 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
6701 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 6702 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
6702 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 6703 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
6703 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 6704 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5245:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
6704 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5245:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 6705 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_W, |
6705 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_W, |
| 6706 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6706 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6707 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6707 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6708 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6708 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6709 |
GIR_EraseFromParent, /*InsnID*/0, |
6709 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6710 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6710 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6711 |
// GIR_Coverage, 485, |
6711 |
// GIR_Coverage, 485, |
| 6712 |
GIR_Done, |
6712 |
GIR_Done, |
| 6713 |
// Label 518: @14576 |
6713 |
// Label 518: @14576 |
| 6714 |
GIM_Try, /*On fail goto*//*Label 519*/ 14628, // Rule ID 486 // |
6714 |
GIM_Try, /*On fail goto*//*Label 519*/ 14628, // Rule ID 486 // |
| 6715 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6715 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6716 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_d, |
6716 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_d, |
| 6717 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
6717 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 6718 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
6718 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 6719 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
6719 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 6720 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
6720 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 6721 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
6721 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 6722 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
6722 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 6723 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5243:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
6723 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5243:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 6724 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_D, |
6724 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_D, |
| 6725 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6725 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6726 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6726 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6727 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6727 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6728 |
GIR_EraseFromParent, /*InsnID*/0, |
6728 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6729 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6729 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6730 |
// GIR_Coverage, 486, |
6730 |
// GIR_Coverage, 486, |
| 6731 |
GIR_Done, |
6731 |
GIR_Done, |
| 6732 |
// Label 519: @14628 |
6732 |
// Label 519: @14628 |
| 6733 |
GIM_Try, /*On fail goto*//*Label 520*/ 14680, // Rule ID 487 // |
6733 |
GIM_Try, /*On fail goto*//*Label 520*/ 14680, // Rule ID 487 // |
| 6734 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6734 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6735 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_b, |
6735 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_b, |
| 6736 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
6736 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 6737 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
6737 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6738 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
6738 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 6739 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
6739 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 6740 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
6740 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 6741 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
6741 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 6742 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5246:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
6742 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5246:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 6743 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_B, |
6743 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_B, |
| 6744 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6744 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6745 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6745 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6746 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6746 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6747 |
GIR_EraseFromParent, /*InsnID*/0, |
6747 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6748 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6748 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6749 |
// GIR_Coverage, 487, |
6749 |
// GIR_Coverage, 487, |
| 6750 |
GIR_Done, |
6750 |
GIR_Done, |
| 6751 |
// Label 520: @14680 |
6751 |
// Label 520: @14680 |
| 6752 |
GIM_Try, /*On fail goto*//*Label 521*/ 14732, // Rule ID 488 // |
6752 |
GIM_Try, /*On fail goto*//*Label 521*/ 14732, // Rule ID 488 // |
| 6753 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6753 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6754 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_h, |
6754 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_h, |
| 6755 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
6755 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 6756 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
6756 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6757 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
6757 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 6758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
6758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 6759 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
6759 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 6760 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
6760 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 6761 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5248:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
6761 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5248:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 6762 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_H, |
6762 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_H, |
| 6763 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6763 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6764 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6764 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6766 |
GIR_EraseFromParent, /*InsnID*/0, |
6766 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6767 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6767 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6768 |
// GIR_Coverage, 488, |
6768 |
// GIR_Coverage, 488, |
| 6769 |
GIR_Done, |
6769 |
GIR_Done, |
| 6770 |
// Label 521: @14732 |
6770 |
// Label 521: @14732 |
| 6771 |
GIM_Try, /*On fail goto*//*Label 522*/ 14784, // Rule ID 489 // |
6771 |
GIM_Try, /*On fail goto*//*Label 522*/ 14784, // Rule ID 489 // |
| 6772 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6772 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6773 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_w, |
6773 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_w, |
| 6774 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
6774 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6775 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
6775 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6776 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
6776 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 6777 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
6777 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 6778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
6778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 6779 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
6779 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 6780 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5249:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
6780 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5249:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 6781 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_W, |
6781 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_W, |
| 6782 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6782 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6783 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6783 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6784 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6784 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6785 |
GIR_EraseFromParent, /*InsnID*/0, |
6785 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6786 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6786 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6787 |
// GIR_Coverage, 489, |
6787 |
// GIR_Coverage, 489, |
| 6788 |
GIR_Done, |
6788 |
GIR_Done, |
| 6789 |
// Label 522: @14784 |
6789 |
// Label 522: @14784 |
| 6790 |
GIM_Try, /*On fail goto*//*Label 523*/ 14836, // Rule ID 490 // |
6790 |
GIM_Try, /*On fail goto*//*Label 523*/ 14836, // Rule ID 490 // |
| 6791 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6791 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6792 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_d, |
6792 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_d, |
| 6793 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
6793 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 6794 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
6794 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 6795 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
6795 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 6796 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
6796 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 6797 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
6797 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 6798 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
6798 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 6799 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5247:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
6799 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5247:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 6800 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_D, |
6800 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_D, |
| 6801 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6801 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6802 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6802 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6803 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6803 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6804 |
GIR_EraseFromParent, /*InsnID*/0, |
6804 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6805 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6805 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6806 |
// GIR_Coverage, 490, |
6806 |
// GIR_Coverage, 490, |
| 6807 |
GIR_Done, |
6807 |
GIR_Done, |
| 6808 |
// Label 523: @14836 |
6808 |
// Label 523: @14836 |
| 6809 |
GIM_Try, /*On fail goto*//*Label 524*/ 14888, // Rule ID 491 // |
6809 |
GIM_Try, /*On fail goto*//*Label 524*/ 14888, // Rule ID 491 // |
| 6810 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6810 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6811 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_b, |
6811 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_b, |
| 6812 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
6812 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 6813 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
6813 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6814 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
6814 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 6815 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
6815 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 6816 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
6816 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 6817 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
6817 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 6818 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5250:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
6818 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5250:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 6819 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_B, |
6819 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_B, |
| 6820 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6820 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6821 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6821 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6822 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6822 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6823 |
GIR_EraseFromParent, /*InsnID*/0, |
6823 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6824 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6824 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6825 |
// GIR_Coverage, 491, |
6825 |
// GIR_Coverage, 491, |
| 6826 |
GIR_Done, |
6826 |
GIR_Done, |
| 6827 |
// Label 524: @14888 |
6827 |
// Label 524: @14888 |
| 6828 |
GIM_Try, /*On fail goto*//*Label 525*/ 14940, // Rule ID 492 // |
6828 |
GIM_Try, /*On fail goto*//*Label 525*/ 14940, // Rule ID 492 // |
| 6829 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6829 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6830 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_h, |
6830 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_h, |
| 6831 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
6831 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 6832 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
6832 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6833 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
6833 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 6834 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
6834 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 6835 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
6835 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 6836 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
6836 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 6837 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5252:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
6837 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5252:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 6838 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_H, |
6838 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_H, |
| 6839 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6839 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6840 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6840 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6841 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6841 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6842 |
GIR_EraseFromParent, /*InsnID*/0, |
6842 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6843 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6843 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6844 |
// GIR_Coverage, 492, |
6844 |
// GIR_Coverage, 492, |
| 6845 |
GIR_Done, |
6845 |
GIR_Done, |
| 6846 |
// Label 525: @14940 |
6846 |
// Label 525: @14940 |
| 6847 |
GIM_Try, /*On fail goto*//*Label 526*/ 14992, // Rule ID 493 // |
6847 |
GIM_Try, /*On fail goto*//*Label 526*/ 14992, // Rule ID 493 // |
| 6848 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6848 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6849 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_w, |
6849 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_w, |
| 6850 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
6850 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6851 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
6851 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6852 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
6852 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 6853 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
6853 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 6854 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
6854 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 6855 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
6855 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 6856 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5253:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
6856 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5253:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 6857 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_W, |
6857 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_W, |
| 6858 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6858 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6859 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6859 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6860 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6860 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6861 |
GIR_EraseFromParent, /*InsnID*/0, |
6861 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6862 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6862 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6863 |
// GIR_Coverage, 493, |
6863 |
// GIR_Coverage, 493, |
| 6864 |
GIR_Done, |
6864 |
GIR_Done, |
| 6865 |
// Label 526: @14992 |
6865 |
// Label 526: @14992 |
| 6866 |
GIM_Try, /*On fail goto*//*Label 527*/ 15044, // Rule ID 494 // |
6866 |
GIM_Try, /*On fail goto*//*Label 527*/ 15044, // Rule ID 494 // |
| 6867 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6867 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6868 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_d, |
6868 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_d, |
| 6869 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
6869 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 6870 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
6870 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 6871 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
6871 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 6872 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
6872 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 6873 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
6873 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 6874 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
6874 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 6875 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5251:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
6875 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5251:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 6876 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_D, |
6876 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_D, |
| 6877 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6877 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6878 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6878 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6879 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6879 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6880 |
GIR_EraseFromParent, /*InsnID*/0, |
6880 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6881 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6881 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6882 |
// GIR_Coverage, 494, |
6882 |
// GIR_Coverage, 494, |
| 6883 |
GIR_Done, |
6883 |
GIR_Done, |
| 6884 |
// Label 527: @15044 |
6884 |
// Label 527: @15044 |
| 6885 |
GIM_Try, /*On fail goto*//*Label 528*/ 15096, // Rule ID 508 // |
6885 |
GIM_Try, /*On fail goto*//*Label 528*/ 15096, // Rule ID 508 // |
| 6886 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6886 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6887 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_b, |
6887 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_b, |
| 6888 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
6888 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 6889 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
6889 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6890 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
6890 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 6891 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
6891 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 6892 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
6892 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 6893 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
6893 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 6894 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5273:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
6894 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5273:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 6895 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_B, |
6895 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_B, |
| 6896 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6896 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6897 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6897 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6898 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6898 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6899 |
GIR_EraseFromParent, /*InsnID*/0, |
6899 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6900 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6900 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6901 |
// GIR_Coverage, 508, |
6901 |
// GIR_Coverage, 508, |
| 6902 |
GIR_Done, |
6902 |
GIR_Done, |
| 6903 |
// Label 528: @15096 |
6903 |
// Label 528: @15096 |
| 6904 |
GIM_Try, /*On fail goto*//*Label 529*/ 15148, // Rule ID 509 // |
6904 |
GIM_Try, /*On fail goto*//*Label 529*/ 15148, // Rule ID 509 // |
| 6905 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6905 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6906 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_h, |
6906 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_h, |
| 6907 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
6907 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 6908 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
6908 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6909 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
6909 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 6910 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
6910 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 6911 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
6911 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 6912 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
6912 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 6913 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5275:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
6913 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5275:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 6914 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_H, |
6914 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_H, |
| 6915 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6915 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6916 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6916 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6917 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6917 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6918 |
GIR_EraseFromParent, /*InsnID*/0, |
6918 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6919 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6919 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6920 |
// GIR_Coverage, 509, |
6920 |
// GIR_Coverage, 509, |
| 6921 |
GIR_Done, |
6921 |
GIR_Done, |
| 6922 |
// Label 529: @15148 |
6922 |
// Label 529: @15148 |
| 6923 |
GIM_Try, /*On fail goto*//*Label 530*/ 15200, // Rule ID 510 // |
6923 |
GIM_Try, /*On fail goto*//*Label 530*/ 15200, // Rule ID 510 // |
| 6924 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6924 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6925 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_w, |
6925 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_w, |
| 6926 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
6926 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 6927 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
6927 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6928 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
6928 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 6929 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
6929 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 6930 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
6930 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 6931 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
6931 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 6932 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5276:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
6932 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5276:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 6933 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_W, |
6933 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_W, |
| 6934 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6934 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6935 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6935 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6936 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6936 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6937 |
GIR_EraseFromParent, /*InsnID*/0, |
6937 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6938 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6938 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6939 |
// GIR_Coverage, 510, |
6939 |
// GIR_Coverage, 510, |
| 6940 |
GIR_Done, |
6940 |
GIR_Done, |
| 6941 |
// Label 530: @15200 |
6941 |
// Label 530: @15200 |
| 6942 |
GIM_Try, /*On fail goto*//*Label 531*/ 15252, // Rule ID 511 // |
6942 |
GIM_Try, /*On fail goto*//*Label 531*/ 15252, // Rule ID 511 // |
| 6943 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6943 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6944 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_d, |
6944 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_d, |
| 6945 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
6945 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 6946 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
6946 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 6947 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
6947 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 6948 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
6948 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 6949 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
6949 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 6950 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
6950 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 6951 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5274:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
6951 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5274:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 6952 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_D, |
6952 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_D, |
| 6953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6954 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6954 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6955 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6955 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6956 |
GIR_EraseFromParent, /*InsnID*/0, |
6956 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6957 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6957 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6958 |
// GIR_Coverage, 511, |
6958 |
// GIR_Coverage, 511, |
| 6959 |
GIR_Done, |
6959 |
GIR_Done, |
| 6960 |
// Label 531: @15252 |
6960 |
// Label 531: @15252 |
| 6961 |
GIM_Try, /*On fail goto*//*Label 532*/ 15304, // Rule ID 512 // |
6961 |
GIM_Try, /*On fail goto*//*Label 532*/ 15304, // Rule ID 512 // |
| 6962 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6962 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6963 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_b, |
6963 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_b, |
| 6964 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
6964 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 6965 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
6965 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6966 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
6966 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 6967 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
6967 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 6968 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
6968 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 6969 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
6969 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 6970 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5277:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
6970 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5277:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 6971 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_B, |
6971 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_B, |
| 6972 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6972 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6973 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6973 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6974 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6974 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6975 |
GIR_EraseFromParent, /*InsnID*/0, |
6975 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6976 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6976 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6977 |
// GIR_Coverage, 512, |
6977 |
// GIR_Coverage, 512, |
| 6978 |
GIR_Done, |
6978 |
GIR_Done, |
| 6979 |
// Label 532: @15304 |
6979 |
// Label 532: @15304 |
| 6980 |
GIM_Try, /*On fail goto*//*Label 533*/ 15356, // Rule ID 513 // |
6980 |
GIM_Try, /*On fail goto*//*Label 533*/ 15356, // Rule ID 513 // |
| 6981 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
6981 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 6982 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_h, |
6982 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_h, |
| 6983 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
6983 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 6984 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
6984 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6985 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
6985 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 6986 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
6986 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 6987 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
6987 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 6988 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
6988 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 6989 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5279:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
6989 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5279:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 6990 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_H, |
6990 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_H, |
| 6991 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
6991 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 6992 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
6992 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 6993 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
6993 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 6994 |
GIR_EraseFromParent, /*InsnID*/0, |
6994 |
GIR_EraseFromParent, /*InsnID*/0, |
| 6995 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
6995 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 6996 |
// GIR_Coverage, 513, |
6996 |
// GIR_Coverage, 513, |
| 6997 |
GIR_Done, |
6997 |
GIR_Done, |
| 6998 |
// Label 533: @15356 |
6998 |
// Label 533: @15356 |
| 6999 |
GIM_Try, /*On fail goto*//*Label 534*/ 15408, // Rule ID 514 // |
6999 |
GIM_Try, /*On fail goto*//*Label 534*/ 15408, // Rule ID 514 // |
| 7000 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7000 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7001 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_w, |
7001 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_w, |
| 7002 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7002 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7003 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7003 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7004 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7004 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7005 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7005 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7006 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7006 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7007 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7007 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7008 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5280:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
7008 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5280:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 7009 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_W, |
7009 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_W, |
| 7010 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7010 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7011 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7011 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7012 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7012 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7013 |
GIR_EraseFromParent, /*InsnID*/0, |
7013 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7014 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7014 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7015 |
// GIR_Coverage, 514, |
7015 |
// GIR_Coverage, 514, |
| 7016 |
GIR_Done, |
7016 |
GIR_Done, |
| 7017 |
// Label 534: @15408 |
7017 |
// Label 534: @15408 |
| 7018 |
GIM_Try, /*On fail goto*//*Label 535*/ 15460, // Rule ID 515 // |
7018 |
GIM_Try, /*On fail goto*//*Label 535*/ 15460, // Rule ID 515 // |
| 7019 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7019 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7020 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_d, |
7020 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_d, |
| 7021 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7021 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7022 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7022 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7023 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7023 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7024 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7024 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7025 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7025 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7026 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7026 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7027 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5278:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
7027 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5278:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 7028 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_D, |
7028 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_D, |
| 7029 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7029 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7030 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7030 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7031 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7031 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7032 |
GIR_EraseFromParent, /*InsnID*/0, |
7032 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7033 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7033 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7034 |
// GIR_Coverage, 515, |
7034 |
// GIR_Coverage, 515, |
| 7035 |
GIR_Done, |
7035 |
GIR_Done, |
| 7036 |
// Label 535: @15460 |
7036 |
// Label 535: @15460 |
| 7037 |
GIM_Try, /*On fail goto*//*Label 536*/ 15512, // Rule ID 516 // |
7037 |
GIM_Try, /*On fail goto*//*Label 536*/ 15512, // Rule ID 516 // |
| 7038 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7038 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7039 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_b, |
7039 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_b, |
| 7040 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
7040 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7041 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
7041 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7042 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
7042 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7043 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
7043 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 7044 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
7044 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 7045 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
7045 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 7046 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5281:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
7046 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5281:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 7047 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_B, |
7047 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_B, |
| 7048 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7048 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7049 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7049 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7050 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7050 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7051 |
GIR_EraseFromParent, /*InsnID*/0, |
7051 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7052 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7052 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7053 |
// GIR_Coverage, 516, |
7053 |
// GIR_Coverage, 516, |
| 7054 |
GIR_Done, |
7054 |
GIR_Done, |
| 7055 |
// Label 536: @15512 |
7055 |
// Label 536: @15512 |
| 7056 |
GIM_Try, /*On fail goto*//*Label 537*/ 15564, // Rule ID 517 // |
7056 |
GIM_Try, /*On fail goto*//*Label 537*/ 15564, // Rule ID 517 // |
| 7057 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7057 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7058 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_h, |
7058 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_h, |
| 7059 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
7059 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7060 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
7060 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7061 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
7061 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7062 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
7062 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 7063 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
7063 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 7064 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
7064 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 7065 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5283:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
7065 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5283:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 7066 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_H, |
7066 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_H, |
| 7067 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7067 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7068 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7068 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7069 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7069 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7070 |
GIR_EraseFromParent, /*InsnID*/0, |
7070 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7071 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7071 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7072 |
// GIR_Coverage, 517, |
7072 |
// GIR_Coverage, 517, |
| 7073 |
GIR_Done, |
7073 |
GIR_Done, |
| 7074 |
// Label 537: @15564 |
7074 |
// Label 537: @15564 |
| 7075 |
GIM_Try, /*On fail goto*//*Label 538*/ 15616, // Rule ID 518 // |
7075 |
GIM_Try, /*On fail goto*//*Label 538*/ 15616, // Rule ID 518 // |
| 7076 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7076 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7077 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_w, |
7077 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_w, |
| 7078 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7078 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7079 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7079 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7080 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7080 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7081 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7081 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7083 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7083 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7084 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5284:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
7084 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5284:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 7085 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_W, |
7085 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_W, |
| 7086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7087 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7087 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7088 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7088 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7089 |
GIR_EraseFromParent, /*InsnID*/0, |
7089 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7090 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7090 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7091 |
// GIR_Coverage, 518, |
7091 |
// GIR_Coverage, 518, |
| 7092 |
GIR_Done, |
7092 |
GIR_Done, |
| 7093 |
// Label 538: @15616 |
7093 |
// Label 538: @15616 |
| 7094 |
GIM_Try, /*On fail goto*//*Label 539*/ 15668, // Rule ID 519 // |
7094 |
GIM_Try, /*On fail goto*//*Label 539*/ 15668, // Rule ID 519 // |
| 7095 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7095 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7096 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_d, |
7096 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_d, |
| 7097 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7097 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7098 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7098 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7099 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7099 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7100 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7100 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7101 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7101 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7102 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7102 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7103 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5282:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
7103 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5282:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 7104 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_D, |
7104 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_D, |
| 7105 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7105 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7106 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7106 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7107 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7107 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7108 |
GIR_EraseFromParent, /*InsnID*/0, |
7108 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7109 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7109 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7110 |
// GIR_Coverage, 519, |
7110 |
// GIR_Coverage, 519, |
| 7111 |
GIR_Done, |
7111 |
GIR_Done, |
| 7112 |
// Label 539: @15668 |
7112 |
// Label 539: @15668 |
| 7113 |
GIM_Try, /*On fail goto*//*Label 540*/ 15720, // Rule ID 520 // |
7113 |
GIM_Try, /*On fail goto*//*Label 540*/ 15720, // Rule ID 520 // |
| 7114 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7114 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7115 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_b, |
7115 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_b, |
| 7116 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
7116 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7117 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
7117 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7118 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
7118 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7119 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
7119 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 7120 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
7120 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 7121 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
7121 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 7122 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5285:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
7122 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5285:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 7123 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_B, |
7123 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_B, |
| 7124 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7124 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7125 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7125 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7126 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7126 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7127 |
GIR_EraseFromParent, /*InsnID*/0, |
7127 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7128 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7128 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7129 |
// GIR_Coverage, 520, |
7129 |
// GIR_Coverage, 520, |
| 7130 |
GIR_Done, |
7130 |
GIR_Done, |
| 7131 |
// Label 540: @15720 |
7131 |
// Label 540: @15720 |
| 7132 |
GIM_Try, /*On fail goto*//*Label 541*/ 15772, // Rule ID 521 // |
7132 |
GIM_Try, /*On fail goto*//*Label 541*/ 15772, // Rule ID 521 // |
| 7133 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7133 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7134 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_h, |
7134 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_h, |
| 7135 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
7135 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7136 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
7136 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7137 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
7137 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7138 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
7138 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 7139 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
7139 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 7140 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
7140 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 7141 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5287:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
7141 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5287:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 7142 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_H, |
7142 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_H, |
| 7143 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7143 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7144 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7144 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7145 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7145 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7146 |
GIR_EraseFromParent, /*InsnID*/0, |
7146 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7147 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7147 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7148 |
// GIR_Coverage, 521, |
7148 |
// GIR_Coverage, 521, |
| 7149 |
GIR_Done, |
7149 |
GIR_Done, |
| 7150 |
// Label 541: @15772 |
7150 |
// Label 541: @15772 |
| 7151 |
GIM_Try, /*On fail goto*//*Label 542*/ 15824, // Rule ID 522 // |
7151 |
GIM_Try, /*On fail goto*//*Label 542*/ 15824, // Rule ID 522 // |
| 7152 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7152 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7153 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_w, |
7153 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_w, |
| 7154 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7154 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7155 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7155 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7156 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7156 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7157 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7157 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7158 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7158 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7159 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7159 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7160 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5288:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
7160 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5288:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 7161 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_W, |
7161 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_W, |
| 7162 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7162 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7163 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7163 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7164 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7164 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7165 |
GIR_EraseFromParent, /*InsnID*/0, |
7165 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7166 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7166 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7167 |
// GIR_Coverage, 522, |
7167 |
// GIR_Coverage, 522, |
| 7168 |
GIR_Done, |
7168 |
GIR_Done, |
| 7169 |
// Label 542: @15824 |
7169 |
// Label 542: @15824 |
| 7170 |
GIM_Try, /*On fail goto*//*Label 543*/ 15876, // Rule ID 523 // |
7170 |
GIM_Try, /*On fail goto*//*Label 543*/ 15876, // Rule ID 523 // |
| 7171 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7171 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7172 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_d, |
7172 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_d, |
| 7173 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7173 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7174 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7174 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7175 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7175 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7176 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7176 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7177 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7177 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7178 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7178 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7179 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5286:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
7179 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5286:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 7180 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_D, |
7180 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_D, |
| 7181 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7181 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7182 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7182 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7183 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7183 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7184 |
GIR_EraseFromParent, /*InsnID*/0, |
7184 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7185 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7185 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7186 |
// GIR_Coverage, 523, |
7186 |
// GIR_Coverage, 523, |
| 7187 |
GIR_Done, |
7187 |
GIR_Done, |
| 7188 |
// Label 543: @15876 |
7188 |
// Label 543: @15876 |
| 7189 |
GIM_Try, /*On fail goto*//*Label 544*/ 15928, // Rule ID 524 // |
7189 |
GIM_Try, /*On fail goto*//*Label 544*/ 15928, // Rule ID 524 // |
| 7190 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7190 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7191 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_b, |
7191 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_b, |
| 7192 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
7192 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7193 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
7193 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7194 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
7194 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7195 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
7195 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 7196 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
7196 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 7197 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
7197 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 7198 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5289:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
7198 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5289:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 7199 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_B, |
7199 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_B, |
| 7200 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7200 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7201 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7201 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7202 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7202 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7203 |
GIR_EraseFromParent, /*InsnID*/0, |
7203 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7204 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7204 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7205 |
// GIR_Coverage, 524, |
7205 |
// GIR_Coverage, 524, |
| 7206 |
GIR_Done, |
7206 |
GIR_Done, |
| 7207 |
// Label 544: @15928 |
7207 |
// Label 544: @15928 |
| 7208 |
GIM_Try, /*On fail goto*//*Label 545*/ 15980, // Rule ID 525 // |
7208 |
GIM_Try, /*On fail goto*//*Label 545*/ 15980, // Rule ID 525 // |
| 7209 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7209 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7210 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_h, |
7210 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_h, |
| 7211 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
7211 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7212 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
7212 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7213 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
7213 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7214 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
7214 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 7215 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
7215 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 7216 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
7216 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 7217 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5291:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
7217 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5291:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 7218 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_H, |
7218 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_H, |
| 7219 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7219 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7220 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7220 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7221 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7221 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7222 |
GIR_EraseFromParent, /*InsnID*/0, |
7222 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7223 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7223 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7224 |
// GIR_Coverage, 525, |
7224 |
// GIR_Coverage, 525, |
| 7225 |
GIR_Done, |
7225 |
GIR_Done, |
| 7226 |
// Label 545: @15980 |
7226 |
// Label 545: @15980 |
| 7227 |
GIM_Try, /*On fail goto*//*Label 546*/ 16032, // Rule ID 526 // |
7227 |
GIM_Try, /*On fail goto*//*Label 546*/ 16032, // Rule ID 526 // |
| 7228 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7228 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7229 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_w, |
7229 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_w, |
| 7230 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7230 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7231 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7231 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7232 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7232 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7233 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7233 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7235 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7235 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7236 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5292:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
7236 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5292:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 7237 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_W, |
7237 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_W, |
| 7238 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7238 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7239 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7239 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7240 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7240 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7241 |
GIR_EraseFromParent, /*InsnID*/0, |
7241 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7242 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7242 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7243 |
// GIR_Coverage, 526, |
7243 |
// GIR_Coverage, 526, |
| 7244 |
GIR_Done, |
7244 |
GIR_Done, |
| 7245 |
// Label 546: @16032 |
7245 |
// Label 546: @16032 |
| 7246 |
GIM_Try, /*On fail goto*//*Label 547*/ 16084, // Rule ID 527 // |
7246 |
GIM_Try, /*On fail goto*//*Label 547*/ 16084, // Rule ID 527 // |
| 7247 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7247 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7248 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_d, |
7248 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_d, |
| 7249 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7249 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7250 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7250 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7251 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7251 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7252 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7252 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7253 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7253 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7254 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7254 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7255 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5290:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
7255 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5290:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 7256 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_D, |
7256 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_D, |
| 7257 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7257 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7258 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7258 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7259 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7259 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7260 |
GIR_EraseFromParent, /*InsnID*/0, |
7260 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7261 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7261 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7262 |
// GIR_Coverage, 527, |
7262 |
// GIR_Coverage, 527, |
| 7263 |
GIR_Done, |
7263 |
GIR_Done, |
| 7264 |
// Label 547: @16084 |
7264 |
// Label 547: @16084 |
| 7265 |
GIM_Try, /*On fail goto*//*Label 548*/ 16136, // Rule ID 528 // |
7265 |
GIM_Try, /*On fail goto*//*Label 548*/ 16136, // Rule ID 528 // |
| 7266 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7266 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7267 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_b, |
7267 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_b, |
| 7268 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
7268 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 7269 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
7269 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7270 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
7270 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7271 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
7271 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 7272 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
7272 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 7273 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
7273 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 7274 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5293:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
7274 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5293:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 7275 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_B, |
7275 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_B, |
| 7276 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7276 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7277 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7277 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7278 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7278 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7279 |
GIR_EraseFromParent, /*InsnID*/0, |
7279 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7280 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7280 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7281 |
// GIR_Coverage, 528, |
7281 |
// GIR_Coverage, 528, |
| 7282 |
GIR_Done, |
7282 |
GIR_Done, |
| 7283 |
// Label 548: @16136 |
7283 |
// Label 548: @16136 |
| 7284 |
GIM_Try, /*On fail goto*//*Label 549*/ 16188, // Rule ID 529 // |
7284 |
GIM_Try, /*On fail goto*//*Label 549*/ 16188, // Rule ID 529 // |
| 7285 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7285 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7286 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_h, |
7286 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_h, |
| 7287 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
7287 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7288 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
7288 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7289 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
7289 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7290 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
7290 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 7291 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
7291 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 7292 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
7292 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 7293 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5295:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
7293 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5295:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 7294 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_H, |
7294 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_H, |
| 7295 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7295 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7296 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7296 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7297 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7297 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7298 |
GIR_EraseFromParent, /*InsnID*/0, |
7298 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7299 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7299 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7300 |
// GIR_Coverage, 529, |
7300 |
// GIR_Coverage, 529, |
| 7301 |
GIR_Done, |
7301 |
GIR_Done, |
| 7302 |
// Label 549: @16188 |
7302 |
// Label 549: @16188 |
| 7303 |
GIM_Try, /*On fail goto*//*Label 550*/ 16240, // Rule ID 530 // |
7303 |
GIM_Try, /*On fail goto*//*Label 550*/ 16240, // Rule ID 530 // |
| 7304 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7304 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7305 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_w, |
7305 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_w, |
| 7306 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7306 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7307 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7307 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7308 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7308 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7309 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7309 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7310 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7310 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7311 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7311 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7312 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5296:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
7312 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5296:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 7313 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_W, |
7313 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_W, |
| 7314 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7314 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7315 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7315 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7316 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7316 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7317 |
GIR_EraseFromParent, /*InsnID*/0, |
7317 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7318 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7318 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7319 |
// GIR_Coverage, 530, |
7319 |
// GIR_Coverage, 530, |
| 7320 |
GIR_Done, |
7320 |
GIR_Done, |
| 7321 |
// Label 550: @16240 |
7321 |
// Label 550: @16240 |
| 7322 |
GIM_Try, /*On fail goto*//*Label 551*/ 16292, // Rule ID 531 // |
7322 |
GIM_Try, /*On fail goto*//*Label 551*/ 16292, // Rule ID 531 // |
| 7323 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7323 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7324 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_d, |
7324 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_d, |
| 7325 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7325 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7326 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7326 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7327 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7327 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7328 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7328 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7329 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7329 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7330 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7330 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7331 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5294:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
7331 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5294:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 7332 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_D, |
7332 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_D, |
| 7333 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7333 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7334 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7334 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7335 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7335 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7336 |
GIR_EraseFromParent, /*InsnID*/0, |
7336 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7337 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7337 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7338 |
// GIR_Coverage, 531, |
7338 |
// GIR_Coverage, 531, |
| 7339 |
GIR_Done, |
7339 |
GIR_Done, |
| 7340 |
// Label 551: @16292 |
7340 |
// Label 551: @16292 |
| 7341 |
GIM_Try, /*On fail goto*//*Label 552*/ 16344, // Rule ID 640 // |
7341 |
GIM_Try, /*On fail goto*//*Label 552*/ 16344, // Rule ID 640 // |
| 7342 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7342 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7343 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_h, |
7343 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_h, |
| 7344 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
7344 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7345 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
7345 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7346 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
7346 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7347 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
7347 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 7348 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
7348 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 7349 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
7349 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 7350 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5428:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
7350 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5428:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 7351 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_H, |
7351 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_H, |
| 7352 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7352 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7353 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7353 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7354 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7354 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7355 |
GIR_EraseFromParent, /*InsnID*/0, |
7355 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7356 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7356 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7357 |
// GIR_Coverage, 640, |
7357 |
// GIR_Coverage, 640, |
| 7358 |
GIR_Done, |
7358 |
GIR_Done, |
| 7359 |
// Label 552: @16344 |
7359 |
// Label 552: @16344 |
| 7360 |
GIM_Try, /*On fail goto*//*Label 553*/ 16396, // Rule ID 641 // |
7360 |
GIM_Try, /*On fail goto*//*Label 553*/ 16396, // Rule ID 641 // |
| 7361 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7361 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7362 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_w, |
7362 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_w, |
| 7363 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7363 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7364 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
7364 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7365 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
7365 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7366 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7366 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7367 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
7367 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 7368 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
7368 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 7369 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5429:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
7369 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5429:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 7370 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_W, |
7370 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_W, |
| 7371 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7371 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7372 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7372 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7373 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7373 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7374 |
GIR_EraseFromParent, /*InsnID*/0, |
7374 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7375 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7375 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7376 |
// GIR_Coverage, 641, |
7376 |
// GIR_Coverage, 641, |
| 7377 |
GIR_Done, |
7377 |
GIR_Done, |
| 7378 |
// Label 553: @16396 |
7378 |
// Label 553: @16396 |
| 7379 |
GIM_Try, /*On fail goto*//*Label 554*/ 16448, // Rule ID 642 // |
7379 |
GIM_Try, /*On fail goto*//*Label 554*/ 16448, // Rule ID 642 // |
| 7380 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7380 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7381 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_d, |
7381 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_d, |
| 7382 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7382 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7383 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7383 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7384 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7384 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7385 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7385 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7386 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7386 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7387 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7387 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7388 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5427:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
7388 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5427:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 7389 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_D, |
7389 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_D, |
| 7390 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7390 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7391 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7391 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7392 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7392 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7393 |
GIR_EraseFromParent, /*InsnID*/0, |
7393 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7394 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7394 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7395 |
// GIR_Coverage, 642, |
7395 |
// GIR_Coverage, 642, |
| 7396 |
GIR_Done, |
7396 |
GIR_Done, |
| 7397 |
// Label 554: @16448 |
7397 |
// Label 554: @16448 |
| 7398 |
GIM_Try, /*On fail goto*//*Label 555*/ 16500, // Rule ID 643 // |
7398 |
GIM_Try, /*On fail goto*//*Label 555*/ 16500, // Rule ID 643 // |
| 7399 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7399 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7400 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_h, |
7400 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_h, |
| 7401 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
7401 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7402 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
7402 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7403 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
7403 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 7404 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
7404 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 7405 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
7405 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 7406 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
7406 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 7407 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5431:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
7407 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5431:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 7408 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_H, |
7408 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_H, |
| 7409 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7409 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7410 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7410 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7411 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7411 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7412 |
GIR_EraseFromParent, /*InsnID*/0, |
7412 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7413 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7413 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7414 |
// GIR_Coverage, 643, |
7414 |
// GIR_Coverage, 643, |
| 7415 |
GIR_Done, |
7415 |
GIR_Done, |
| 7416 |
// Label 555: @16500 |
7416 |
// Label 555: @16500 |
| 7417 |
GIM_Try, /*On fail goto*//*Label 556*/ 16552, // Rule ID 644 // |
7417 |
GIM_Try, /*On fail goto*//*Label 556*/ 16552, // Rule ID 644 // |
| 7418 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7418 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7419 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_w, |
7419 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_w, |
| 7420 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7420 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7421 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
7421 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7422 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
7422 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 7423 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7423 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7424 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
7424 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 7425 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
7425 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 7426 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5432:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
7426 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5432:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 7427 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_W, |
7427 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_W, |
| 7428 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7428 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7429 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7429 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7430 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7430 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7431 |
GIR_EraseFromParent, /*InsnID*/0, |
7431 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7432 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7432 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7433 |
// GIR_Coverage, 644, |
7433 |
// GIR_Coverage, 644, |
| 7434 |
GIR_Done, |
7434 |
GIR_Done, |
| 7435 |
// Label 556: @16552 |
7435 |
// Label 556: @16552 |
| 7436 |
GIM_Try, /*On fail goto*//*Label 557*/ 16604, // Rule ID 645 // |
7436 |
GIM_Try, /*On fail goto*//*Label 557*/ 16604, // Rule ID 645 // |
| 7437 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7437 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7438 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_d, |
7438 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_d, |
| 7439 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7439 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7440 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7440 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7441 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7441 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7442 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7442 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7443 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7443 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7444 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7444 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7445 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5430:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
7445 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5430:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 7446 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_D, |
7446 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_D, |
| 7447 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7447 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7448 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7448 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7449 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7449 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7450 |
GIR_EraseFromParent, /*InsnID*/0, |
7450 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7451 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7451 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7452 |
// GIR_Coverage, 645, |
7452 |
// GIR_Coverage, 645, |
| 7453 |
GIR_Done, |
7453 |
GIR_Done, |
| 7454 |
// Label 557: @16604 |
7454 |
// Label 557: @16604 |
| 7455 |
GIM_Try, /*On fail goto*//*Label 558*/ 16656, // Rule ID 660 // |
7455 |
GIM_Try, /*On fail goto*//*Label 558*/ 16656, // Rule ID 660 // |
| 7456 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7456 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7457 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_w, |
7457 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_w, |
| 7458 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7458 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7459 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7459 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7460 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7460 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7461 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7461 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7462 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7462 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7463 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7463 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7464 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5470:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7464 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5470:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7465 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_W, |
7465 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_W, |
| 7466 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7466 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7467 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7467 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7468 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7468 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7469 |
GIR_EraseFromParent, /*InsnID*/0, |
7469 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7470 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7470 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7471 |
// GIR_Coverage, 660, |
7471 |
// GIR_Coverage, 660, |
| 7472 |
GIR_Done, |
7472 |
GIR_Done, |
| 7473 |
// Label 558: @16656 |
7473 |
// Label 558: @16656 |
| 7474 |
GIM_Try, /*On fail goto*//*Label 559*/ 16708, // Rule ID 661 // |
7474 |
GIM_Try, /*On fail goto*//*Label 559*/ 16708, // Rule ID 661 // |
| 7475 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7475 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7476 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_d, |
7476 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_d, |
| 7477 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7477 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7478 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7478 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7479 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7479 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7480 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7480 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7481 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7481 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7482 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7482 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7483 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5469:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7483 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5469:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7484 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_D, |
7484 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_D, |
| 7485 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7485 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7486 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7486 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7487 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7487 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7488 |
GIR_EraseFromParent, /*InsnID*/0, |
7488 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7489 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7489 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7490 |
// GIR_Coverage, 661, |
7490 |
// GIR_Coverage, 661, |
| 7491 |
GIR_Done, |
7491 |
GIR_Done, |
| 7492 |
// Label 559: @16708 |
7492 |
// Label 559: @16708 |
| 7493 |
GIM_Try, /*On fail goto*//*Label 560*/ 16760, // Rule ID 686 // |
7493 |
GIM_Try, /*On fail goto*//*Label 560*/ 16760, // Rule ID 686 // |
| 7494 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7494 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7495 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_h, |
7495 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_h, |
| 7496 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
7496 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 7497 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7497 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7498 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7498 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7499 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
7499 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 7500 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7500 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7501 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7501 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7502 |
// (intrinsic_wo_chain:{ *:[v8f16] } 5495:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7502 |
// (intrinsic_wo_chain:{ *:[v8f16] } 5495:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7503 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_H, |
7503 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_H, |
| 7504 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7504 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7505 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7505 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7506 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7506 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7507 |
GIR_EraseFromParent, /*InsnID*/0, |
7507 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7508 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7508 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7509 |
// GIR_Coverage, 686, |
7509 |
// GIR_Coverage, 686, |
| 7510 |
GIR_Done, |
7510 |
GIR_Done, |
| 7511 |
// Label 560: @16760 |
7511 |
// Label 560: @16760 |
| 7512 |
GIM_Try, /*On fail goto*//*Label 561*/ 16812, // Rule ID 687 // |
7512 |
GIM_Try, /*On fail goto*//*Label 561*/ 16812, // Rule ID 687 // |
| 7513 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7513 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7514 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_w, |
7514 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_w, |
| 7515 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7515 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7516 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7516 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7517 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7517 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7518 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7518 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7519 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7519 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7520 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7520 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7521 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5496:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7521 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5496:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7522 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_W, |
7522 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_W, |
| 7523 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7523 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7524 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7524 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7525 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7525 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7526 |
GIR_EraseFromParent, /*InsnID*/0, |
7526 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7527 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7527 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7528 |
// GIR_Coverage, 687, |
7528 |
// GIR_Coverage, 687, |
| 7529 |
GIR_Done, |
7529 |
GIR_Done, |
| 7530 |
// Label 561: @16812 |
7530 |
// Label 561: @16812 |
| 7531 |
GIM_Try, /*On fail goto*//*Label 562*/ 16864, // Rule ID 714 // |
7531 |
GIM_Try, /*On fail goto*//*Label 562*/ 16864, // Rule ID 714 // |
| 7532 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7532 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7533 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_w, |
7533 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_w, |
| 7534 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7534 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7535 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7535 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7536 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7536 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7537 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7537 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7538 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7538 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7539 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7539 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7540 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5522:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7540 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5522:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7541 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_W, |
7541 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_W, |
| 7542 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7542 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7543 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7543 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7544 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7544 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7545 |
GIR_EraseFromParent, /*InsnID*/0, |
7545 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7546 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7546 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7547 |
// GIR_Coverage, 714, |
7547 |
// GIR_Coverage, 714, |
| 7548 |
GIR_Done, |
7548 |
GIR_Done, |
| 7549 |
// Label 562: @16864 |
7549 |
// Label 562: @16864 |
| 7550 |
GIM_Try, /*On fail goto*//*Label 563*/ 16916, // Rule ID 715 // |
7550 |
GIM_Try, /*On fail goto*//*Label 563*/ 16916, // Rule ID 715 // |
| 7551 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7551 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7552 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_d, |
7552 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_d, |
| 7553 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7553 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7554 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7554 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7555 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7555 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7556 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7556 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7557 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7557 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7558 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7558 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7559 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5521:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7559 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5521:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7560 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_D, |
7560 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_D, |
| 7561 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7561 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7562 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7562 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7563 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7563 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7564 |
GIR_EraseFromParent, /*InsnID*/0, |
7564 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7565 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7565 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7566 |
// GIR_Coverage, 715, |
7566 |
// GIR_Coverage, 715, |
| 7567 |
GIR_Done, |
7567 |
GIR_Done, |
| 7568 |
// Label 563: @16916 |
7568 |
// Label 563: @16916 |
| 7569 |
GIM_Try, /*On fail goto*//*Label 564*/ 16968, // Rule ID 716 // |
7569 |
GIM_Try, /*On fail goto*//*Label 564*/ 16968, // Rule ID 716 // |
| 7570 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7570 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7571 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_w, |
7571 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_w, |
| 7572 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7572 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7573 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7573 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7574 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7574 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7575 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7575 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7576 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7576 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7577 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7577 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7578 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5520:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7578 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5520:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7579 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_W, |
7579 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_W, |
| 7580 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7580 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7581 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7581 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7582 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7582 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7583 |
GIR_EraseFromParent, /*InsnID*/0, |
7583 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7584 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7584 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7585 |
// GIR_Coverage, 716, |
7585 |
// GIR_Coverage, 716, |
| 7586 |
GIR_Done, |
7586 |
GIR_Done, |
| 7587 |
// Label 564: @16968 |
7587 |
// Label 564: @16968 |
| 7588 |
GIM_Try, /*On fail goto*//*Label 565*/ 17020, // Rule ID 717 // |
7588 |
GIM_Try, /*On fail goto*//*Label 565*/ 17020, // Rule ID 717 // |
| 7589 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7589 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7590 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_d, |
7590 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_d, |
| 7591 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7591 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7592 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7592 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7593 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7593 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7594 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7594 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7595 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7595 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7596 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7596 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7597 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5519:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7597 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5519:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7598 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_D, |
7598 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_D, |
| 7599 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7599 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7600 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7600 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7601 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7601 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7602 |
GIR_EraseFromParent, /*InsnID*/0, |
7602 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7603 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7603 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7604 |
// GIR_Coverage, 717, |
7604 |
// GIR_Coverage, 717, |
| 7605 |
GIR_Done, |
7605 |
GIR_Done, |
| 7606 |
// Label 565: @17020 |
7606 |
// Label 565: @17020 |
| 7607 |
GIM_Try, /*On fail goto*//*Label 566*/ 17072, // Rule ID 718 // |
7607 |
GIM_Try, /*On fail goto*//*Label 566*/ 17072, // Rule ID 718 // |
| 7608 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7608 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7609 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_w, |
7609 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_w, |
| 7610 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7610 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7611 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7611 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7612 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7612 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7613 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7613 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7614 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7614 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7615 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7615 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7616 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5526:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7616 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5526:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7617 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_W, |
7617 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_W, |
| 7618 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7618 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7619 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7619 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7620 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7620 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7621 |
GIR_EraseFromParent, /*InsnID*/0, |
7621 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7622 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7622 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7623 |
// GIR_Coverage, 718, |
7623 |
// GIR_Coverage, 718, |
| 7624 |
GIR_Done, |
7624 |
GIR_Done, |
| 7625 |
// Label 566: @17072 |
7625 |
// Label 566: @17072 |
| 7626 |
GIM_Try, /*On fail goto*//*Label 567*/ 17124, // Rule ID 719 // |
7626 |
GIM_Try, /*On fail goto*//*Label 567*/ 17124, // Rule ID 719 // |
| 7627 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7627 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7628 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_d, |
7628 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_d, |
| 7629 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7629 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7630 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7630 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7631 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7631 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7632 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7632 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7633 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7633 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7634 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7634 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7635 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5525:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7635 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5525:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7636 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_D, |
7636 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_D, |
| 7637 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7637 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7638 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7638 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7639 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7639 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7640 |
GIR_EraseFromParent, /*InsnID*/0, |
7640 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7641 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7641 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7642 |
// GIR_Coverage, 719, |
7642 |
// GIR_Coverage, 719, |
| 7643 |
GIR_Done, |
7643 |
GIR_Done, |
| 7644 |
// Label 567: @17124 |
7644 |
// Label 567: @17124 |
| 7645 |
GIM_Try, /*On fail goto*//*Label 568*/ 17176, // Rule ID 720 // |
7645 |
GIM_Try, /*On fail goto*//*Label 568*/ 17176, // Rule ID 720 // |
| 7646 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7646 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7647 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_w, |
7647 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_w, |
| 7648 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7648 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7649 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7649 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7650 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7650 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7651 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7651 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7652 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7652 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7653 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7653 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7654 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5524:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7654 |
// (intrinsic_wo_chain:{ *:[v4f32] } 5524:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7655 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_W, |
7655 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_W, |
| 7656 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7656 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7657 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7657 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7658 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7658 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7659 |
GIR_EraseFromParent, /*InsnID*/0, |
7659 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7660 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7660 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7661 |
// GIR_Coverage, 720, |
7661 |
// GIR_Coverage, 720, |
| 7662 |
GIR_Done, |
7662 |
GIR_Done, |
| 7663 |
// Label 568: @17176 |
7663 |
// Label 568: @17176 |
| 7664 |
GIM_Try, /*On fail goto*//*Label 569*/ 17228, // Rule ID 721 // |
7664 |
GIM_Try, /*On fail goto*//*Label 569*/ 17228, // Rule ID 721 // |
| 7665 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7665 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7666 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_d, |
7666 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_d, |
| 7667 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7667 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7668 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7668 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7669 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7669 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7670 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7670 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7671 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7671 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7672 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7672 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7673 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5523:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7673 |
// (intrinsic_wo_chain:{ *:[v2f64] } 5523:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7674 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_D, |
7674 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_D, |
| 7675 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7675 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7676 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7676 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7677 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7677 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7678 |
GIR_EraseFromParent, /*InsnID*/0, |
7678 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7679 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7679 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7680 |
// GIR_Coverage, 721, |
7680 |
// GIR_Coverage, 721, |
| 7681 |
GIR_Done, |
7681 |
GIR_Done, |
| 7682 |
// Label 569: @17228 |
7682 |
// Label 569: @17228 |
| 7683 |
GIM_Try, /*On fail goto*//*Label 570*/ 17280, // Rule ID 732 // |
7683 |
GIM_Try, /*On fail goto*//*Label 570*/ 17280, // Rule ID 732 // |
| 7684 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7684 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7685 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_w, |
7685 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_w, |
| 7686 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7686 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7687 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7687 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7688 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7688 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7689 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7689 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7690 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7690 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7691 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7691 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7692 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5538:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7692 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5538:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7693 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_W, |
7693 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_W, |
| 7694 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7694 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7695 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7695 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7696 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7696 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7697 |
GIR_EraseFromParent, /*InsnID*/0, |
7697 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7698 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7698 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7699 |
// GIR_Coverage, 732, |
7699 |
// GIR_Coverage, 732, |
| 7700 |
GIR_Done, |
7700 |
GIR_Done, |
| 7701 |
// Label 570: @17280 |
7701 |
// Label 570: @17280 |
| 7702 |
GIM_Try, /*On fail goto*//*Label 571*/ 17332, // Rule ID 733 // |
7702 |
GIM_Try, /*On fail goto*//*Label 571*/ 17332, // Rule ID 733 // |
| 7703 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7703 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7704 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_d, |
7704 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_d, |
| 7705 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7705 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7706 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7706 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7707 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7707 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7708 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7708 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7709 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7709 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7710 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7710 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7711 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5537:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7711 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5537:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7712 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_D, |
7712 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_D, |
| 7713 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7713 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7714 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7714 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7715 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7715 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7716 |
GIR_EraseFromParent, /*InsnID*/0, |
7716 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7717 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7717 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7718 |
// GIR_Coverage, 733, |
7718 |
// GIR_Coverage, 733, |
| 7719 |
GIR_Done, |
7719 |
GIR_Done, |
| 7720 |
// Label 571: @17332 |
7720 |
// Label 571: @17332 |
| 7721 |
GIM_Try, /*On fail goto*//*Label 572*/ 17384, // Rule ID 734 // |
7721 |
GIM_Try, /*On fail goto*//*Label 572*/ 17384, // Rule ID 734 // |
| 7722 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7722 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7723 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_w, |
7723 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_w, |
| 7724 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7724 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7725 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7725 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7726 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7726 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7727 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7727 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7728 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7728 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7729 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7729 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7730 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5540:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7730 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5540:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7731 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_W, |
7731 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_W, |
| 7732 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7732 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7733 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7733 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7734 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7734 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7735 |
GIR_EraseFromParent, /*InsnID*/0, |
7735 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7736 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7736 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7737 |
// GIR_Coverage, 734, |
7737 |
// GIR_Coverage, 734, |
| 7738 |
GIR_Done, |
7738 |
GIR_Done, |
| 7739 |
// Label 572: @17384 |
7739 |
// Label 572: @17384 |
| 7740 |
GIM_Try, /*On fail goto*//*Label 573*/ 17436, // Rule ID 735 // |
7740 |
GIM_Try, /*On fail goto*//*Label 573*/ 17436, // Rule ID 735 // |
| 7741 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7741 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7742 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_d, |
7742 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_d, |
| 7743 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7743 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7744 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7744 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7745 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7745 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7746 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7746 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7747 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7747 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7748 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7748 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7749 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5539:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7749 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5539:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7750 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_D, |
7750 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_D, |
| 7751 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7751 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7752 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7752 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7753 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7753 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7754 |
GIR_EraseFromParent, /*InsnID*/0, |
7754 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7755 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7755 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7756 |
// GIR_Coverage, 735, |
7756 |
// GIR_Coverage, 735, |
| 7757 |
GIR_Done, |
7757 |
GIR_Done, |
| 7758 |
// Label 573: @17436 |
7758 |
// Label 573: @17436 |
| 7759 |
GIM_Try, /*On fail goto*//*Label 574*/ 17488, // Rule ID 736 // |
7759 |
GIM_Try, /*On fail goto*//*Label 574*/ 17488, // Rule ID 736 // |
| 7760 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7760 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7761 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_w, |
7761 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_w, |
| 7762 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7762 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7763 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7763 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7764 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7764 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7765 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7765 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7766 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7766 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7767 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7767 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7768 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5542:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7768 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5542:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7769 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_W, |
7769 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_W, |
| 7770 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7770 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7771 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7771 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7772 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7772 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7773 |
GIR_EraseFromParent, /*InsnID*/0, |
7773 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7774 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7774 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7775 |
// GIR_Coverage, 736, |
7775 |
// GIR_Coverage, 736, |
| 7776 |
GIR_Done, |
7776 |
GIR_Done, |
| 7777 |
// Label 574: @17488 |
7777 |
// Label 574: @17488 |
| 7778 |
GIM_Try, /*On fail goto*//*Label 575*/ 17540, // Rule ID 737 // |
7778 |
GIM_Try, /*On fail goto*//*Label 575*/ 17540, // Rule ID 737 // |
| 7779 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7779 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7780 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_d, |
7780 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_d, |
| 7781 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7781 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7782 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7782 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7783 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7783 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7784 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7784 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7785 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7785 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7786 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7786 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7787 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5541:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7787 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5541:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7788 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_D, |
7788 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_D, |
| 7789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7790 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7790 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7791 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7791 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7792 |
GIR_EraseFromParent, /*InsnID*/0, |
7792 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7793 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7793 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7794 |
// GIR_Coverage, 737, |
7794 |
// GIR_Coverage, 737, |
| 7795 |
GIR_Done, |
7795 |
GIR_Done, |
| 7796 |
// Label 575: @17540 |
7796 |
// Label 575: @17540 |
| 7797 |
GIM_Try, /*On fail goto*//*Label 576*/ 17592, // Rule ID 738 // |
7797 |
GIM_Try, /*On fail goto*//*Label 576*/ 17592, // Rule ID 738 // |
| 7798 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7798 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7799 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_w, |
7799 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_w, |
| 7800 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7800 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7801 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7801 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7802 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7802 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7803 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7803 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7804 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7804 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7805 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7805 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7806 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5544:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7806 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5544:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7807 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_W, |
7807 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_W, |
| 7808 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7808 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7809 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7809 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7810 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7810 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7811 |
GIR_EraseFromParent, /*InsnID*/0, |
7811 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7812 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7812 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7813 |
// GIR_Coverage, 738, |
7813 |
// GIR_Coverage, 738, |
| 7814 |
GIR_Done, |
7814 |
GIR_Done, |
| 7815 |
// Label 576: @17592 |
7815 |
// Label 576: @17592 |
| 7816 |
GIM_Try, /*On fail goto*//*Label 577*/ 17644, // Rule ID 739 // |
7816 |
GIM_Try, /*On fail goto*//*Label 577*/ 17644, // Rule ID 739 // |
| 7817 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7817 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7818 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_d, |
7818 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_d, |
| 7819 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7819 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7820 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7820 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7821 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7821 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7822 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7822 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7823 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7823 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7824 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7824 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7825 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5543:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7825 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5543:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7826 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_D, |
7826 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_D, |
| 7827 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7827 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7828 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7828 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7829 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7829 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7830 |
GIR_EraseFromParent, /*InsnID*/0, |
7830 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7831 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7831 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7832 |
// GIR_Coverage, 739, |
7832 |
// GIR_Coverage, 739, |
| 7833 |
GIR_Done, |
7833 |
GIR_Done, |
| 7834 |
// Label 577: @17644 |
7834 |
// Label 577: @17644 |
| 7835 |
GIM_Try, /*On fail goto*//*Label 578*/ 17696, // Rule ID 740 // |
7835 |
GIM_Try, /*On fail goto*//*Label 578*/ 17696, // Rule ID 740 // |
| 7836 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7836 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7837 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_w, |
7837 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_w, |
| 7838 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7838 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7839 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7839 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7840 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7840 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7841 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7841 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7843 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7843 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7844 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5546:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7844 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5546:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7845 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_W, |
7845 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_W, |
| 7846 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7846 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7847 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7847 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7848 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7848 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7849 |
GIR_EraseFromParent, /*InsnID*/0, |
7849 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7850 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7850 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7851 |
// GIR_Coverage, 740, |
7851 |
// GIR_Coverage, 740, |
| 7852 |
GIR_Done, |
7852 |
GIR_Done, |
| 7853 |
// Label 578: @17696 |
7853 |
// Label 578: @17696 |
| 7854 |
GIM_Try, /*On fail goto*//*Label 579*/ 17748, // Rule ID 741 // |
7854 |
GIM_Try, /*On fail goto*//*Label 579*/ 17748, // Rule ID 741 // |
| 7855 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7855 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7856 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_d, |
7856 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_d, |
| 7857 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7857 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7858 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7858 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7859 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7859 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7860 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7860 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7861 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7861 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7862 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7862 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7863 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5545:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7863 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5545:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7864 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_D, |
7864 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_D, |
| 7865 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7865 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7866 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7866 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7867 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7867 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7868 |
GIR_EraseFromParent, /*InsnID*/0, |
7868 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7869 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7869 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7870 |
// GIR_Coverage, 741, |
7870 |
// GIR_Coverage, 741, |
| 7871 |
GIR_Done, |
7871 |
GIR_Done, |
| 7872 |
// Label 579: @17748 |
7872 |
// Label 579: @17748 |
| 7873 |
GIM_Try, /*On fail goto*//*Label 580*/ 17800, // Rule ID 742 // |
7873 |
GIM_Try, /*On fail goto*//*Label 580*/ 17800, // Rule ID 742 // |
| 7874 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7874 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7875 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_w, |
7875 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_w, |
| 7876 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7876 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7877 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7877 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7878 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7878 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7879 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7879 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7880 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7880 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7881 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7881 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7882 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5548:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7882 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5548:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7883 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_W, |
7883 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_W, |
| 7884 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7884 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7885 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7885 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7886 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7886 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7887 |
GIR_EraseFromParent, /*InsnID*/0, |
7887 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7888 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7888 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7889 |
// GIR_Coverage, 742, |
7889 |
// GIR_Coverage, 742, |
| 7890 |
GIR_Done, |
7890 |
GIR_Done, |
| 7891 |
// Label 580: @17800 |
7891 |
// Label 580: @17800 |
| 7892 |
GIM_Try, /*On fail goto*//*Label 581*/ 17852, // Rule ID 743 // |
7892 |
GIM_Try, /*On fail goto*//*Label 581*/ 17852, // Rule ID 743 // |
| 7893 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7893 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7894 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_d, |
7894 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_d, |
| 7895 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7895 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7896 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7896 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7897 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7897 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7898 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7898 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7899 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7899 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7900 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7900 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7901 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5547:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7901 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5547:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7902 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_D, |
7902 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_D, |
| 7903 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7903 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7904 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7904 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7905 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7905 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7906 |
GIR_EraseFromParent, /*InsnID*/0, |
7906 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7907 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7907 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7908 |
// GIR_Coverage, 743, |
7908 |
// GIR_Coverage, 743, |
| 7909 |
GIR_Done, |
7909 |
GIR_Done, |
| 7910 |
// Label 581: @17852 |
7910 |
// Label 581: @17852 |
| 7911 |
GIM_Try, /*On fail goto*//*Label 582*/ 17904, // Rule ID 748 // |
7911 |
GIM_Try, /*On fail goto*//*Label 582*/ 17904, // Rule ID 748 // |
| 7912 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7912 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7913 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_w, |
7913 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_w, |
| 7914 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7914 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7915 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7915 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7916 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7916 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7917 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7917 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7918 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7918 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7919 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7919 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7920 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5554:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7920 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5554:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7921 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_W, |
7921 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_W, |
| 7922 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7922 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7923 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7923 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7924 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7924 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7925 |
GIR_EraseFromParent, /*InsnID*/0, |
7925 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7926 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7926 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7927 |
// GIR_Coverage, 748, |
7927 |
// GIR_Coverage, 748, |
| 7928 |
GIR_Done, |
7928 |
GIR_Done, |
| 7929 |
// Label 582: @17904 |
7929 |
// Label 582: @17904 |
| 7930 |
GIM_Try, /*On fail goto*//*Label 583*/ 17956, // Rule ID 749 // |
7930 |
GIM_Try, /*On fail goto*//*Label 583*/ 17956, // Rule ID 749 // |
| 7931 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7931 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7932 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_d, |
7932 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_d, |
| 7933 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7933 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7934 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7934 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7935 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7935 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7936 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7936 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7937 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7937 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7938 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7938 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7939 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5553:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7939 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5553:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7940 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_D, |
7940 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_D, |
| 7941 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7941 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7942 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7942 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7943 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7943 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7944 |
GIR_EraseFromParent, /*InsnID*/0, |
7944 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7945 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7945 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7946 |
// GIR_Coverage, 749, |
7946 |
// GIR_Coverage, 749, |
| 7947 |
GIR_Done, |
7947 |
GIR_Done, |
| 7948 |
// Label 583: @17956 |
7948 |
// Label 583: @17956 |
| 7949 |
GIM_Try, /*On fail goto*//*Label 584*/ 18008, // Rule ID 750 // |
7949 |
GIM_Try, /*On fail goto*//*Label 584*/ 18008, // Rule ID 750 // |
| 7950 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7950 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7951 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_w, |
7951 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_w, |
| 7952 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7952 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7953 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7953 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7954 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7954 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7955 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7955 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7956 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7956 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7957 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7957 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7958 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5556:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7958 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5556:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7959 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_W, |
7959 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_W, |
| 7960 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7960 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7961 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7961 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7962 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7962 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7963 |
GIR_EraseFromParent, /*InsnID*/0, |
7963 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7964 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7964 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7965 |
// GIR_Coverage, 750, |
7965 |
// GIR_Coverage, 750, |
| 7966 |
GIR_Done, |
7966 |
GIR_Done, |
| 7967 |
// Label 584: @18008 |
7967 |
// Label 584: @18008 |
| 7968 |
GIM_Try, /*On fail goto*//*Label 585*/ 18060, // Rule ID 751 // |
7968 |
GIM_Try, /*On fail goto*//*Label 585*/ 18060, // Rule ID 751 // |
| 7969 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7969 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7970 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_d, |
7970 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_d, |
| 7971 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
7971 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 7972 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
7972 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7973 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
7973 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 7974 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
7974 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 7975 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
7975 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 7976 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
7976 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 7977 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5555:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
7977 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5555:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 7978 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_D, |
7978 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_D, |
| 7979 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7979 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7980 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7980 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 7981 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
7981 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 7982 |
GIR_EraseFromParent, /*InsnID*/0, |
7982 |
GIR_EraseFromParent, /*InsnID*/0, |
| 7983 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
7983 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 7984 |
// GIR_Coverage, 751, |
7984 |
// GIR_Coverage, 751, |
| 7985 |
GIR_Done, |
7985 |
GIR_Done, |
| 7986 |
// Label 585: @18060 |
7986 |
// Label 585: @18060 |
| 7987 |
GIM_Try, /*On fail goto*//*Label 586*/ 18112, // Rule ID 752 // |
7987 |
GIM_Try, /*On fail goto*//*Label 586*/ 18112, // Rule ID 752 // |
| 7988 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
7988 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 7989 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_w, |
7989 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_w, |
| 7990 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
7990 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 7991 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
7991 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7992 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
7992 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 7993 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
7993 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 7994 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
7994 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 7995 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
7995 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 7996 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5558:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
7996 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5558:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 7997 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_W, |
7997 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_W, |
| 7998 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
7998 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 7999 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
7999 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8000 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8000 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8001 |
GIR_EraseFromParent, /*InsnID*/0, |
8001 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8002 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8002 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8003 |
// GIR_Coverage, 752, |
8003 |
// GIR_Coverage, 752, |
| 8004 |
GIR_Done, |
8004 |
GIR_Done, |
| 8005 |
// Label 586: @18112 |
8005 |
// Label 586: @18112 |
| 8006 |
GIM_Try, /*On fail goto*//*Label 587*/ 18164, // Rule ID 753 // |
8006 |
GIM_Try, /*On fail goto*//*Label 587*/ 18164, // Rule ID 753 // |
| 8007 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8007 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8008 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_d, |
8008 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_d, |
| 8009 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8009 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8010 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
8010 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8011 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
8011 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8012 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8012 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8013 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
8013 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 8014 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
8014 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 8015 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5557:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
8015 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5557:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 8016 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_D, |
8016 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_D, |
| 8017 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8017 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8018 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8018 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8019 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8019 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8020 |
GIR_EraseFromParent, /*InsnID*/0, |
8020 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8021 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8021 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8022 |
// GIR_Coverage, 753, |
8022 |
// GIR_Coverage, 753, |
| 8023 |
GIR_Done, |
8023 |
GIR_Done, |
| 8024 |
// Label 587: @18164 |
8024 |
// Label 587: @18164 |
| 8025 |
GIM_Try, /*On fail goto*//*Label 588*/ 18216, // Rule ID 754 // |
8025 |
GIM_Try, /*On fail goto*//*Label 588*/ 18216, // Rule ID 754 // |
| 8026 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8026 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8027 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_w, |
8027 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_w, |
| 8028 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8028 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8029 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8029 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8030 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8030 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8031 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8031 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8032 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8032 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8033 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8033 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8034 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5560:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
8034 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5560:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 8035 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_W, |
8035 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_W, |
| 8036 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8036 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8037 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8037 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8038 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8038 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8039 |
GIR_EraseFromParent, /*InsnID*/0, |
8039 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8040 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8040 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8041 |
// GIR_Coverage, 754, |
8041 |
// GIR_Coverage, 754, |
| 8042 |
GIR_Done, |
8042 |
GIR_Done, |
| 8043 |
// Label 588: @18216 |
8043 |
// Label 588: @18216 |
| 8044 |
GIM_Try, /*On fail goto*//*Label 589*/ 18268, // Rule ID 755 // |
8044 |
GIM_Try, /*On fail goto*//*Label 589*/ 18268, // Rule ID 755 // |
| 8045 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8045 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8046 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_d, |
8046 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_d, |
| 8047 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8047 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8048 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
8048 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8049 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
8049 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8050 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8050 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8051 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
8051 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 8052 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
8052 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 8053 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5559:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
8053 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5559:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 8054 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_D, |
8054 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_D, |
| 8055 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8055 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8056 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8056 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8057 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8057 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8058 |
GIR_EraseFromParent, /*InsnID*/0, |
8058 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8059 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8059 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8060 |
// GIR_Coverage, 755, |
8060 |
// GIR_Coverage, 755, |
| 8061 |
GIR_Done, |
8061 |
GIR_Done, |
| 8062 |
// Label 589: @18268 |
8062 |
// Label 589: @18268 |
| 8063 |
GIM_Try, /*On fail goto*//*Label 590*/ 18320, // Rule ID 756 // |
8063 |
GIM_Try, /*On fail goto*//*Label 590*/ 18320, // Rule ID 756 // |
| 8064 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8064 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8065 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_w, |
8065 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_w, |
| 8066 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8066 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8067 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8067 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8068 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8068 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8069 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8069 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8070 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8070 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8071 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8071 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8072 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5562:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
8072 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5562:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 8073 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_W, |
8073 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_W, |
| 8074 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8074 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8075 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8075 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8076 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8076 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8077 |
GIR_EraseFromParent, /*InsnID*/0, |
8077 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8078 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8078 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8079 |
// GIR_Coverage, 756, |
8079 |
// GIR_Coverage, 756, |
| 8080 |
GIR_Done, |
8080 |
GIR_Done, |
| 8081 |
// Label 590: @18320 |
8081 |
// Label 590: @18320 |
| 8082 |
GIM_Try, /*On fail goto*//*Label 591*/ 18372, // Rule ID 757 // |
8082 |
GIM_Try, /*On fail goto*//*Label 591*/ 18372, // Rule ID 757 // |
| 8083 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8083 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8084 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_d, |
8084 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_d, |
| 8085 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8085 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8086 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
8086 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8087 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
8087 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8088 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8088 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8089 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
8089 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 8090 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
8090 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 8091 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5561:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
8091 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5561:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 8092 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_D, |
8092 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_D, |
| 8093 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8093 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8094 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8094 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8095 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8095 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8096 |
GIR_EraseFromParent, /*InsnID*/0, |
8096 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8097 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8097 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8098 |
// GIR_Coverage, 757, |
8098 |
// GIR_Coverage, 757, |
| 8099 |
GIR_Done, |
8099 |
GIR_Done, |
| 8100 |
// Label 591: @18372 |
8100 |
// Label 591: @18372 |
| 8101 |
GIM_Try, /*On fail goto*//*Label 592*/ 18424, // Rule ID 762 // |
8101 |
GIM_Try, /*On fail goto*//*Label 592*/ 18424, // Rule ID 762 // |
| 8102 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8102 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8103 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_h, |
8103 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_h, |
| 8104 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8104 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8105 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8105 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8106 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8106 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8107 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8107 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8108 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8108 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8109 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8109 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8110 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5567:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
8110 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5567:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 8111 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_H, |
8111 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_H, |
| 8112 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8112 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8113 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8113 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8114 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8114 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8115 |
GIR_EraseFromParent, /*InsnID*/0, |
8115 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8116 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8116 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8117 |
// GIR_Coverage, 762, |
8117 |
// GIR_Coverage, 762, |
| 8118 |
GIR_Done, |
8118 |
GIR_Done, |
| 8119 |
// Label 592: @18424 |
8119 |
// Label 592: @18424 |
| 8120 |
GIM_Try, /*On fail goto*//*Label 593*/ 18476, // Rule ID 763 // |
8120 |
GIM_Try, /*On fail goto*//*Label 593*/ 18476, // Rule ID 763 // |
| 8121 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8121 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8122 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_w, |
8122 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_w, |
| 8123 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8123 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8124 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
8124 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8125 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
8125 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8126 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8126 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8127 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
8127 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 8128 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
8128 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 8129 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5568:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
8129 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5568:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 8130 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_W, |
8130 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_W, |
| 8131 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8131 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8132 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8132 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8133 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8133 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8134 |
GIR_EraseFromParent, /*InsnID*/0, |
8134 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8135 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8135 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8136 |
// GIR_Coverage, 763, |
8136 |
// GIR_Coverage, 763, |
| 8137 |
GIR_Done, |
8137 |
GIR_Done, |
| 8138 |
// Label 593: @18476 |
8138 |
// Label 593: @18476 |
| 8139 |
GIM_Try, /*On fail goto*//*Label 594*/ 18528, // Rule ID 768 // |
8139 |
GIM_Try, /*On fail goto*//*Label 594*/ 18528, // Rule ID 768 // |
| 8140 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8140 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8141 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_h, |
8141 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_h, |
| 8142 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8142 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8143 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
8143 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8144 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
8144 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8145 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8145 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8146 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
8146 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 8147 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
8147 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 8148 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5574:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
8148 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5574:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 8149 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_H, |
8149 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_H, |
| 8150 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8150 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8151 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8151 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8152 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8152 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8153 |
GIR_EraseFromParent, /*InsnID*/0, |
8153 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8154 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8154 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8155 |
// GIR_Coverage, 768, |
8155 |
// GIR_Coverage, 768, |
| 8156 |
GIR_Done, |
8156 |
GIR_Done, |
| 8157 |
// Label 594: @18528 |
8157 |
// Label 594: @18528 |
| 8158 |
GIM_Try, /*On fail goto*//*Label 595*/ 18580, // Rule ID 769 // |
8158 |
GIM_Try, /*On fail goto*//*Label 595*/ 18580, // Rule ID 769 // |
| 8159 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8159 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8160 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_w, |
8160 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_w, |
| 8161 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8161 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8162 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8162 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8163 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8163 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8164 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8164 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8165 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
8165 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 8166 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
8166 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 8167 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5575:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
8167 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5575:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 8168 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_W, |
8168 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_W, |
| 8169 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8169 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8170 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8170 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8171 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8171 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8172 |
GIR_EraseFromParent, /*InsnID*/0, |
8172 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8173 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8173 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8174 |
// GIR_Coverage, 769, |
8174 |
// GIR_Coverage, 769, |
| 8175 |
GIR_Done, |
8175 |
GIR_Done, |
| 8176 |
// Label 595: @18580 |
8176 |
// Label 595: @18580 |
| 8177 |
GIM_Try, /*On fail goto*//*Label 596*/ 18632, // Rule ID 770 // |
8177 |
GIM_Try, /*On fail goto*//*Label 596*/ 18632, // Rule ID 770 // |
| 8178 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8178 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8179 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_d, |
8179 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_d, |
| 8180 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8180 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8181 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8181 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8182 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8182 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8183 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8183 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8184 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8184 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8185 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8185 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8186 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5573:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
8186 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5573:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 8187 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_D, |
8187 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_D, |
| 8188 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8188 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8189 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8189 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8190 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8190 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8191 |
GIR_EraseFromParent, /*InsnID*/0, |
8191 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8192 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8192 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8193 |
// GIR_Coverage, 770, |
8193 |
// GIR_Coverage, 770, |
| 8194 |
GIR_Done, |
8194 |
GIR_Done, |
| 8195 |
// Label 596: @18632 |
8195 |
// Label 596: @18632 |
| 8196 |
GIM_Try, /*On fail goto*//*Label 597*/ 18684, // Rule ID 771 // |
8196 |
GIM_Try, /*On fail goto*//*Label 597*/ 18684, // Rule ID 771 // |
| 8197 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8197 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8198 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_h, |
8198 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_h, |
| 8199 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8199 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8200 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
8200 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8201 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
8201 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8202 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8202 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8203 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
8203 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 8204 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
8204 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 8205 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5577:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
8205 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5577:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 8206 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_H, |
8206 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_H, |
| 8207 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8207 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8208 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8208 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8209 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8209 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8210 |
GIR_EraseFromParent, /*InsnID*/0, |
8210 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8211 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8211 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8212 |
// GIR_Coverage, 771, |
8212 |
// GIR_Coverage, 771, |
| 8213 |
GIR_Done, |
8213 |
GIR_Done, |
| 8214 |
// Label 597: @18684 |
8214 |
// Label 597: @18684 |
| 8215 |
GIM_Try, /*On fail goto*//*Label 598*/ 18736, // Rule ID 772 // |
8215 |
GIM_Try, /*On fail goto*//*Label 598*/ 18736, // Rule ID 772 // |
| 8216 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8216 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8217 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_w, |
8217 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_w, |
| 8218 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8218 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8219 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8219 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8220 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8220 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8221 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8221 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8222 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
8222 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 8223 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
8223 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 8224 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5578:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
8224 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5578:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 8225 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_W, |
8225 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_W, |
| 8226 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8226 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8227 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8227 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8228 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8228 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8229 |
GIR_EraseFromParent, /*InsnID*/0, |
8229 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8230 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8230 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8231 |
// GIR_Coverage, 772, |
8231 |
// GIR_Coverage, 772, |
| 8232 |
GIR_Done, |
8232 |
GIR_Done, |
| 8233 |
// Label 598: @18736 |
8233 |
// Label 598: @18736 |
| 8234 |
GIM_Try, /*On fail goto*//*Label 599*/ 18788, // Rule ID 773 // |
8234 |
GIM_Try, /*On fail goto*//*Label 599*/ 18788, // Rule ID 773 // |
| 8235 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8235 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8236 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_d, |
8236 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_d, |
| 8237 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8237 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8238 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8238 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8239 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8239 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8240 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8240 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8241 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8241 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8242 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8242 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8243 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5576:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
8243 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5576:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 8244 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_D, |
8244 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_D, |
| 8245 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8245 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8246 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8246 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8247 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8247 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8248 |
GIR_EraseFromParent, /*InsnID*/0, |
8248 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8249 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8249 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8250 |
// GIR_Coverage, 773, |
8250 |
// GIR_Coverage, 773, |
| 8251 |
GIR_Done, |
8251 |
GIR_Done, |
| 8252 |
// Label 599: @18788 |
8252 |
// Label 599: @18788 |
| 8253 |
GIM_Try, /*On fail goto*//*Label 600*/ 18840, // Rule ID 774 // |
8253 |
GIM_Try, /*On fail goto*//*Label 600*/ 18840, // Rule ID 774 // |
| 8254 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8254 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8255 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_h, |
8255 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_h, |
| 8256 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8256 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8257 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
8257 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8258 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
8258 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8259 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8259 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8260 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
8260 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 8261 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
8261 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 8262 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5580:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
8262 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5580:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 8263 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_H, |
8263 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_H, |
| 8264 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8264 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8265 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8265 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8266 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8266 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8267 |
GIR_EraseFromParent, /*InsnID*/0, |
8267 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8268 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8268 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8269 |
// GIR_Coverage, 774, |
8269 |
// GIR_Coverage, 774, |
| 8270 |
GIR_Done, |
8270 |
GIR_Done, |
| 8271 |
// Label 600: @18840 |
8271 |
// Label 600: @18840 |
| 8272 |
GIM_Try, /*On fail goto*//*Label 601*/ 18892, // Rule ID 775 // |
8272 |
GIM_Try, /*On fail goto*//*Label 601*/ 18892, // Rule ID 775 // |
| 8273 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8273 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8274 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_w, |
8274 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_w, |
| 8275 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8275 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8276 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8276 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8277 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8277 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
8279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 8280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
8280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 8281 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5581:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
8281 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5581:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 8282 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_W, |
8282 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_W, |
| 8283 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8283 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8284 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8284 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8285 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8285 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8286 |
GIR_EraseFromParent, /*InsnID*/0, |
8286 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8287 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8287 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8288 |
// GIR_Coverage, 775, |
8288 |
// GIR_Coverage, 775, |
| 8289 |
GIR_Done, |
8289 |
GIR_Done, |
| 8290 |
// Label 601: @18892 |
8290 |
// Label 601: @18892 |
| 8291 |
GIM_Try, /*On fail goto*//*Label 602*/ 18944, // Rule ID 776 // |
8291 |
GIM_Try, /*On fail goto*//*Label 602*/ 18944, // Rule ID 776 // |
| 8292 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8292 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8293 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_d, |
8293 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_d, |
| 8294 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8294 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8295 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8295 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8296 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8296 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8297 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8297 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8298 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8298 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8299 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8299 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8300 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5579:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
8300 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5579:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 8301 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_D, |
8301 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_D, |
| 8302 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8302 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8303 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8303 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8304 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8304 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8305 |
GIR_EraseFromParent, /*InsnID*/0, |
8305 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8306 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8306 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8307 |
// GIR_Coverage, 776, |
8307 |
// GIR_Coverage, 776, |
| 8308 |
GIR_Done, |
8308 |
GIR_Done, |
| 8309 |
// Label 602: @18944 |
8309 |
// Label 602: @18944 |
| 8310 |
GIM_Try, /*On fail goto*//*Label 603*/ 18996, // Rule ID 777 // |
8310 |
GIM_Try, /*On fail goto*//*Label 603*/ 18996, // Rule ID 777 // |
| 8311 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8311 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8312 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_h, |
8312 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_h, |
| 8313 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8313 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8314 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
8314 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8315 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
8315 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8316 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8316 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8317 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
8317 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 8318 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
8318 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 8319 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5583:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
8319 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5583:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 8320 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_H, |
8320 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_H, |
| 8321 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8321 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8322 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8322 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8323 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8323 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8324 |
GIR_EraseFromParent, /*InsnID*/0, |
8324 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8325 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8325 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8326 |
// GIR_Coverage, 777, |
8326 |
// GIR_Coverage, 777, |
| 8327 |
GIR_Done, |
8327 |
GIR_Done, |
| 8328 |
// Label 603: @18996 |
8328 |
// Label 603: @18996 |
| 8329 |
GIM_Try, /*On fail goto*//*Label 604*/ 19048, // Rule ID 778 // |
8329 |
GIM_Try, /*On fail goto*//*Label 604*/ 19048, // Rule ID 778 // |
| 8330 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8330 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8331 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_w, |
8331 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_w, |
| 8332 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8332 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8333 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8333 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8334 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8334 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8335 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8335 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8336 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
8336 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 8337 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
8337 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 8338 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5584:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
8338 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5584:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 8339 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_W, |
8339 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_W, |
| 8340 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8340 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8341 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8341 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8342 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8342 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8343 |
GIR_EraseFromParent, /*InsnID*/0, |
8343 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8344 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8344 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8345 |
// GIR_Coverage, 778, |
8345 |
// GIR_Coverage, 778, |
| 8346 |
GIR_Done, |
8346 |
GIR_Done, |
| 8347 |
// Label 604: @19048 |
8347 |
// Label 604: @19048 |
| 8348 |
GIM_Try, /*On fail goto*//*Label 605*/ 19100, // Rule ID 779 // |
8348 |
GIM_Try, /*On fail goto*//*Label 605*/ 19100, // Rule ID 779 // |
| 8349 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8349 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8350 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_d, |
8350 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_d, |
| 8351 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8351 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8352 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8352 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8353 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8353 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8354 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8354 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8355 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8355 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8356 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8356 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8357 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5582:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
8357 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5582:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 8358 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_D, |
8358 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_D, |
| 8359 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8359 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8360 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8360 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8361 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8361 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8362 |
GIR_EraseFromParent, /*InsnID*/0, |
8362 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8363 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8363 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8364 |
// GIR_Coverage, 779, |
8364 |
// GIR_Coverage, 779, |
| 8365 |
GIR_Done, |
8365 |
GIR_Done, |
| 8366 |
// Label 605: @19100 |
8366 |
// Label 605: @19100 |
| 8367 |
GIM_Try, /*On fail goto*//*Label 606*/ 19152, // Rule ID 832 // |
8367 |
GIM_Try, /*On fail goto*//*Label 606*/ 19152, // Rule ID 832 // |
| 8368 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8368 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8369 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_b, |
8369 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_b, |
| 8370 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
8370 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 8371 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
8371 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8372 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
8372 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8373 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
8373 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 8374 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
8374 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 8375 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
8375 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 8376 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5638:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
8376 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5638:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 8377 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_B, |
8377 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_B, |
| 8378 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8378 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8379 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8379 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8380 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8380 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8381 |
GIR_EraseFromParent, /*InsnID*/0, |
8381 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8382 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8382 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8383 |
// GIR_Coverage, 832, |
8383 |
// GIR_Coverage, 832, |
| 8384 |
GIR_Done, |
8384 |
GIR_Done, |
| 8385 |
// Label 606: @19152 |
8385 |
// Label 606: @19152 |
| 8386 |
GIM_Try, /*On fail goto*//*Label 607*/ 19204, // Rule ID 833 // |
8386 |
GIM_Try, /*On fail goto*//*Label 607*/ 19204, // Rule ID 833 // |
| 8387 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8387 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8388 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_h, |
8388 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_h, |
| 8389 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8389 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8390 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8390 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8391 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8391 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8392 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8392 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8393 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
8393 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 8394 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
8394 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 8395 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5640:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
8395 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5640:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 8396 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_H, |
8396 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_H, |
| 8397 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8397 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8398 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8398 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8399 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8399 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8400 |
GIR_EraseFromParent, /*InsnID*/0, |
8400 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8401 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8401 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8402 |
// GIR_Coverage, 833, |
8402 |
// GIR_Coverage, 833, |
| 8403 |
GIR_Done, |
8403 |
GIR_Done, |
| 8404 |
// Label 607: @19204 |
8404 |
// Label 607: @19204 |
| 8405 |
GIM_Try, /*On fail goto*//*Label 608*/ 19256, // Rule ID 834 // |
8405 |
GIM_Try, /*On fail goto*//*Label 608*/ 19256, // Rule ID 834 // |
| 8406 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8406 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8407 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_w, |
8407 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_w, |
| 8408 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8408 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8409 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8409 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8410 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8410 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8411 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8411 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8412 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8412 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8413 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8413 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8414 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5641:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
8414 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5641:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 8415 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_W, |
8415 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_W, |
| 8416 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8416 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8417 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8417 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8418 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8418 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8419 |
GIR_EraseFromParent, /*InsnID*/0, |
8419 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8420 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8420 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8421 |
// GIR_Coverage, 834, |
8421 |
// GIR_Coverage, 834, |
| 8422 |
GIR_Done, |
8422 |
GIR_Done, |
| 8423 |
// Label 608: @19256 |
8423 |
// Label 608: @19256 |
| 8424 |
GIM_Try, /*On fail goto*//*Label 609*/ 19308, // Rule ID 835 // |
8424 |
GIM_Try, /*On fail goto*//*Label 609*/ 19308, // Rule ID 835 // |
| 8425 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8425 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8426 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_d, |
8426 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_d, |
| 8427 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8427 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8428 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
8428 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8429 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
8429 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8430 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8430 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8431 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
8431 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 8432 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
8432 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 8433 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5639:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
8433 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5639:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 8434 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_D, |
8434 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_D, |
| 8435 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8435 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8436 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8436 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8437 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8437 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8438 |
GIR_EraseFromParent, /*InsnID*/0, |
8438 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8439 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8439 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8440 |
// GIR_Coverage, 835, |
8440 |
// GIR_Coverage, 835, |
| 8441 |
GIR_Done, |
8441 |
GIR_Done, |
| 8442 |
// Label 609: @19308 |
8442 |
// Label 609: @19308 |
| 8443 |
GIM_Try, /*On fail goto*//*Label 610*/ 19360, // Rule ID 852 // |
8443 |
GIM_Try, /*On fail goto*//*Label 610*/ 19360, // Rule ID 852 // |
| 8444 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8444 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8445 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_b, |
8445 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_b, |
| 8446 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
8446 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 8447 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
8447 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8448 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
8448 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8449 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
8449 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 8450 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
8450 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 8451 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
8451 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 8452 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5658:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
8452 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5658:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 8453 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_B, |
8453 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_B, |
| 8454 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8454 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8455 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8455 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8456 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8456 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8457 |
GIR_EraseFromParent, /*InsnID*/0, |
8457 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8458 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8458 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8459 |
// GIR_Coverage, 852, |
8459 |
// GIR_Coverage, 852, |
| 8460 |
GIR_Done, |
8460 |
GIR_Done, |
| 8461 |
// Label 610: @19360 |
8461 |
// Label 610: @19360 |
| 8462 |
GIM_Try, /*On fail goto*//*Label 611*/ 19412, // Rule ID 853 // |
8462 |
GIM_Try, /*On fail goto*//*Label 611*/ 19412, // Rule ID 853 // |
| 8463 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8463 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8464 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_h, |
8464 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_h, |
| 8465 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8465 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8466 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8466 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8467 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8467 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8468 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8468 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8469 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
8469 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 8470 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
8470 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 8471 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5660:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
8471 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5660:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 8472 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_H, |
8472 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_H, |
| 8473 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8473 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8474 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8474 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8475 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8475 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8476 |
GIR_EraseFromParent, /*InsnID*/0, |
8476 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8477 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8477 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8478 |
// GIR_Coverage, 853, |
8478 |
// GIR_Coverage, 853, |
| 8479 |
GIR_Done, |
8479 |
GIR_Done, |
| 8480 |
// Label 611: @19412 |
8480 |
// Label 611: @19412 |
| 8481 |
GIM_Try, /*On fail goto*//*Label 612*/ 19464, // Rule ID 854 // |
8481 |
GIM_Try, /*On fail goto*//*Label 612*/ 19464, // Rule ID 854 // |
| 8482 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8482 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8483 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_w, |
8483 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_w, |
| 8484 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8484 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8485 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8485 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8486 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8486 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8487 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8487 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8488 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8488 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8489 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8489 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8490 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5661:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
8490 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5661:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 8491 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_W, |
8491 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_W, |
| 8492 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8492 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8493 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8493 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8494 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8494 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8495 |
GIR_EraseFromParent, /*InsnID*/0, |
8495 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8496 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8496 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8497 |
// GIR_Coverage, 854, |
8497 |
// GIR_Coverage, 854, |
| 8498 |
GIR_Done, |
8498 |
GIR_Done, |
| 8499 |
// Label 612: @19464 |
8499 |
// Label 612: @19464 |
| 8500 |
GIM_Try, /*On fail goto*//*Label 613*/ 19516, // Rule ID 855 // |
8500 |
GIM_Try, /*On fail goto*//*Label 613*/ 19516, // Rule ID 855 // |
| 8501 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8501 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8502 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_d, |
8502 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_d, |
| 8503 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8503 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8504 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
8504 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8505 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
8505 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8506 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8506 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8507 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
8507 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 8508 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
8508 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 8509 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5659:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
8509 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5659:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 8510 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_D, |
8510 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_D, |
| 8511 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8511 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8512 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8512 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8513 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8513 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8514 |
GIR_EraseFromParent, /*InsnID*/0, |
8514 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8515 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8515 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8516 |
// GIR_Coverage, 855, |
8516 |
// GIR_Coverage, 855, |
| 8517 |
GIR_Done, |
8517 |
GIR_Done, |
| 8518 |
// Label 613: @19516 |
8518 |
// Label 613: @19516 |
| 8519 |
GIM_Try, /*On fail goto*//*Label 614*/ 19568, // Rule ID 888 // |
8519 |
GIM_Try, /*On fail goto*//*Label 614*/ 19568, // Rule ID 888 // |
| 8520 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8520 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8521 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_h, |
8521 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_h, |
| 8522 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8522 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8523 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8523 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8524 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8524 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8525 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8525 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8526 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
8526 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 8527 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
8527 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 8528 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5700:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
8528 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5700:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 8529 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_H, |
8529 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_H, |
| 8530 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8530 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8531 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8531 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8532 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8532 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8533 |
GIR_EraseFromParent, /*InsnID*/0, |
8533 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8534 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8534 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8535 |
// GIR_Coverage, 888, |
8535 |
// GIR_Coverage, 888, |
| 8536 |
GIR_Done, |
8536 |
GIR_Done, |
| 8537 |
// Label 614: @19568 |
8537 |
// Label 614: @19568 |
| 8538 |
GIM_Try, /*On fail goto*//*Label 615*/ 19620, // Rule ID 889 // |
8538 |
GIM_Try, /*On fail goto*//*Label 615*/ 19620, // Rule ID 889 // |
| 8539 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8539 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8540 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_w, |
8540 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_w, |
| 8541 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8541 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8542 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8542 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8543 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8543 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8544 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8544 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8545 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8545 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8546 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8546 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8547 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5701:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
8547 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5701:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 8548 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_W, |
8548 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_W, |
| 8549 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8549 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8550 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8550 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8551 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8551 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8552 |
GIR_EraseFromParent, /*InsnID*/0, |
8552 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8553 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8553 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8554 |
// GIR_Coverage, 889, |
8554 |
// GIR_Coverage, 889, |
| 8555 |
GIR_Done, |
8555 |
GIR_Done, |
| 8556 |
// Label 615: @19620 |
8556 |
// Label 615: @19620 |
| 8557 |
GIM_Try, /*On fail goto*//*Label 616*/ 19672, // Rule ID 890 // |
8557 |
GIM_Try, /*On fail goto*//*Label 616*/ 19672, // Rule ID 890 // |
| 8558 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8558 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8559 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_h, |
8559 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_h, |
| 8560 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8560 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8561 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8561 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8562 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8562 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8563 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8563 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8564 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
8564 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 8565 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
8565 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 8566 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5711:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
8566 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5711:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 8567 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_H, |
8567 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_H, |
| 8568 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8568 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8569 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8569 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8570 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8570 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8571 |
GIR_EraseFromParent, /*InsnID*/0, |
8571 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8572 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8572 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8573 |
// GIR_Coverage, 890, |
8573 |
// GIR_Coverage, 890, |
| 8574 |
GIR_Done, |
8574 |
GIR_Done, |
| 8575 |
// Label 616: @19672 |
8575 |
// Label 616: @19672 |
| 8576 |
GIM_Try, /*On fail goto*//*Label 617*/ 19724, // Rule ID 891 // |
8576 |
GIM_Try, /*On fail goto*//*Label 617*/ 19724, // Rule ID 891 // |
| 8577 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8577 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8578 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_w, |
8578 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_w, |
| 8579 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8579 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8580 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8580 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8581 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8581 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8582 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8582 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8583 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8583 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8584 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8584 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8585 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5712:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
8585 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5712:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 8586 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_W, |
8586 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_W, |
| 8587 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8587 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8588 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8588 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8589 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8589 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8590 |
GIR_EraseFromParent, /*InsnID*/0, |
8590 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8591 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8591 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8592 |
// GIR_Coverage, 891, |
8592 |
// GIR_Coverage, 891, |
| 8593 |
GIR_Done, |
8593 |
GIR_Done, |
| 8594 |
// Label 617: @19724 |
8594 |
// Label 617: @19724 |
| 8595 |
GIM_Try, /*On fail goto*//*Label 618*/ 19776, // Rule ID 969 // |
8595 |
GIM_Try, /*On fail goto*//*Label 618*/ 19776, // Rule ID 969 // |
| 8596 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8596 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8597 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_b, |
8597 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_b, |
| 8598 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
8598 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 8599 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
8599 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8600 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
8600 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8601 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
8601 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 8602 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
8602 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 8603 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
8603 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 8604 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5825:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
8604 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5825:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 8605 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_B, |
8605 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_B, |
| 8606 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8606 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8607 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8607 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8608 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8608 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8609 |
GIR_EraseFromParent, /*InsnID*/0, |
8609 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8610 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8610 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8611 |
// GIR_Coverage, 969, |
8611 |
// GIR_Coverage, 969, |
| 8612 |
GIR_Done, |
8612 |
GIR_Done, |
| 8613 |
// Label 618: @19776 |
8613 |
// Label 618: @19776 |
| 8614 |
GIM_Try, /*On fail goto*//*Label 619*/ 19828, // Rule ID 970 // |
8614 |
GIM_Try, /*On fail goto*//*Label 619*/ 19828, // Rule ID 970 // |
| 8615 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8615 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8616 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_h, |
8616 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_h, |
| 8617 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8617 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8618 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8618 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8619 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8619 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8620 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8620 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8621 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
8621 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 8622 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
8622 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 8623 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5827:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
8623 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5827:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 8624 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_H, |
8624 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_H, |
| 8625 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8625 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8626 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8626 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8627 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8627 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8628 |
GIR_EraseFromParent, /*InsnID*/0, |
8628 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8629 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8629 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8630 |
// GIR_Coverage, 970, |
8630 |
// GIR_Coverage, 970, |
| 8631 |
GIR_Done, |
8631 |
GIR_Done, |
| 8632 |
// Label 619: @19828 |
8632 |
// Label 619: @19828 |
| 8633 |
GIM_Try, /*On fail goto*//*Label 620*/ 19880, // Rule ID 971 // |
8633 |
GIM_Try, /*On fail goto*//*Label 620*/ 19880, // Rule ID 971 // |
| 8634 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8634 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8635 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_w, |
8635 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_w, |
| 8636 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8636 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8637 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8637 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8638 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8638 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8639 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8639 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8640 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8640 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8641 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8641 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8642 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5828:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
8642 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5828:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 8643 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_W, |
8643 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_W, |
| 8644 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8644 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8645 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8645 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8646 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8646 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8647 |
GIR_EraseFromParent, /*InsnID*/0, |
8647 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8648 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8648 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8649 |
// GIR_Coverage, 971, |
8649 |
// GIR_Coverage, 971, |
| 8650 |
GIR_Done, |
8650 |
GIR_Done, |
| 8651 |
// Label 620: @19880 |
8651 |
// Label 620: @19880 |
| 8652 |
GIM_Try, /*On fail goto*//*Label 621*/ 19932, // Rule ID 972 // |
8652 |
GIM_Try, /*On fail goto*//*Label 621*/ 19932, // Rule ID 972 // |
| 8653 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8653 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8654 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_d, |
8654 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_d, |
| 8655 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8655 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8656 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
8656 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8657 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
8657 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8658 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8658 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8659 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
8659 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 8660 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
8660 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 8661 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5826:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
8661 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5826:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 8662 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_D, |
8662 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_D, |
| 8663 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8663 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8664 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8664 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8665 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8665 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8666 |
GIR_EraseFromParent, /*InsnID*/0, |
8666 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8667 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8667 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8668 |
// GIR_Coverage, 972, |
8668 |
// GIR_Coverage, 972, |
| 8669 |
GIR_Done, |
8669 |
GIR_Done, |
| 8670 |
// Label 621: @19932 |
8670 |
// Label 621: @19932 |
| 8671 |
GIM_Try, /*On fail goto*//*Label 622*/ 19984, // Rule ID 985 // |
8671 |
GIM_Try, /*On fail goto*//*Label 622*/ 19984, // Rule ID 985 // |
| 8672 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8672 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8673 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_b, |
8673 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_b, |
| 8674 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
8674 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 8675 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
8675 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8676 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
8676 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8677 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
8677 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 8678 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
8678 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 8679 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
8679 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 8680 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5841:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
8680 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5841:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 8681 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_B, |
8681 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_B, |
| 8682 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8682 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8683 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8683 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8684 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8684 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8685 |
GIR_EraseFromParent, /*InsnID*/0, |
8685 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8686 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8686 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8687 |
// GIR_Coverage, 985, |
8687 |
// GIR_Coverage, 985, |
| 8688 |
GIR_Done, |
8688 |
GIR_Done, |
| 8689 |
// Label 622: @19984 |
8689 |
// Label 622: @19984 |
| 8690 |
GIM_Try, /*On fail goto*//*Label 623*/ 20036, // Rule ID 986 // |
8690 |
GIM_Try, /*On fail goto*//*Label 623*/ 20036, // Rule ID 986 // |
| 8691 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8691 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8692 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_h, |
8692 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_h, |
| 8693 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8693 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8694 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8694 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8695 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8695 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8696 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8696 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8697 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
8697 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 8698 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
8698 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 8699 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5843:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
8699 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5843:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 8700 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_H, |
8700 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_H, |
| 8701 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8701 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8702 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8702 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8703 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8703 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8704 |
GIR_EraseFromParent, /*InsnID*/0, |
8704 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8705 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8705 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8706 |
// GIR_Coverage, 986, |
8706 |
// GIR_Coverage, 986, |
| 8707 |
GIR_Done, |
8707 |
GIR_Done, |
| 8708 |
// Label 623: @20036 |
8708 |
// Label 623: @20036 |
| 8709 |
GIM_Try, /*On fail goto*//*Label 624*/ 20088, // Rule ID 987 // |
8709 |
GIM_Try, /*On fail goto*//*Label 624*/ 20088, // Rule ID 987 // |
| 8710 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8710 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8711 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_w, |
8711 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_w, |
| 8712 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8712 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8713 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8713 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8714 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8714 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8715 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8715 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8716 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8716 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8717 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8717 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8718 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5844:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
8718 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5844:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 8719 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_W, |
8719 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_W, |
| 8720 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8720 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8721 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8721 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8722 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8722 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8723 |
GIR_EraseFromParent, /*InsnID*/0, |
8723 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8724 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8724 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8725 |
// GIR_Coverage, 987, |
8725 |
// GIR_Coverage, 987, |
| 8726 |
GIR_Done, |
8726 |
GIR_Done, |
| 8727 |
// Label 624: @20088 |
8727 |
// Label 624: @20088 |
| 8728 |
GIM_Try, /*On fail goto*//*Label 625*/ 20140, // Rule ID 988 // |
8728 |
GIM_Try, /*On fail goto*//*Label 625*/ 20140, // Rule ID 988 // |
| 8729 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8729 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8730 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_d, |
8730 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_d, |
| 8731 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8731 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8732 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
8732 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8733 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
8733 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8734 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8734 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8735 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
8735 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 8736 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
8736 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 8737 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5842:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
8737 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5842:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 8738 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_D, |
8738 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_D, |
| 8739 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8739 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8740 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8740 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8741 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8741 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8742 |
GIR_EraseFromParent, /*InsnID*/0, |
8742 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8743 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8743 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8744 |
// GIR_Coverage, 988, |
8744 |
// GIR_Coverage, 988, |
| 8745 |
GIR_Done, |
8745 |
GIR_Done, |
| 8746 |
// Label 625: @20140 |
8746 |
// Label 625: @20140 |
| 8747 |
GIM_Try, /*On fail goto*//*Label 626*/ 20192, // Rule ID 997 // |
8747 |
GIM_Try, /*On fail goto*//*Label 626*/ 20192, // Rule ID 997 // |
| 8748 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8748 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8749 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_b, |
8749 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_b, |
| 8750 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
8750 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 8751 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
8751 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8752 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
8752 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8753 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
8753 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 8754 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
8754 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 8755 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
8755 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 8756 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5862:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
8756 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5862:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 8757 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_B, |
8757 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_B, |
| 8758 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8758 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8759 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8759 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8760 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8760 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8761 |
GIR_EraseFromParent, /*InsnID*/0, |
8761 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8762 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8762 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8763 |
// GIR_Coverage, 997, |
8763 |
// GIR_Coverage, 997, |
| 8764 |
GIR_Done, |
8764 |
GIR_Done, |
| 8765 |
// Label 626: @20192 |
8765 |
// Label 626: @20192 |
| 8766 |
GIM_Try, /*On fail goto*//*Label 627*/ 20244, // Rule ID 998 // |
8766 |
GIM_Try, /*On fail goto*//*Label 627*/ 20244, // Rule ID 998 // |
| 8767 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8767 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8768 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_h, |
8768 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_h, |
| 8769 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8769 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8770 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8770 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8771 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8771 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8772 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8772 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8773 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
8773 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 8774 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
8774 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 8775 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5864:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
8775 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5864:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 8776 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_H, |
8776 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_H, |
| 8777 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8777 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8778 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8778 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8779 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8779 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8780 |
GIR_EraseFromParent, /*InsnID*/0, |
8780 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8781 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8781 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8782 |
// GIR_Coverage, 998, |
8782 |
// GIR_Coverage, 998, |
| 8783 |
GIR_Done, |
8783 |
GIR_Done, |
| 8784 |
// Label 627: @20244 |
8784 |
// Label 627: @20244 |
| 8785 |
GIM_Try, /*On fail goto*//*Label 628*/ 20296, // Rule ID 999 // |
8785 |
GIM_Try, /*On fail goto*//*Label 628*/ 20296, // Rule ID 999 // |
| 8786 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8786 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8787 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_w, |
8787 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_w, |
| 8788 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8788 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8789 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8789 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8790 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8790 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8791 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8791 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8792 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8792 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8793 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8793 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8794 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5865:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
8794 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5865:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 8795 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_W, |
8795 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_W, |
| 8796 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8796 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8797 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8797 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8798 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8798 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8799 |
GIR_EraseFromParent, /*InsnID*/0, |
8799 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8800 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8800 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8801 |
// GIR_Coverage, 999, |
8801 |
// GIR_Coverage, 999, |
| 8802 |
GIR_Done, |
8802 |
GIR_Done, |
| 8803 |
// Label 628: @20296 |
8803 |
// Label 628: @20296 |
| 8804 |
GIM_Try, /*On fail goto*//*Label 629*/ 20348, // Rule ID 1000 // |
8804 |
GIM_Try, /*On fail goto*//*Label 629*/ 20348, // Rule ID 1000 // |
| 8805 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8805 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8806 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_d, |
8806 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_d, |
| 8807 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8807 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8808 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
8808 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8809 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
8809 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8810 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8810 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8811 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
8811 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 8812 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
8812 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 8813 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5863:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
8813 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5863:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 8814 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_D, |
8814 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_D, |
| 8815 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8815 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8816 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8816 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8817 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8817 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8818 |
GIR_EraseFromParent, /*InsnID*/0, |
8818 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8819 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8819 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8820 |
// GIR_Coverage, 1000, |
8820 |
// GIR_Coverage, 1000, |
| 8821 |
GIR_Done, |
8821 |
GIR_Done, |
| 8822 |
// Label 629: @20348 |
8822 |
// Label 629: @20348 |
| 8823 |
GIM_Try, /*On fail goto*//*Label 630*/ 20400, // Rule ID 1001 // |
8823 |
GIM_Try, /*On fail goto*//*Label 630*/ 20400, // Rule ID 1001 // |
| 8824 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8824 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8825 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_b, |
8825 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_b, |
| 8826 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
8826 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 8827 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
8827 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8828 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
8828 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8829 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
8829 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 8830 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
8830 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 8831 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
8831 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 8832 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5866:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
8832 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5866:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 8833 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_B, |
8833 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_B, |
| 8834 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8834 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8835 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8835 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8836 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8836 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8837 |
GIR_EraseFromParent, /*InsnID*/0, |
8837 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8838 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8838 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8839 |
// GIR_Coverage, 1001, |
8839 |
// GIR_Coverage, 1001, |
| 8840 |
GIR_Done, |
8840 |
GIR_Done, |
| 8841 |
// Label 630: @20400 |
8841 |
// Label 630: @20400 |
| 8842 |
GIM_Try, /*On fail goto*//*Label 631*/ 20452, // Rule ID 1002 // |
8842 |
GIM_Try, /*On fail goto*//*Label 631*/ 20452, // Rule ID 1002 // |
| 8843 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8843 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8844 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_h, |
8844 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_h, |
| 8845 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8845 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8846 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8846 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8847 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8847 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8848 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8848 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8849 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
8849 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 8850 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
8850 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 8851 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5868:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
8851 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5868:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 8852 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_H, |
8852 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_H, |
| 8853 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8853 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8854 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8854 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8855 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8855 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8856 |
GIR_EraseFromParent, /*InsnID*/0, |
8856 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8857 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8857 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8858 |
// GIR_Coverage, 1002, |
8858 |
// GIR_Coverage, 1002, |
| 8859 |
GIR_Done, |
8859 |
GIR_Done, |
| 8860 |
// Label 631: @20452 |
8860 |
// Label 631: @20452 |
| 8861 |
GIM_Try, /*On fail goto*//*Label 632*/ 20504, // Rule ID 1003 // |
8861 |
GIM_Try, /*On fail goto*//*Label 632*/ 20504, // Rule ID 1003 // |
| 8862 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8862 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8863 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_w, |
8863 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_w, |
| 8864 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8864 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8865 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8865 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8866 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8866 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8867 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8867 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8868 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8868 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8869 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8869 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8870 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5869:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
8870 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5869:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 8871 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_W, |
8871 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_W, |
| 8872 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8872 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8873 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8873 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8874 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8874 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8875 |
GIR_EraseFromParent, /*InsnID*/0, |
8875 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8876 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8876 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8877 |
// GIR_Coverage, 1003, |
8877 |
// GIR_Coverage, 1003, |
| 8878 |
GIR_Done, |
8878 |
GIR_Done, |
| 8879 |
// Label 632: @20504 |
8879 |
// Label 632: @20504 |
| 8880 |
GIM_Try, /*On fail goto*//*Label 633*/ 20556, // Rule ID 1004 // |
8880 |
GIM_Try, /*On fail goto*//*Label 633*/ 20556, // Rule ID 1004 // |
| 8881 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8881 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8882 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_d, |
8882 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_d, |
| 8883 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8883 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8884 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
8884 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8885 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
8885 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8886 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8886 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8887 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
8887 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 8888 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
8888 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 8889 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5867:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
8889 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5867:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 8890 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_D, |
8890 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_D, |
| 8891 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8891 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8892 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8892 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8893 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8893 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8894 |
GIR_EraseFromParent, /*InsnID*/0, |
8894 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8895 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8895 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8896 |
// GIR_Coverage, 1004, |
8896 |
// GIR_Coverage, 1004, |
| 8897 |
GIR_Done, |
8897 |
GIR_Done, |
| 8898 |
// Label 633: @20556 |
8898 |
// Label 633: @20556 |
| 8899 |
GIM_Try, /*On fail goto*//*Label 634*/ 20608, // Rule ID 1005 // |
8899 |
GIM_Try, /*On fail goto*//*Label 634*/ 20608, // Rule ID 1005 // |
| 8900 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8900 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8901 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_b, |
8901 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_b, |
| 8902 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
8902 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 8903 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
8903 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8904 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
8904 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8905 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
8905 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 8906 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
8906 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 8907 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
8907 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 8908 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5870:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
8908 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5870:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 8909 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_B, |
8909 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_B, |
| 8910 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8910 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8911 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8911 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8912 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8912 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8913 |
GIR_EraseFromParent, /*InsnID*/0, |
8913 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8914 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8914 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8915 |
// GIR_Coverage, 1005, |
8915 |
// GIR_Coverage, 1005, |
| 8916 |
GIR_Done, |
8916 |
GIR_Done, |
| 8917 |
// Label 634: @20608 |
8917 |
// Label 634: @20608 |
| 8918 |
GIM_Try, /*On fail goto*//*Label 635*/ 20660, // Rule ID 1006 // |
8918 |
GIM_Try, /*On fail goto*//*Label 635*/ 20660, // Rule ID 1006 // |
| 8919 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8919 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8920 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_h, |
8920 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_h, |
| 8921 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8921 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8922 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8922 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8923 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8923 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 8924 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
8924 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 8925 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
8925 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 8926 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
8926 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 8927 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5872:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
8927 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5872:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 8928 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_H, |
8928 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_H, |
| 8929 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8929 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8930 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8930 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8931 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8931 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8932 |
GIR_EraseFromParent, /*InsnID*/0, |
8932 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8933 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8933 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8934 |
// GIR_Coverage, 1006, |
8934 |
// GIR_Coverage, 1006, |
| 8935 |
GIR_Done, |
8935 |
GIR_Done, |
| 8936 |
// Label 635: @20660 |
8936 |
// Label 635: @20660 |
| 8937 |
GIM_Try, /*On fail goto*//*Label 636*/ 20712, // Rule ID 1007 // |
8937 |
GIM_Try, /*On fail goto*//*Label 636*/ 20712, // Rule ID 1007 // |
| 8938 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8938 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8939 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_w, |
8939 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_w, |
| 8940 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
8940 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 8941 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
8941 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 8942 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
8942 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 8943 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
8943 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 8944 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
8944 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 8945 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
8945 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 8946 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5873:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
8946 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5873:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 8947 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_W, |
8947 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_W, |
| 8948 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8948 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8949 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8949 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8950 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8950 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8951 |
GIR_EraseFromParent, /*InsnID*/0, |
8951 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8952 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8952 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8953 |
// GIR_Coverage, 1007, |
8953 |
// GIR_Coverage, 1007, |
| 8954 |
GIR_Done, |
8954 |
GIR_Done, |
| 8955 |
// Label 636: @20712 |
8955 |
// Label 636: @20712 |
| 8956 |
GIM_Try, /*On fail goto*//*Label 637*/ 20764, // Rule ID 1008 // |
8956 |
GIM_Try, /*On fail goto*//*Label 637*/ 20764, // Rule ID 1008 // |
| 8957 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8957 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8958 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_d, |
8958 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_d, |
| 8959 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
8959 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 8960 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
8960 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 8961 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
8961 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 8962 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
8962 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 8963 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
8963 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 8964 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
8964 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 8965 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5871:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
8965 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5871:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 8966 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_D, |
8966 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_D, |
| 8967 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8967 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8968 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8968 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8969 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8969 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8970 |
GIR_EraseFromParent, /*InsnID*/0, |
8970 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8971 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8971 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8972 |
// GIR_Coverage, 1008, |
8972 |
// GIR_Coverage, 1008, |
| 8973 |
GIR_Done, |
8973 |
GIR_Done, |
| 8974 |
// Label 637: @20764 |
8974 |
// Label 637: @20764 |
| 8975 |
GIM_Try, /*On fail goto*//*Label 638*/ 20816, // Rule ID 1009 // |
8975 |
GIM_Try, /*On fail goto*//*Label 638*/ 20816, // Rule ID 1009 // |
| 8976 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8976 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8977 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_b, |
8977 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_b, |
| 8978 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
8978 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 8979 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
8979 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 8980 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
8980 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 8981 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
8981 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 8982 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
8982 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 8983 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
8983 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 8984 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5874:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
8984 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5874:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 8985 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_B, |
8985 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_B, |
| 8986 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
8986 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 8987 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
8987 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 8988 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
8988 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 8989 |
GIR_EraseFromParent, /*InsnID*/0, |
8989 |
GIR_EraseFromParent, /*InsnID*/0, |
| 8990 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
8990 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 8991 |
// GIR_Coverage, 1009, |
8991 |
// GIR_Coverage, 1009, |
| 8992 |
GIR_Done, |
8992 |
GIR_Done, |
| 8993 |
// Label 638: @20816 |
8993 |
// Label 638: @20816 |
| 8994 |
GIM_Try, /*On fail goto*//*Label 639*/ 20868, // Rule ID 1010 // |
8994 |
GIM_Try, /*On fail goto*//*Label 639*/ 20868, // Rule ID 1010 // |
| 8995 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
8995 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 8996 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_h, |
8996 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_h, |
| 8997 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
8997 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 8998 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
8998 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 8999 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
8999 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 9000 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
9000 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 9001 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
9001 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 9002 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
9002 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 9003 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5876:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
9003 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5876:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 9004 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_H, |
9004 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_H, |
| 9005 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
9005 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 9006 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
9006 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 9007 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
9007 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 9008 |
GIR_EraseFromParent, /*InsnID*/0, |
9008 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9009 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9009 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9010 |
// GIR_Coverage, 1010, |
9010 |
// GIR_Coverage, 1010, |
| 9011 |
GIR_Done, |
9011 |
GIR_Done, |
| 9012 |
// Label 639: @20868 |
9012 |
// Label 639: @20868 |
| 9013 |
GIM_Try, /*On fail goto*//*Label 640*/ 20920, // Rule ID 1011 // |
9013 |
GIM_Try, /*On fail goto*//*Label 640*/ 20920, // Rule ID 1011 // |
| 9014 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
9014 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 9015 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_w, |
9015 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_w, |
| 9016 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
9016 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9017 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
9017 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9018 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
9018 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 9019 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
9019 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 9020 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
9020 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 9021 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
9021 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 9022 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5877:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
9022 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5877:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 9023 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_W, |
9023 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_W, |
| 9024 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
9024 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 9025 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
9025 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 9026 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
9026 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 9027 |
GIR_EraseFromParent, /*InsnID*/0, |
9027 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9028 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9028 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9029 |
// GIR_Coverage, 1011, |
9029 |
// GIR_Coverage, 1011, |
| 9030 |
GIR_Done, |
9030 |
GIR_Done, |
| 9031 |
// Label 640: @20920 |
9031 |
// Label 640: @20920 |
| 9032 |
GIM_Try, /*On fail goto*//*Label 641*/ 20972, // Rule ID 1012 // |
9032 |
GIM_Try, /*On fail goto*//*Label 641*/ 20972, // Rule ID 1012 // |
| 9033 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
9033 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 9034 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_d, |
9034 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_d, |
| 9035 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
9035 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9036 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
9036 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9037 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
9037 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 9038 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
9038 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 9039 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
9039 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 9040 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
9040 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 9041 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5875:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
9041 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5875:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 9042 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_D, |
9042 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_D, |
| 9043 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
9043 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 9044 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
9044 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 9045 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
9045 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt |
| 9046 |
GIR_EraseFromParent, /*InsnID*/0, |
9046 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9047 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9047 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9048 |
// GIR_Coverage, 1012, |
9048 |
// GIR_Coverage, 1012, |
| 9049 |
GIR_Done, |
9049 |
GIR_Done, |
| 9050 |
// Label 641: @20972 |
9050 |
// Label 641: @20972 |
| 9051 |
GIM_Try, /*On fail goto*//*Label 642*/ 21024, // Rule ID 1211 // |
9051 |
GIM_Try, /*On fail goto*//*Label 642*/ 21024, // Rule ID 1211 // |
| 9052 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
9052 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 9053 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph, |
9053 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph, |
| 9054 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9054 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9055 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
9055 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9056 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
9056 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 9057 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9057 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9058 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9058 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9059 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9059 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9060 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5236:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
9060 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5236:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 9061 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH_MM, |
9061 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH_MM, |
| 9062 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9062 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9063 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9063 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9064 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9064 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9065 |
GIR_EraseFromParent, /*InsnID*/0, |
9065 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9066 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9066 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9067 |
// GIR_Coverage, 1211, |
9067 |
// GIR_Coverage, 1211, |
| 9068 |
GIR_Done, |
9068 |
GIR_Done, |
| 9069 |
// Label 642: @21024 |
9069 |
// Label 642: @21024 |
| 9070 |
GIM_Try, /*On fail goto*//*Label 643*/ 21076, // Rule ID 1213 // |
9070 |
GIM_Try, /*On fail goto*//*Label 643*/ 21076, // Rule ID 1213 // |
| 9071 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
9071 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 9072 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb, |
9072 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb, |
| 9073 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
9073 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 9074 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
9074 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 9075 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
9075 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 9076 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9076 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9077 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9077 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9078 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9078 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9079 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5258:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
9079 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5258:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 9080 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB_MM, |
9080 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB_MM, |
| 9081 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9081 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9082 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9082 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9083 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9083 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9084 |
GIR_EraseFromParent, /*InsnID*/0, |
9084 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9085 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9085 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9086 |
// GIR_Coverage, 1213, |
9086 |
// GIR_Coverage, 1213, |
| 9087 |
GIR_Done, |
9087 |
GIR_Done, |
| 9088 |
// Label 643: @21076 |
9088 |
// Label 643: @21076 |
| 9089 |
GIM_Try, /*On fail goto*//*Label 644*/ 21128, // Rule ID 1234 // |
9089 |
GIM_Try, /*On fail goto*//*Label 644*/ 21128, // Rule ID 1234 // |
| 9090 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
9090 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 9091 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph, |
9091 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph, |
| 9092 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9092 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9093 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
9093 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9094 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9094 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9095 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9095 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9096 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9096 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9097 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9097 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9098 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5786:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
9098 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5786:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 9099 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH_MM, |
9099 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH_MM, |
| 9100 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9100 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9101 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
9101 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 9102 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9102 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9103 |
GIR_EraseFromParent, /*InsnID*/0, |
9103 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9104 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9104 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9105 |
// GIR_Coverage, 1234, |
9105 |
// GIR_Coverage, 1234, |
| 9106 |
GIR_Done, |
9106 |
GIR_Done, |
| 9107 |
// Label 644: @21128 |
9107 |
// Label 644: @21128 |
| 9108 |
GIM_Try, /*On fail goto*//*Label 645*/ 21180, // Rule ID 1235 // |
9108 |
GIM_Try, /*On fail goto*//*Label 645*/ 21180, // Rule ID 1235 // |
| 9109 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
9109 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 9110 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph, |
9110 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph, |
| 9111 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9111 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9112 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
9112 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9113 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9113 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9114 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9114 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9115 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9115 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9116 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9116 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9117 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5788:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
9117 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5788:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 9118 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH_MM, |
9118 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH_MM, |
| 9119 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9119 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9120 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
9120 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 9121 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9121 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9122 |
GIR_EraseFromParent, /*InsnID*/0, |
9122 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9123 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9123 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9124 |
// GIR_Coverage, 1235, |
9124 |
// GIR_Coverage, 1235, |
| 9125 |
GIR_Done, |
9125 |
GIR_Done, |
| 9126 |
// Label 645: @21180 |
9126 |
// Label 645: @21180 |
| 9127 |
GIM_Try, /*On fail goto*//*Label 646*/ 21232, // Rule ID 1236 // |
9127 |
GIM_Try, /*On fail goto*//*Label 646*/ 21232, // Rule ID 1236 // |
| 9128 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
9128 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 9129 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w, |
9129 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w, |
| 9130 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
9130 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 9131 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9131 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9132 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9132 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9133 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
9133 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 9134 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9134 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9135 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9135 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9136 |
// (intrinsic_wo_chain:{ *:[i32] } 5790:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
9136 |
// (intrinsic_wo_chain:{ *:[i32] } 5790:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 9137 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W_MM, |
9137 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W_MM, |
| 9138 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9138 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9139 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
9139 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 9140 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9140 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9141 |
GIR_EraseFromParent, /*InsnID*/0, |
9141 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9142 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9142 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9143 |
// GIR_Coverage, 1236, |
9143 |
// GIR_Coverage, 1236, |
| 9144 |
GIR_Done, |
9144 |
GIR_Done, |
| 9145 |
// Label 646: @21232 |
9145 |
// Label 646: @21232 |
| 9146 |
GIM_Try, /*On fail goto*//*Label 647*/ 21284, // Rule ID 1238 // |
9146 |
GIM_Try, /*On fail goto*//*Label 647*/ 21284, // Rule ID 1238 // |
| 9147 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
9147 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 9148 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb, |
9148 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb, |
| 9149 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
9149 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 9150 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
9150 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 9151 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9151 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9152 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9152 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9153 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9153 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9154 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9154 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9155 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5792:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
9155 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5792:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 9156 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB_MM, |
9156 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB_MM, |
| 9157 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9157 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9158 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
9158 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 9159 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9159 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9160 |
GIR_EraseFromParent, /*InsnID*/0, |
9160 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9161 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9161 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9162 |
// GIR_Coverage, 1238, |
9162 |
// GIR_Coverage, 1238, |
| 9163 |
GIR_Done, |
9163 |
GIR_Done, |
| 9164 |
// Label 647: @21284 |
9164 |
// Label 647: @21284 |
| 9165 |
GIM_Try, /*On fail goto*//*Label 648*/ 21336, // Rule ID 1249 // |
9165 |
GIM_Try, /*On fail goto*//*Label 648*/ 21336, // Rule ID 1249 // |
| 9166 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
9166 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 9167 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph, |
9167 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph, |
| 9168 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9168 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9169 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
9169 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9170 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
9170 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 9171 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9171 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9172 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9172 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9173 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9173 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9174 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5856:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
9174 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5856:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 9175 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH_MM, |
9175 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH_MM, |
| 9176 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9176 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9177 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9177 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9178 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9178 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9179 |
GIR_EraseFromParent, /*InsnID*/0, |
9179 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9180 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9180 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9181 |
// GIR_Coverage, 1249, |
9181 |
// GIR_Coverage, 1249, |
| 9182 |
GIR_Done, |
9182 |
GIR_Done, |
| 9183 |
// Label 648: @21336 |
9183 |
// Label 648: @21336 |
| 9184 |
GIM_Try, /*On fail goto*//*Label 649*/ 21388, // Rule ID 1251 // |
9184 |
GIM_Try, /*On fail goto*//*Label 649*/ 21388, // Rule ID 1251 // |
| 9185 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
9185 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 9186 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb, |
9186 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb, |
| 9187 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
9187 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 9188 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
9188 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 9189 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
9189 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 9190 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9190 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9191 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9191 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9192 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9192 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9193 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5881:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
9193 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5881:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 9194 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB_MM, |
9194 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB_MM, |
| 9195 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9195 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9196 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9196 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9197 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9197 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9198 |
GIR_EraseFromParent, /*InsnID*/0, |
9198 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9199 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9199 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9200 |
// GIR_Coverage, 1251, |
9200 |
// GIR_Coverage, 1251, |
| 9201 |
GIR_Done, |
9201 |
GIR_Done, |
| 9202 |
// Label 649: @21388 |
9202 |
// Label 649: @21388 |
| 9203 |
GIM_Try, /*On fail goto*//*Label 650*/ 21440, // Rule ID 1261 // |
9203 |
GIM_Try, /*On fail goto*//*Label 650*/ 21440, // Rule ID 1261 // |
| 9204 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
9204 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 9205 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w, |
9205 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w, |
| 9206 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9206 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9207 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9207 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9208 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9208 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9209 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9209 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9210 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9210 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9212 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5761:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
9212 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5761:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 9213 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W_MM, |
9213 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W_MM, |
| 9214 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9214 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9215 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9215 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9216 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9216 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9217 |
GIR_EraseFromParent, /*InsnID*/0, |
9217 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9218 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9218 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9219 |
// GIR_Coverage, 1261, |
9219 |
// GIR_Coverage, 1261, |
| 9220 |
GIR_Done, |
9220 |
GIR_Done, |
| 9221 |
// Label 650: @21440 |
9221 |
// Label 650: @21440 |
| 9222 |
GIM_Try, /*On fail goto*//*Label 651*/ 21492, // Rule ID 1262 // |
9222 |
GIM_Try, /*On fail goto*//*Label 651*/ 21492, // Rule ID 1262 // |
| 9223 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
9223 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 9224 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph, |
9224 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph, |
| 9225 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
9225 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 9226 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
9226 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9227 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
9227 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 9228 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9228 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9229 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9229 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9230 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9230 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9231 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5762:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
9231 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5762:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 9232 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH_MM, |
9232 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH_MM, |
| 9233 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9233 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9234 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9234 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9235 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9235 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9236 |
GIR_EraseFromParent, /*InsnID*/0, |
9236 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9237 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9237 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9238 |
// GIR_Coverage, 1262, |
9238 |
// GIR_Coverage, 1262, |
| 9239 |
GIR_Done, |
9239 |
GIR_Done, |
| 9240 |
// Label 651: @21492 |
9240 |
// Label 651: @21492 |
| 9241 |
GIM_Try, /*On fail goto*//*Label 652*/ 21544, // Rule ID 1281 // |
9241 |
GIM_Try, /*On fail goto*//*Label 652*/ 21544, // Rule ID 1281 // |
| 9242 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
9242 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 9243 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph, |
9243 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph, |
| 9244 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9244 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9245 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
9245 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9246 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
9246 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 9247 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9247 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9248 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9248 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9249 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9249 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9250 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5733:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
9250 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5733:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 9251 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH_MM, |
9251 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH_MM, |
| 9252 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9252 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9253 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9253 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9254 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9254 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9255 |
GIR_EraseFromParent, /*InsnID*/0, |
9255 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9256 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9256 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9257 |
// GIR_Coverage, 1281, |
9257 |
// GIR_Coverage, 1281, |
| 9258 |
GIR_Done, |
9258 |
GIR_Done, |
| 9259 |
// Label 652: @21544 |
9259 |
// Label 652: @21544 |
| 9260 |
GIM_Try, /*On fail goto*//*Label 653*/ 21596, // Rule ID 1287 // |
9260 |
GIM_Try, /*On fail goto*//*Label 653*/ 21596, // Rule ID 1287 // |
| 9261 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
9261 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 9262 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub, |
9262 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub, |
| 9263 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
9263 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 9264 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9264 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9265 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9265 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9266 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
9266 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 9267 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9267 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9268 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9268 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9269 |
// (intrinsic_wo_chain:{ *:[i32] } 5686:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
9269 |
// (intrinsic_wo_chain:{ *:[i32] } 5686:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 9270 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB_MM, |
9270 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB_MM, |
| 9271 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9271 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9272 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9272 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9273 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9273 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9274 |
GIR_EraseFromParent, /*InsnID*/0, |
9274 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9275 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9275 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9276 |
// GIR_Coverage, 1287, |
9276 |
// GIR_Coverage, 1287, |
| 9277 |
GIR_Done, |
9277 |
GIR_Done, |
| 9278 |
// Label 653: @21596 |
9278 |
// Label 653: @21596 |
| 9279 |
GIM_Try, /*On fail goto*//*Label 654*/ 21648, // Rule ID 1300 // |
9279 |
GIM_Try, /*On fail goto*//*Label 654*/ 21648, // Rule ID 1300 // |
| 9280 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9280 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9281 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph, |
9281 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph, |
| 9282 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9282 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9283 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
9283 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9284 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
9284 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 9285 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9285 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9286 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9286 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9287 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9287 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9288 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5238:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
9288 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5238:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 9289 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH_MMR2, |
9289 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH_MMR2, |
| 9290 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9290 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9291 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9291 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9292 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9292 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9293 |
GIR_EraseFromParent, /*InsnID*/0, |
9293 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9294 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9294 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9295 |
// GIR_Coverage, 1300, |
9295 |
// GIR_Coverage, 1300, |
| 9296 |
GIR_Done, |
9296 |
GIR_Done, |
| 9297 |
// Label 654: @21648 |
9297 |
// Label 654: @21648 |
| 9298 |
GIM_Try, /*On fail goto*//*Label 655*/ 21700, // Rule ID 1301 // |
9298 |
GIM_Try, /*On fail goto*//*Label 655*/ 21700, // Rule ID 1301 // |
| 9299 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9299 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9300 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph, |
9300 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph, |
| 9301 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9301 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9302 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
9302 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9303 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
9303 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 9304 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9304 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9305 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9305 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9306 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9306 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9307 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5239:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
9307 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5239:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 9308 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH_MMR2, |
9308 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH_MMR2, |
| 9309 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9309 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9310 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9310 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9311 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9311 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9312 |
GIR_EraseFromParent, /*InsnID*/0, |
9312 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9313 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9313 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9314 |
// GIR_Coverage, 1301, |
9314 |
// GIR_Coverage, 1301, |
| 9315 |
GIR_Done, |
9315 |
GIR_Done, |
| 9316 |
// Label 655: @21700 |
9316 |
// Label 655: @21700 |
| 9317 |
GIM_Try, /*On fail goto*//*Label 656*/ 21752, // Rule ID 1302 // |
9317 |
GIM_Try, /*On fail goto*//*Label 656*/ 21752, // Rule ID 1302 // |
| 9318 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9318 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9319 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w, |
9319 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w, |
| 9320 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
9320 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 9321 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9321 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9322 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9322 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9323 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
9323 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 9324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9325 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9325 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9326 |
// (intrinsic_wo_chain:{ *:[i32] } 5241:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
9326 |
// (intrinsic_wo_chain:{ *:[i32] } 5241:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 9327 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W_MMR2, |
9327 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W_MMR2, |
| 9328 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9328 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9329 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9329 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9330 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9330 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9331 |
GIR_EraseFromParent, /*InsnID*/0, |
9331 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9332 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9332 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9333 |
// GIR_Coverage, 1302, |
9333 |
// GIR_Coverage, 1302, |
| 9334 |
GIR_Done, |
9334 |
GIR_Done, |
| 9335 |
// Label 656: @21752 |
9335 |
// Label 656: @21752 |
| 9336 |
GIM_Try, /*On fail goto*//*Label 657*/ 21804, // Rule ID 1303 // |
9336 |
GIM_Try, /*On fail goto*//*Label 657*/ 21804, // Rule ID 1303 // |
| 9337 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9337 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9338 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w, |
9338 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w, |
| 9339 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
9339 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 9340 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9340 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9341 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9341 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9342 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
9342 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 9343 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9343 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9344 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9344 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9345 |
// (intrinsic_wo_chain:{ *:[i32] } 5240:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
9345 |
// (intrinsic_wo_chain:{ *:[i32] } 5240:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 9346 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W_MMR2, |
9346 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W_MMR2, |
| 9347 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9347 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9348 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9348 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9349 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9349 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9350 |
GIR_EraseFromParent, /*InsnID*/0, |
9350 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9351 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9351 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9352 |
// GIR_Coverage, 1303, |
9352 |
// GIR_Coverage, 1303, |
| 9353 |
GIR_Done, |
9353 |
GIR_Done, |
| 9354 |
// Label 657: @21804 |
9354 |
// Label 657: @21804 |
| 9355 |
GIM_Try, /*On fail goto*//*Label 658*/ 21856, // Rule ID 1306 // |
9355 |
GIM_Try, /*On fail goto*//*Label 658*/ 21856, // Rule ID 1306 // |
| 9356 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9356 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9357 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb, |
9357 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb, |
| 9358 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
9358 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 9359 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
9359 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 9360 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
9360 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 9361 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9361 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9362 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9362 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9363 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9363 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9364 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5259:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
9364 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5259:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 9365 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB_MMR2, |
9365 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB_MMR2, |
| 9366 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9366 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9367 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9367 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9368 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9368 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9369 |
GIR_EraseFromParent, /*InsnID*/0, |
9369 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9370 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9370 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9371 |
// GIR_Coverage, 1306, |
9371 |
// GIR_Coverage, 1306, |
| 9372 |
GIR_Done, |
9372 |
GIR_Done, |
| 9373 |
// Label 658: @21856 |
9373 |
// Label 658: @21856 |
| 9374 |
GIM_Try, /*On fail goto*//*Label 659*/ 21908, // Rule ID 1307 // |
9374 |
GIM_Try, /*On fail goto*//*Label 659*/ 21908, // Rule ID 1307 // |
| 9375 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9375 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9376 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb, |
9376 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb, |
| 9377 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
9377 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 9378 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
9378 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 9379 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
9379 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 9380 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9380 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9381 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9381 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9382 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9382 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9383 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5260:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
9383 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5260:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 9384 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB_MMR2, |
9384 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB_MMR2, |
| 9385 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9385 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9386 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9386 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9387 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9387 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9388 |
GIR_EraseFromParent, /*InsnID*/0, |
9388 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9389 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9389 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9390 |
// GIR_Coverage, 1307, |
9390 |
// GIR_Coverage, 1307, |
| 9391 |
GIR_Done, |
9391 |
GIR_Done, |
| 9392 |
// Label 659: @21908 |
9392 |
// Label 659: @21908 |
| 9393 |
GIM_Try, /*On fail goto*//*Label 660*/ 21960, // Rule ID 1313 // |
9393 |
GIM_Try, /*On fail goto*//*Label 660*/ 21960, // Rule ID 1313 // |
| 9394 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9394 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9395 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb, |
9395 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb, |
| 9396 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
9396 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 9397 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
9397 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 9398 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9398 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9399 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9399 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9400 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9400 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9401 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9401 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9402 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5787:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
9402 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5787:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 9403 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB_MMR2, |
9403 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB_MMR2, |
| 9404 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9404 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9405 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
9405 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 9406 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9406 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9407 |
GIR_EraseFromParent, /*InsnID*/0, |
9407 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9408 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9408 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9409 |
// GIR_Coverage, 1313, |
9409 |
// GIR_Coverage, 1313, |
| 9410 |
GIR_Done, |
9410 |
GIR_Done, |
| 9411 |
// Label 660: @21960 |
9411 |
// Label 660: @21960 |
| 9412 |
GIM_Try, /*On fail goto*//*Label 661*/ 22012, // Rule ID 1314 // |
9412 |
GIM_Try, /*On fail goto*//*Label 661*/ 22012, // Rule ID 1314 // |
| 9413 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9413 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9414 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb, |
9414 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb, |
| 9415 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
9415 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 9416 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
9416 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 9417 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9417 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9418 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9418 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9419 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9419 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9420 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9420 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9421 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5789:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
9421 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5789:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 9422 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB_MMR2, |
9422 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB_MMR2, |
| 9423 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9423 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9424 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
9424 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 9425 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9425 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9426 |
GIR_EraseFromParent, /*InsnID*/0, |
9426 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9427 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9427 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9428 |
// GIR_Coverage, 1314, |
9428 |
// GIR_Coverage, 1314, |
| 9429 |
GIR_Done, |
9429 |
GIR_Done, |
| 9430 |
// Label 661: @22012 |
9430 |
// Label 661: @22012 |
| 9431 |
GIM_Try, /*On fail goto*//*Label 662*/ 22064, // Rule ID 1319 // |
9431 |
GIM_Try, /*On fail goto*//*Label 662*/ 22064, // Rule ID 1319 // |
| 9432 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9432 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9433 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph, |
9433 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph, |
| 9434 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9434 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9435 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
9435 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9436 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9436 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9437 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9437 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9438 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9438 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9439 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9439 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9440 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5791:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
9440 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5791:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 9441 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH_MMR2, |
9441 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH_MMR2, |
| 9442 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9442 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9443 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
9443 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 9444 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9444 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9445 |
GIR_EraseFromParent, /*InsnID*/0, |
9445 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9446 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9446 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9447 |
// GIR_Coverage, 1319, |
9447 |
// GIR_Coverage, 1319, |
| 9448 |
GIR_Done, |
9448 |
GIR_Done, |
| 9449 |
// Label 662: @22064 |
9449 |
// Label 662: @22064 |
| 9450 |
GIM_Try, /*On fail goto*//*Label 663*/ 22116, // Rule ID 1320 // |
9450 |
GIM_Try, /*On fail goto*//*Label 663*/ 22116, // Rule ID 1320 // |
| 9451 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9451 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9452 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph, |
9452 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph, |
| 9453 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9453 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9454 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
9454 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9455 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
9455 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 9456 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9456 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9457 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9457 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9458 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9458 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9459 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5858:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
9459 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5858:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 9460 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH_MMR2, |
9460 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH_MMR2, |
| 9461 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9461 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9462 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9462 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9463 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9463 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9464 |
GIR_EraseFromParent, /*InsnID*/0, |
9464 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9465 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9465 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9466 |
// GIR_Coverage, 1320, |
9466 |
// GIR_Coverage, 1320, |
| 9467 |
GIR_Done, |
9467 |
GIR_Done, |
| 9468 |
// Label 663: @22116 |
9468 |
// Label 663: @22116 |
| 9469 |
GIM_Try, /*On fail goto*//*Label 664*/ 22168, // Rule ID 1321 // |
9469 |
GIM_Try, /*On fail goto*//*Label 664*/ 22168, // Rule ID 1321 // |
| 9470 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9470 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9471 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph, |
9471 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph, |
| 9472 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9472 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9473 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
9473 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9474 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
9474 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 9475 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9475 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9476 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9476 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9477 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9477 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9478 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5859:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
9478 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5859:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 9479 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH_MMR2, |
9479 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH_MMR2, |
| 9480 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9480 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9481 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9481 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9482 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9482 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9483 |
GIR_EraseFromParent, /*InsnID*/0, |
9483 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9484 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9484 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9485 |
// GIR_Coverage, 1321, |
9485 |
// GIR_Coverage, 1321, |
| 9486 |
GIR_Done, |
9486 |
GIR_Done, |
| 9487 |
// Label 664: @22168 |
9487 |
// Label 664: @22168 |
| 9488 |
GIM_Try, /*On fail goto*//*Label 665*/ 22220, // Rule ID 1322 // |
9488 |
GIM_Try, /*On fail goto*//*Label 665*/ 22220, // Rule ID 1322 // |
| 9489 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9489 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9490 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w, |
9490 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w, |
| 9491 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
9491 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 9492 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9492 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9493 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9493 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9494 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
9494 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 9495 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9495 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9496 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9496 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9497 |
// (intrinsic_wo_chain:{ *:[i32] } 5861:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
9497 |
// (intrinsic_wo_chain:{ *:[i32] } 5861:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 9498 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W_MMR2, |
9498 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W_MMR2, |
| 9499 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9499 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9500 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9500 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9501 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9501 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9502 |
GIR_EraseFromParent, /*InsnID*/0, |
9502 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9503 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9503 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9504 |
// GIR_Coverage, 1322, |
9504 |
// GIR_Coverage, 1322, |
| 9505 |
GIR_Done, |
9505 |
GIR_Done, |
| 9506 |
// Label 665: @22220 |
9506 |
// Label 665: @22220 |
| 9507 |
GIM_Try, /*On fail goto*//*Label 666*/ 22272, // Rule ID 1323 // |
9507 |
GIM_Try, /*On fail goto*//*Label 666*/ 22272, // Rule ID 1323 // |
| 9508 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9508 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9509 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w, |
9509 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w, |
| 9510 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
9510 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 9511 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9511 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9512 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9512 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9513 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
9513 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 9514 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9514 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9515 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9515 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9516 |
// (intrinsic_wo_chain:{ *:[i32] } 5860:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
9516 |
// (intrinsic_wo_chain:{ *:[i32] } 5860:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 9517 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W_MMR2, |
9517 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W_MMR2, |
| 9518 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9518 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9519 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9519 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9520 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9520 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9521 |
GIR_EraseFromParent, /*InsnID*/0, |
9521 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9522 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9522 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9523 |
// GIR_Coverage, 1323, |
9523 |
// GIR_Coverage, 1323, |
| 9524 |
GIR_Done, |
9524 |
GIR_Done, |
| 9525 |
// Label 666: @22272 |
9525 |
// Label 666: @22272 |
| 9526 |
GIM_Try, /*On fail goto*//*Label 667*/ 22324, // Rule ID 1326 // |
9526 |
GIM_Try, /*On fail goto*//*Label 667*/ 22324, // Rule ID 1326 // |
| 9527 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9527 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9528 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb, |
9528 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb, |
| 9529 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
9529 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 9530 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
9530 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 9531 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
9531 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 9532 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9532 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9533 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9533 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9534 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9534 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9535 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5882:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
9535 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5882:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 9536 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB_MMR2, |
9536 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB_MMR2, |
| 9537 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9537 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9538 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9538 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9539 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9539 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9540 |
GIR_EraseFromParent, /*InsnID*/0, |
9540 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9541 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9541 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9542 |
// GIR_Coverage, 1326, |
9542 |
// GIR_Coverage, 1326, |
| 9543 |
GIR_Done, |
9543 |
GIR_Done, |
| 9544 |
// Label 667: @22324 |
9544 |
// Label 667: @22324 |
| 9545 |
GIM_Try, /*On fail goto*//*Label 668*/ 22376, // Rule ID 1327 // |
9545 |
GIM_Try, /*On fail goto*//*Label 668*/ 22376, // Rule ID 1327 // |
| 9546 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9546 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9547 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb, |
9547 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb, |
| 9548 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
9548 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 9549 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
9549 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 9550 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
9550 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 9551 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9551 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9552 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
9552 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 9553 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
9553 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 9554 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5883:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
9554 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5883:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 9555 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB_MMR2, |
9555 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB_MMR2, |
| 9556 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9556 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9557 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
9557 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 9558 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
9558 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 9559 |
GIR_EraseFromParent, /*InsnID*/0, |
9559 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9560 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9560 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9561 |
// GIR_Coverage, 1327, |
9561 |
// GIR_Coverage, 1327, |
| 9562 |
GIR_Done, |
9562 |
GIR_Done, |
| 9563 |
// Label 668: @22376 |
9563 |
// Label 668: @22376 |
| 9564 |
GIM_Try, /*On fail goto*//*Label 669*/ 22420, // Rule ID 1881 // |
9564 |
GIM_Try, /*On fail goto*//*Label 669*/ 22420, // Rule ID 1881 // |
| 9565 |
GIM_CheckFeatures, GIFBS_HasDSP, |
9565 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 9566 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_ph, |
9566 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_ph, |
| 9567 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9567 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9568 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
9568 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9569 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
9569 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 9570 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9570 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9571 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5235:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) |
9571 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5235:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) |
| 9572 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_PH, |
9572 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_PH, |
| 9573 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9573 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9574 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
9574 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 9575 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
9575 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
| 9576 |
GIR_EraseFromParent, /*InsnID*/0, |
9576 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9577 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9577 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9578 |
// GIR_Coverage, 1881, |
9578 |
// GIR_Coverage, 1881, |
| 9579 |
GIR_Done, |
9579 |
GIR_Done, |
| 9580 |
// Label 669: @22420 |
9580 |
// Label 669: @22420 |
| 9581 |
GIM_Try, /*On fail goto*//*Label 670*/ 22464, // Rule ID 1883 // |
9581 |
GIM_Try, /*On fail goto*//*Label 670*/ 22464, // Rule ID 1883 // |
| 9582 |
GIM_CheckFeatures, GIFBS_HasDSP, |
9582 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 9583 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_ph, |
9583 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_ph, |
| 9584 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9584 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9585 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
9585 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9586 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
9586 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 9587 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9587 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9588 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5855:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) |
9588 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5855:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) |
| 9589 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_PH, |
9589 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_PH, |
| 9590 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9590 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9591 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
9591 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 9592 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
9592 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
| 9593 |
GIR_EraseFromParent, /*InsnID*/0, |
9593 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9594 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9594 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9595 |
// GIR_Coverage, 1883, |
9595 |
// GIR_Coverage, 1883, |
| 9596 |
GIR_Done, |
9596 |
GIR_Done, |
| 9597 |
// Label 670: @22464 |
9597 |
// Label 670: @22464 |
| 9598 |
GIM_Try, /*On fail goto*//*Label 671*/ 22508, // Rule ID 1887 // |
9598 |
GIM_Try, /*On fail goto*//*Label 671*/ 22508, // Rule ID 1887 // |
| 9599 |
GIM_CheckFeatures, GIFBS_HasDSP, |
9599 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 9600 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_qb, |
9600 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_qb, |
| 9601 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
9601 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 9602 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
9602 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 9603 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
9603 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 9604 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9604 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9605 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5256:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) |
9605 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5256:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) |
| 9606 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_QB, |
9606 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_QB, |
| 9607 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9607 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9608 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
9608 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 9609 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
9609 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
| 9610 |
GIR_EraseFromParent, /*InsnID*/0, |
9610 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9611 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9611 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9612 |
// GIR_Coverage, 1887, |
9612 |
// GIR_Coverage, 1887, |
| 9613 |
GIR_Done, |
9613 |
GIR_Done, |
| 9614 |
// Label 671: @22508 |
9614 |
// Label 671: @22508 |
| 9615 |
GIM_Try, /*On fail goto*//*Label 672*/ 22552, // Rule ID 1889 // |
9615 |
GIM_Try, /*On fail goto*//*Label 672*/ 22552, // Rule ID 1889 // |
| 9616 |
GIM_CheckFeatures, GIFBS_HasDSP, |
9616 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 9617 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_qb, |
9617 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_qb, |
| 9618 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
9618 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 9619 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
9619 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 9620 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
9620 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 9621 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9621 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9622 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5879:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) |
9622 |
// (intrinsic_wo_chain:{ *:[v4i8] } 5879:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) |
| 9623 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_QB, |
9623 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_QB, |
| 9624 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
9624 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 9625 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
9625 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 9626 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
9626 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
| 9627 |
GIR_EraseFromParent, /*InsnID*/0, |
9627 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9628 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9628 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9629 |
// GIR_Coverage, 1889, |
9629 |
// GIR_Coverage, 1889, |
| 9630 |
GIR_Done, |
9630 |
GIR_Done, |
| 9631 |
// Label 672: @22552 |
9631 |
// Label 672: @22552 |
| 9632 |
GIM_Reject, |
9632 |
GIM_Reject, |
| 9633 |
// Label 458: @22553 |
9633 |
// Label 458: @22553 |
| 9634 |
GIM_Try, /*On fail goto*//*Label 673*/ 25493, |
9634 |
GIM_Try, /*On fail goto*//*Label 673*/ 25493, |
| 9635 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
9635 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 9636 |
GIM_Try, /*On fail goto*//*Label 674*/ 22621, // Rule ID 465 // |
9636 |
GIM_Try, /*On fail goto*//*Label 674*/ 22621, // Rule ID 465 // |
| 9637 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
9637 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 9638 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w, |
9638 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w, |
| 9639 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9639 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9640 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9640 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9641 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9641 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9642 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9642 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9643 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9643 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9644 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9644 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9645 |
// MIs[0] sa |
9645 |
// MIs[0] sa |
| 9646 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
9646 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9647 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
9647 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
| 9648 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5759:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
9648 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5759:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
| 9649 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W, |
9649 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W, |
| 9650 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
9650 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 9651 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9651 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9652 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
9652 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
| 9653 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
9653 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 9654 |
GIR_EraseFromParent, /*InsnID*/0, |
9654 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9655 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9655 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9656 |
// GIR_Coverage, 465, |
9656 |
// GIR_Coverage, 465, |
| 9657 |
GIR_Done, |
9657 |
GIR_Done, |
| 9658 |
// Label 674: @22621 |
9658 |
// Label 674: @22621 |
| 9659 |
GIM_Try, /*On fail goto*//*Label 675*/ 22684, // Rule ID 466 // |
9659 |
GIM_Try, /*On fail goto*//*Label 675*/ 22684, // Rule ID 466 // |
| 9660 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
9660 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 9661 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w, |
9661 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w, |
| 9662 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9662 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9663 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9663 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9664 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9664 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9665 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9665 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9666 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9666 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9667 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9667 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9668 |
// MIs[0] sa |
9668 |
// MIs[0] sa |
| 9669 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
9669 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9670 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
9670 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
| 9671 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5760:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
9671 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5760:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
| 9672 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W, |
9672 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W, |
| 9673 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
9673 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 9674 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9674 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9675 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
9675 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
| 9676 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
9676 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 9677 |
GIR_EraseFromParent, /*InsnID*/0, |
9677 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9678 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9678 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9679 |
// GIR_Coverage, 466, |
9679 |
// GIR_Coverage, 466, |
| 9680 |
GIR_Done, |
9680 |
GIR_Done, |
| 9681 |
// Label 675: @22684 |
9681 |
// Label 675: @22684 |
| 9682 |
GIM_Try, /*On fail goto*//*Label 676*/ 22747, // Rule ID 471 // |
9682 |
GIM_Try, /*On fail goto*//*Label 676*/ 22747, // Rule ID 471 // |
| 9683 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
9683 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 9684 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append, |
9684 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append, |
| 9685 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
9685 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 9686 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9686 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9687 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9687 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9688 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
9688 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 9689 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9689 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9690 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9690 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9691 |
// MIs[0] sa |
9691 |
// MIs[0] sa |
| 9692 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
9692 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9693 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
9693 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
| 9694 |
// (intrinsic_wo_chain:{ *:[i32] } 5272:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
9694 |
// (intrinsic_wo_chain:{ *:[i32] } 5272:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
| 9695 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND, |
9695 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND, |
| 9696 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
9696 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 9697 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9697 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9698 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
9698 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
| 9699 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
9699 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 9700 |
GIR_EraseFromParent, /*InsnID*/0, |
9700 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9701 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9701 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9702 |
// GIR_Coverage, 471, |
9702 |
// GIR_Coverage, 471, |
| 9703 |
GIR_Done, |
9703 |
GIR_Done, |
| 9704 |
// Label 676: @22747 |
9704 |
// Label 676: @22747 |
| 9705 |
GIM_Try, /*On fail goto*//*Label 677*/ 22810, // Rule ID 472 // |
9705 |
GIM_Try, /*On fail goto*//*Label 677*/ 22810, // Rule ID 472 // |
| 9706 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
9706 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 9707 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign, |
9707 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign, |
| 9708 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
9708 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 9709 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9709 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9710 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9710 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9711 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
9711 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 9712 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9712 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9713 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9713 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9714 |
// MIs[0] sa |
9714 |
// MIs[0] sa |
| 9715 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
9715 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9716 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt2, |
9716 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt2, |
| 9717 |
// (intrinsic_wo_chain:{ *:[i32] } 5297:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
9717 |
// (intrinsic_wo_chain:{ *:[i32] } 5297:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
| 9718 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN, |
9718 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN, |
| 9719 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
9719 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 9720 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9720 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9721 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
9721 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
| 9722 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
9722 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 9723 |
GIR_EraseFromParent, /*InsnID*/0, |
9723 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9724 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9724 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9725 |
// GIR_Coverage, 472, |
9725 |
// GIR_Coverage, 472, |
| 9726 |
GIR_Done, |
9726 |
GIR_Done, |
| 9727 |
// Label 677: @22810 |
9727 |
// Label 677: @22810 |
| 9728 |
GIM_Try, /*On fail goto*//*Label 678*/ 22873, // Rule ID 473 // |
9728 |
GIM_Try, /*On fail goto*//*Label 678*/ 22873, // Rule ID 473 // |
| 9729 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
9729 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 9730 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend, |
9730 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend, |
| 9731 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
9731 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 9732 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9732 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9733 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9733 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9734 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
9734 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 9735 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9735 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9736 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9736 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9737 |
// MIs[0] sa |
9737 |
// MIs[0] sa |
| 9738 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
9738 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9739 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
9739 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
| 9740 |
// (intrinsic_wo_chain:{ *:[i32] } 5765:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
9740 |
// (intrinsic_wo_chain:{ *:[i32] } 5765:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
| 9741 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND, |
9741 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND, |
| 9742 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
9742 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 9743 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9743 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9744 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
9744 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
| 9745 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
9745 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 9746 |
GIR_EraseFromParent, /*InsnID*/0, |
9746 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9747 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9747 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9748 |
// GIR_Coverage, 473, |
9748 |
// GIR_Coverage, 473, |
| 9749 |
GIR_Done, |
9749 |
GIR_Done, |
| 9750 |
// Label 678: @22873 |
9750 |
// Label 678: @22873 |
| 9751 |
GIM_Try, /*On fail goto*//*Label 679*/ 22936, // Rule ID 941 // |
9751 |
GIM_Try, /*On fail goto*//*Label 679*/ 22936, // Rule ID 941 // |
| 9752 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
9752 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 9753 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_b, |
9753 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_b, |
| 9754 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
9754 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 9755 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
9755 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9756 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
9756 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 9757 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
9757 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 9758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
9758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 9759 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
9759 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 9760 |
// MIs[0] n |
9760 |
// MIs[0] n |
| 9761 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
9761 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9762 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt4, |
9762 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt4, |
| 9763 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5797:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<>:$n) => (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$n) |
9763 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5797:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<>:$n) => (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$n) |
| 9764 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_B, |
9764 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_B, |
| 9765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
9765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 9766 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
9766 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 9767 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
9767 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 9768 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n |
9768 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n |
| 9769 |
GIR_EraseFromParent, /*InsnID*/0, |
9769 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9770 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9770 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9771 |
// GIR_Coverage, 941, |
9771 |
// GIR_Coverage, 941, |
| 9772 |
GIR_Done, |
9772 |
GIR_Done, |
| 9773 |
// Label 679: @22936 |
9773 |
// Label 679: @22936 |
| 9774 |
GIM_Try, /*On fail goto*//*Label 680*/ 22999, // Rule ID 942 // |
9774 |
GIM_Try, /*On fail goto*//*Label 680*/ 22999, // Rule ID 942 // |
| 9775 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
9775 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 9776 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_h, |
9776 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_h, |
| 9777 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
9777 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 9778 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
9778 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9779 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
9779 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 9780 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
9780 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 9781 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
9781 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 9782 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
9782 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 9783 |
// MIs[0] n |
9783 |
// MIs[0] n |
| 9784 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
9784 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9785 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt3, |
9785 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt3, |
| 9786 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5799:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<>:$n) => (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$n) |
9786 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5799:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<>:$n) => (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$n) |
| 9787 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_H, |
9787 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_H, |
| 9788 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
9788 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 9789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
9789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 9790 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
9790 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 9791 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n |
9791 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n |
| 9792 |
GIR_EraseFromParent, /*InsnID*/0, |
9792 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9793 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9793 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9794 |
// GIR_Coverage, 942, |
9794 |
// GIR_Coverage, 942, |
| 9795 |
GIR_Done, |
9795 |
GIR_Done, |
| 9796 |
// Label 680: @22999 |
9796 |
// Label 680: @22999 |
| 9797 |
GIM_Try, /*On fail goto*//*Label 681*/ 23062, // Rule ID 943 // |
9797 |
GIM_Try, /*On fail goto*//*Label 681*/ 23062, // Rule ID 943 // |
| 9798 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
9798 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 9799 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_w, |
9799 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_w, |
| 9800 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
9800 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 9801 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
9801 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9802 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
9802 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 9803 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
9803 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 9804 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
9804 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 9805 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
9805 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 9806 |
// MIs[0] n |
9806 |
// MIs[0] n |
| 9807 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
9807 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9808 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt2, |
9808 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt2, |
| 9809 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5800:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<>:$n) => (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$n) |
9809 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5800:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<>:$n) => (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$n) |
| 9810 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_W, |
9810 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_W, |
| 9811 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
9811 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 9812 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
9812 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 9813 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
9813 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 9814 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n |
9814 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n |
| 9815 |
GIR_EraseFromParent, /*InsnID*/0, |
9815 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9816 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9816 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9817 |
// GIR_Coverage, 943, |
9817 |
// GIR_Coverage, 943, |
| 9818 |
GIR_Done, |
9818 |
GIR_Done, |
| 9819 |
// Label 681: @23062 |
9819 |
// Label 681: @23062 |
| 9820 |
GIM_Try, /*On fail goto*//*Label 682*/ 23125, // Rule ID 944 // |
9820 |
GIM_Try, /*On fail goto*//*Label 682*/ 23125, // Rule ID 944 // |
| 9821 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
9821 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 9822 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_d, |
9822 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_d, |
| 9823 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
9823 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 9824 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
9824 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9825 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
9825 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 9826 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
9826 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 9827 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
9827 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 9828 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
9828 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 9829 |
// MIs[0] n |
9829 |
// MIs[0] n |
| 9830 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
9830 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9831 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt1, |
9831 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt1, |
| 9832 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5798:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<>:$n) => (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$n) |
9832 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5798:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<>:$n) => (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$n) |
| 9833 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_D, |
9833 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_D, |
| 9834 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
9834 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 9835 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
9835 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 9836 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
9836 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 9837 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n |
9837 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // n |
| 9838 |
GIR_EraseFromParent, /*InsnID*/0, |
9838 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9839 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9839 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9840 |
// GIR_Coverage, 944, |
9840 |
// GIR_Coverage, 944, |
| 9841 |
GIR_Done, |
9841 |
GIR_Done, |
| 9842 |
// Label 682: @23125 |
9842 |
// Label 682: @23125 |
| 9843 |
GIM_Try, /*On fail goto*//*Label 683*/ 23188, // Rule ID 1337 // |
9843 |
GIM_Try, /*On fail goto*//*Label 683*/ 23188, // Rule ID 1337 // |
| 9844 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9844 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9845 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w, |
9845 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w, |
| 9846 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9846 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9847 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9847 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9848 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9848 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9849 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9849 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9850 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9850 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9851 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9851 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9852 |
// MIs[0] sa |
9852 |
// MIs[0] sa |
| 9853 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
9853 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9854 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
9854 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
| 9855 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5759:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
9855 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5759:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
| 9856 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W_MMR2, |
9856 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W_MMR2, |
| 9857 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
9857 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 9858 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9858 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9859 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
9859 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
| 9860 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
9860 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 9861 |
GIR_EraseFromParent, /*InsnID*/0, |
9861 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9862 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9862 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9863 |
// GIR_Coverage, 1337, |
9863 |
// GIR_Coverage, 1337, |
| 9864 |
GIR_Done, |
9864 |
GIR_Done, |
| 9865 |
// Label 683: @23188 |
9865 |
// Label 683: @23188 |
| 9866 |
GIM_Try, /*On fail goto*//*Label 684*/ 23251, // Rule ID 1338 // |
9866 |
GIM_Try, /*On fail goto*//*Label 684*/ 23251, // Rule ID 1338 // |
| 9867 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9867 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9868 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w, |
9868 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w, |
| 9869 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
9869 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9870 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9870 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9871 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9871 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9872 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
9872 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 9873 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9873 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9874 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9874 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9875 |
// MIs[0] sa |
9875 |
// MIs[0] sa |
| 9876 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
9876 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9877 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
9877 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
| 9878 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5760:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
9878 |
// (intrinsic_wo_chain:{ *:[v2i16] } 5760:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
| 9879 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W_MMR2, |
9879 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W_MMR2, |
| 9880 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
9880 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 9881 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9881 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9882 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
9882 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
| 9883 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
9883 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 9884 |
GIR_EraseFromParent, /*InsnID*/0, |
9884 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9885 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9885 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9886 |
// GIR_Coverage, 1338, |
9886 |
// GIR_Coverage, 1338, |
| 9887 |
GIR_Done, |
9887 |
GIR_Done, |
| 9888 |
// Label 684: @23251 |
9888 |
// Label 684: @23251 |
| 9889 |
GIM_Try, /*On fail goto*//*Label 685*/ 23314, // Rule ID 1339 // |
9889 |
GIM_Try, /*On fail goto*//*Label 685*/ 23314, // Rule ID 1339 // |
| 9890 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9890 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9891 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend, |
9891 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend, |
| 9892 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
9892 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 9893 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9893 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9894 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9894 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9895 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
9895 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 9896 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9896 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9897 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9897 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9898 |
// MIs[0] sa |
9898 |
// MIs[0] sa |
| 9899 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
9899 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9900 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
9900 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
| 9901 |
// (intrinsic_wo_chain:{ *:[i32] } 5765:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
9901 |
// (intrinsic_wo_chain:{ *:[i32] } 5765:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
| 9902 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND_MMR2, |
9902 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND_MMR2, |
| 9903 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
9903 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 9904 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9904 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9905 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
9905 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
| 9906 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
9906 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 9907 |
GIR_EraseFromParent, /*InsnID*/0, |
9907 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9908 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9908 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9909 |
// GIR_Coverage, 1339, |
9909 |
// GIR_Coverage, 1339, |
| 9910 |
GIR_Done, |
9910 |
GIR_Done, |
| 9911 |
// Label 685: @23314 |
9911 |
// Label 685: @23314 |
| 9912 |
GIM_Try, /*On fail goto*//*Label 686*/ 23377, // Rule ID 1340 // |
9912 |
GIM_Try, /*On fail goto*//*Label 686*/ 23377, // Rule ID 1340 // |
| 9913 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9913 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9914 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append, |
9914 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append, |
| 9915 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
9915 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 9916 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9916 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9917 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9917 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9918 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
9918 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 9919 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9919 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9920 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9920 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9921 |
// MIs[0] sa |
9921 |
// MIs[0] sa |
| 9922 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
9922 |
GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 9923 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
9923 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GICXXPred_I64_Predicate_timmZExt5, |
| 9924 |
// (intrinsic_wo_chain:{ *:[i32] } 5272:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
9924 |
// (intrinsic_wo_chain:{ *:[i32] } 5272:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$sa) => (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src) |
| 9925 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND_MMR2, |
9925 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND_MMR2, |
| 9926 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
9926 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 9927 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9927 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9928 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
9928 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // sa |
| 9929 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
9929 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 9930 |
GIR_EraseFromParent, /*InsnID*/0, |
9930 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9931 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9931 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9932 |
// GIR_Coverage, 1340, |
9932 |
// GIR_Coverage, 1340, |
| 9933 |
GIR_Done, |
9933 |
GIR_Done, |
| 9934 |
// Label 686: @23377 |
9934 |
// Label 686: @23377 |
| 9935 |
GIM_Try, /*On fail goto*//*Label 687*/ 23444, // Rule ID 1315 // |
9935 |
GIM_Try, /*On fail goto*//*Label 687*/ 23444, // Rule ID 1315 // |
| 9936 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
9936 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 9937 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign, |
9937 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign, |
| 9938 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
9938 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 9939 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
9939 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 9940 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
9940 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 9941 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
9941 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 9942 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
9942 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 9943 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
9943 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 9944 |
// MIs[0] bp |
9944 |
// MIs[0] bp |
| 9945 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
9945 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 9946 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
9946 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 9947 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt2, |
9947 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt2, |
| 9948 |
// MIs[1] Operand 1 |
9948 |
// MIs[1] Operand 1 |
| 9949 |
// No operand predicates |
9949 |
// No operand predicates |
| 9950 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
9950 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 9951 |
// (intrinsic_wo_chain:{ *:[i32] } 5297:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$bp) => (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src) |
9951 |
// (intrinsic_wo_chain:{ *:[i32] } 5297:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$bp) => (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src) |
| 9952 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN_MMR2, |
9952 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN_MMR2, |
| 9953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
9953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 9954 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
9954 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 9955 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp |
9955 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp |
| 9956 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
9956 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 9957 |
GIR_EraseFromParent, /*InsnID*/0, |
9957 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9958 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9958 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9959 |
// GIR_Coverage, 1315, |
9959 |
// GIR_Coverage, 1315, |
| 9960 |
GIR_Done, |
9960 |
GIR_Done, |
| 9961 |
// Label 687: @23444 |
9961 |
// Label 687: @23444 |
| 9962 |
GIM_Try, /*On fail goto*//*Label 688*/ 23508, // Rule ID 540 // |
9962 |
GIM_Try, /*On fail goto*//*Label 688*/ 23508, // Rule ID 540 // |
| 9963 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
9963 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 9964 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_b, |
9964 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_b, |
| 9965 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
9965 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 9966 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
9966 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9967 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
9967 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 9968 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
9968 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 9969 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
9969 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 9970 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
9970 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 9971 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
9971 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 9972 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, |
9972 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, |
| 9973 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5306:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
9973 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5306:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 9974 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_B, |
9974 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_B, |
| 9975 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
9975 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 9976 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
9976 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 9977 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
9977 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 9978 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
9978 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 9979 |
GIR_EraseFromParent, /*InsnID*/0, |
9979 |
GIR_EraseFromParent, /*InsnID*/0, |
| 9980 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
9980 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 9981 |
// GIR_Coverage, 540, |
9981 |
// GIR_Coverage, 540, |
| 9982 |
GIR_Done, |
9982 |
GIR_Done, |
| 9983 |
// Label 688: @23508 |
9983 |
// Label 688: @23508 |
| 9984 |
GIM_Try, /*On fail goto*//*Label 689*/ 23572, // Rule ID 541 // |
9984 |
GIM_Try, /*On fail goto*//*Label 689*/ 23572, // Rule ID 541 // |
| 9985 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
9985 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 9986 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_h, |
9986 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_h, |
| 9987 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
9987 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 9988 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
9988 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9989 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
9989 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 9990 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
9990 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 9991 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
9991 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 9992 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
9992 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 9993 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
9993 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 9994 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
9994 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
| 9995 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5308:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
9995 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5308:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 9996 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_H, |
9996 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_H, |
| 9997 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
9997 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 9998 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
9998 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 9999 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
9999 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10000 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10000 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10001 |
GIR_EraseFromParent, /*InsnID*/0, |
10001 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10002 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10002 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10003 |
// GIR_Coverage, 541, |
10003 |
// GIR_Coverage, 541, |
| 10004 |
GIR_Done, |
10004 |
GIR_Done, |
| 10005 |
// Label 689: @23572 |
10005 |
// Label 689: @23572 |
| 10006 |
GIM_Try, /*On fail goto*//*Label 690*/ 23636, // Rule ID 542 // |
10006 |
GIM_Try, /*On fail goto*//*Label 690*/ 23636, // Rule ID 542 // |
| 10007 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10007 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10008 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_w, |
10008 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_w, |
| 10009 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
10009 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10010 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
10010 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10011 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
10011 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10012 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
10012 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 10013 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
10013 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 10014 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
10014 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 10015 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
10015 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 10016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
10016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
| 10017 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5309:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
10017 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5309:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 10018 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_W, |
10018 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_W, |
| 10019 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10019 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10020 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10020 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10021 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10021 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10022 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10022 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10023 |
GIR_EraseFromParent, /*InsnID*/0, |
10023 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10024 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10024 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10025 |
// GIR_Coverage, 542, |
10025 |
// GIR_Coverage, 542, |
| 10026 |
GIR_Done, |
10026 |
GIR_Done, |
| 10027 |
// Label 690: @23636 |
10027 |
// Label 690: @23636 |
| 10028 |
GIM_Try, /*On fail goto*//*Label 691*/ 23700, // Rule ID 543 // |
10028 |
GIM_Try, /*On fail goto*//*Label 691*/ 23700, // Rule ID 543 // |
| 10029 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10029 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10030 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_d, |
10030 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_d, |
| 10031 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
10031 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 10032 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
10032 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10033 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
10033 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 10034 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, |
10034 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, |
| 10035 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
10035 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 10036 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
10036 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 10037 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
10037 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 10038 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID, |
10038 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID, |
| 10039 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5307:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
10039 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5307:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 10040 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_D, |
10040 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_D, |
| 10041 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10041 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10042 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10042 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10043 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10043 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10044 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10044 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10045 |
GIR_EraseFromParent, /*InsnID*/0, |
10045 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10046 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10046 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10047 |
// GIR_Coverage, 543, |
10047 |
// GIR_Coverage, 543, |
| 10048 |
GIR_Done, |
10048 |
GIR_Done, |
| 10049 |
// Label 691: @23700 |
10049 |
// Label 691: @23700 |
| 10050 |
GIM_Try, /*On fail goto*//*Label 692*/ 23764, // Rule ID 548 // |
10050 |
GIM_Try, /*On fail goto*//*Label 692*/ 23764, // Rule ID 548 // |
| 10051 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10051 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10052 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_b, |
10052 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_b, |
| 10053 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
10053 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 10054 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
10054 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10055 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
10055 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10056 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
10056 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10057 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
10057 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 10058 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
10058 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 10059 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
10059 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 10060 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, |
10060 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, |
| 10061 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5314:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
10061 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5314:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 10062 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_B, |
10062 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_B, |
| 10063 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10063 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10064 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10064 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10065 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10065 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10066 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10066 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10067 |
GIR_EraseFromParent, /*InsnID*/0, |
10067 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10068 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10068 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10069 |
// GIR_Coverage, 548, |
10069 |
// GIR_Coverage, 548, |
| 10070 |
GIR_Done, |
10070 |
GIR_Done, |
| 10071 |
// Label 692: @23764 |
10071 |
// Label 692: @23764 |
| 10072 |
GIM_Try, /*On fail goto*//*Label 693*/ 23828, // Rule ID 549 // |
10072 |
GIM_Try, /*On fail goto*//*Label 693*/ 23828, // Rule ID 549 // |
| 10073 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10073 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10074 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_h, |
10074 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_h, |
| 10075 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
10075 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 10076 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
10076 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10077 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
10077 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 10078 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
10078 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 10079 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
10079 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 10080 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
10080 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 10081 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
10081 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 10082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
10082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
| 10083 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5316:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
10083 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5316:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 10084 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_H, |
10084 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_H, |
| 10085 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10085 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10087 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10087 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10088 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10088 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10089 |
GIR_EraseFromParent, /*InsnID*/0, |
10089 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10090 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10090 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10091 |
// GIR_Coverage, 549, |
10091 |
// GIR_Coverage, 549, |
| 10092 |
GIR_Done, |
10092 |
GIR_Done, |
| 10093 |
// Label 693: @23828 |
10093 |
// Label 693: @23828 |
| 10094 |
GIM_Try, /*On fail goto*//*Label 694*/ 23892, // Rule ID 550 // |
10094 |
GIM_Try, /*On fail goto*//*Label 694*/ 23892, // Rule ID 550 // |
| 10095 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10095 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10096 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_w, |
10096 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_w, |
| 10097 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
10097 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10098 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
10098 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10099 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
10099 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10100 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
10100 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 10101 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
10101 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 10102 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
10102 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 10103 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
10103 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 10104 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
10104 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
| 10105 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5317:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
10105 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5317:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 10106 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_W, |
10106 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_W, |
| 10107 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10107 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10108 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10108 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10109 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10109 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10110 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10110 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10111 |
GIR_EraseFromParent, /*InsnID*/0, |
10111 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10112 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10112 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10113 |
// GIR_Coverage, 550, |
10113 |
// GIR_Coverage, 550, |
| 10114 |
GIR_Done, |
10114 |
GIR_Done, |
| 10115 |
// Label 694: @23892 |
10115 |
// Label 694: @23892 |
| 10116 |
GIM_Try, /*On fail goto*//*Label 695*/ 23956, // Rule ID 551 // |
10116 |
GIM_Try, /*On fail goto*//*Label 695*/ 23956, // Rule ID 551 // |
| 10117 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10117 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10118 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_d, |
10118 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_d, |
| 10119 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
10119 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 10120 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
10120 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10121 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
10121 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 10122 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, |
10122 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, |
| 10123 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
10123 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 10124 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
10124 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 10125 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
10125 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 10126 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID, |
10126 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID, |
| 10127 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5315:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
10127 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5315:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 10128 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_D, |
10128 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_D, |
| 10129 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10129 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10130 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10130 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10131 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10131 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10132 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10132 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10133 |
GIR_EraseFromParent, /*InsnID*/0, |
10133 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10134 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10134 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10135 |
// GIR_Coverage, 551, |
10135 |
// GIR_Coverage, 551, |
| 10136 |
GIR_Done, |
10136 |
GIR_Done, |
| 10137 |
// Label 695: @23956 |
10137 |
// Label 695: @23956 |
| 10138 |
GIM_Try, /*On fail goto*//*Label 696*/ 24020, // Rule ID 646 // |
10138 |
GIM_Try, /*On fail goto*//*Label 696*/ 24020, // Rule ID 646 // |
| 10139 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10139 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10140 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_h, |
10140 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_h, |
| 10141 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
10141 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 10142 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
10142 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10143 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
10143 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10144 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
10144 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10145 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
10145 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 10146 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
10146 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 10147 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
10147 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 10148 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, |
10148 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, |
| 10149 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5435:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
10149 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5435:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 10150 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_H, |
10150 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_H, |
| 10151 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10151 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10152 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10152 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10153 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10153 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10154 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10154 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10155 |
GIR_EraseFromParent, /*InsnID*/0, |
10155 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10156 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10156 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10157 |
// GIR_Coverage, 646, |
10157 |
// GIR_Coverage, 646, |
| 10158 |
GIR_Done, |
10158 |
GIR_Done, |
| 10159 |
// Label 696: @24020 |
10159 |
// Label 696: @24020 |
| 10160 |
GIM_Try, /*On fail goto*//*Label 697*/ 24084, // Rule ID 647 // |
10160 |
GIM_Try, /*On fail goto*//*Label 697*/ 24084, // Rule ID 647 // |
| 10161 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10161 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10162 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_w, |
10162 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_w, |
| 10163 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
10163 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10164 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
10164 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10165 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
10165 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 10166 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
10166 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 10167 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
10167 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 10168 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
10168 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 10169 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
10169 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 10170 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
10170 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
| 10171 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5436:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
10171 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5436:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 10172 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_W, |
10172 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_W, |
| 10173 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10173 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10174 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10174 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10175 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10175 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10176 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10176 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10177 |
GIR_EraseFromParent, /*InsnID*/0, |
10177 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10178 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10178 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10179 |
// GIR_Coverage, 647, |
10179 |
// GIR_Coverage, 647, |
| 10180 |
GIR_Done, |
10180 |
GIR_Done, |
| 10181 |
// Label 697: @24084 |
10181 |
// Label 697: @24084 |
| 10182 |
GIM_Try, /*On fail goto*//*Label 698*/ 24148, // Rule ID 648 // |
10182 |
GIM_Try, /*On fail goto*//*Label 698*/ 24148, // Rule ID 648 // |
| 10183 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10183 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10184 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_d, |
10184 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_d, |
| 10185 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
10185 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 10186 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
10186 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10187 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
10187 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10188 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
10188 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 10189 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
10189 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 10190 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
10190 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 10191 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
10191 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 10192 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
10192 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
| 10193 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5434:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
10193 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5434:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 10194 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_D, |
10194 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_D, |
| 10195 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10195 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10196 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10196 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10197 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10197 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10198 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10198 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10199 |
GIR_EraseFromParent, /*InsnID*/0, |
10199 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10200 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10200 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10201 |
// GIR_Coverage, 648, |
10201 |
// GIR_Coverage, 648, |
| 10202 |
GIR_Done, |
10202 |
GIR_Done, |
| 10203 |
// Label 698: @24148 |
10203 |
// Label 698: @24148 |
| 10204 |
GIM_Try, /*On fail goto*//*Label 699*/ 24212, // Rule ID 649 // |
10204 |
GIM_Try, /*On fail goto*//*Label 699*/ 24212, // Rule ID 649 // |
| 10205 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10205 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10206 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_h, |
10206 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_h, |
| 10207 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
10207 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 10208 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
10208 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10209 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
10209 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10210 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
10210 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
10211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 10212 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
10212 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 10213 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
10213 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 10214 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, |
10214 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, |
| 10215 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5438:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
10215 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5438:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 10216 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_H, |
10216 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_H, |
| 10217 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10217 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10218 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10218 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10219 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10219 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10220 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10220 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10221 |
GIR_EraseFromParent, /*InsnID*/0, |
10221 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10222 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10222 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10223 |
// GIR_Coverage, 649, |
10223 |
// GIR_Coverage, 649, |
| 10224 |
GIR_Done, |
10224 |
GIR_Done, |
| 10225 |
// Label 699: @24212 |
10225 |
// Label 699: @24212 |
| 10226 |
GIM_Try, /*On fail goto*//*Label 700*/ 24276, // Rule ID 650 // |
10226 |
GIM_Try, /*On fail goto*//*Label 700*/ 24276, // Rule ID 650 // |
| 10227 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10227 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10228 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_w, |
10228 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_w, |
| 10229 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
10229 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10230 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
10230 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10231 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
10231 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 10232 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
10232 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 10233 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
10233 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 10234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
10234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 10235 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
10235 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 10236 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
10236 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
| 10237 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5439:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
10237 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5439:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 10238 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_W, |
10238 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_W, |
| 10239 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10239 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10240 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10240 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10241 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10241 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10242 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10242 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10243 |
GIR_EraseFromParent, /*InsnID*/0, |
10243 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10244 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10244 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10245 |
// GIR_Coverage, 650, |
10245 |
// GIR_Coverage, 650, |
| 10246 |
GIR_Done, |
10246 |
GIR_Done, |
| 10247 |
// Label 700: @24276 |
10247 |
// Label 700: @24276 |
| 10248 |
GIM_Try, /*On fail goto*//*Label 701*/ 24340, // Rule ID 651 // |
10248 |
GIM_Try, /*On fail goto*//*Label 701*/ 24340, // Rule ID 651 // |
| 10249 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10249 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10250 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_d, |
10250 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_d, |
| 10251 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
10251 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 10252 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
10252 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10253 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
10253 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10254 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
10254 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 10255 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
10255 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 10256 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
10256 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 10257 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
10257 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 10258 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
10258 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
| 10259 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5437:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
10259 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5437:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 10260 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_D, |
10260 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_D, |
| 10261 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10261 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10262 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10262 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10263 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10263 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10264 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10264 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10265 |
GIR_EraseFromParent, /*InsnID*/0, |
10265 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10266 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10266 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10267 |
// GIR_Coverage, 651, |
10267 |
// GIR_Coverage, 651, |
| 10268 |
GIR_Done, |
10268 |
GIR_Done, |
| 10269 |
// Label 701: @24340 |
10269 |
// Label 701: @24340 |
| 10270 |
GIM_Try, /*On fail goto*//*Label 702*/ 24404, // Rule ID 652 // |
10270 |
GIM_Try, /*On fail goto*//*Label 702*/ 24404, // Rule ID 652 // |
| 10271 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10271 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10272 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_h, |
10272 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_h, |
| 10273 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
10273 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 10274 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
10274 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10275 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
10275 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10276 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
10276 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10277 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
10277 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 10278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
10278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 10279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
10279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 10280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, |
10280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, |
| 10281 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5455:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
10281 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5455:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 10282 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_H, |
10282 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_H, |
| 10283 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10283 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10284 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10284 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10285 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10285 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10286 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10286 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10287 |
GIR_EraseFromParent, /*InsnID*/0, |
10287 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10288 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10288 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10289 |
// GIR_Coverage, 652, |
10289 |
// GIR_Coverage, 652, |
| 10290 |
GIR_Done, |
10290 |
GIR_Done, |
| 10291 |
// Label 702: @24404 |
10291 |
// Label 702: @24404 |
| 10292 |
GIM_Try, /*On fail goto*//*Label 703*/ 24468, // Rule ID 653 // |
10292 |
GIM_Try, /*On fail goto*//*Label 703*/ 24468, // Rule ID 653 // |
| 10293 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10293 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10294 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_w, |
10294 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_w, |
| 10295 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
10295 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10296 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
10296 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10297 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
10297 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 10298 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
10298 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 10299 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
10299 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 10300 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
10300 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 10301 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
10301 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 10302 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
10302 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
| 10303 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5456:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
10303 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5456:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 10304 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_W, |
10304 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_W, |
| 10305 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10305 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10306 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10306 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10307 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10307 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10308 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10308 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10309 |
GIR_EraseFromParent, /*InsnID*/0, |
10309 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10310 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10310 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10311 |
// GIR_Coverage, 653, |
10311 |
// GIR_Coverage, 653, |
| 10312 |
GIR_Done, |
10312 |
GIR_Done, |
| 10313 |
// Label 703: @24468 |
10313 |
// Label 703: @24468 |
| 10314 |
GIM_Try, /*On fail goto*//*Label 704*/ 24532, // Rule ID 654 // |
10314 |
GIM_Try, /*On fail goto*//*Label 704*/ 24532, // Rule ID 654 // |
| 10315 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10315 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10316 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_d, |
10316 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_d, |
| 10317 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
10317 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 10318 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
10318 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10319 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
10319 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10320 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
10320 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 10321 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
10321 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 10322 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
10322 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 10323 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
10323 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 10324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
10324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
| 10325 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5454:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
10325 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5454:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 10326 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_D, |
10326 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_D, |
| 10327 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10327 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10328 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10328 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10329 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10329 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10330 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10330 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10331 |
GIR_EraseFromParent, /*InsnID*/0, |
10331 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10332 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10332 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10333 |
// GIR_Coverage, 654, |
10333 |
// GIR_Coverage, 654, |
| 10334 |
GIR_Done, |
10334 |
GIR_Done, |
| 10335 |
// Label 704: @24532 |
10335 |
// Label 704: @24532 |
| 10336 |
GIM_Try, /*On fail goto*//*Label 705*/ 24596, // Rule ID 655 // |
10336 |
GIM_Try, /*On fail goto*//*Label 705*/ 24596, // Rule ID 655 // |
| 10337 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10337 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10338 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_h, |
10338 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_h, |
| 10339 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
10339 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 10340 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
10340 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10341 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
10341 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10342 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
10342 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8, |
| 10343 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
10343 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 10344 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
10344 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 10345 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
10345 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 10346 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, |
10346 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID, |
| 10347 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5458:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
10347 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5458:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 10348 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_H, |
10348 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_H, |
| 10349 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10349 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10350 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10350 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10351 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10351 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10352 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10352 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10353 |
GIR_EraseFromParent, /*InsnID*/0, |
10353 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10354 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10354 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10355 |
// GIR_Coverage, 655, |
10355 |
// GIR_Coverage, 655, |
| 10356 |
GIR_Done, |
10356 |
GIR_Done, |
| 10357 |
// Label 705: @24596 |
10357 |
// Label 705: @24596 |
| 10358 |
GIM_Try, /*On fail goto*//*Label 706*/ 24660, // Rule ID 656 // |
10358 |
GIM_Try, /*On fail goto*//*Label 706*/ 24660, // Rule ID 656 // |
| 10359 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10359 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10360 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_w, |
10360 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_w, |
| 10361 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
10361 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10362 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
10362 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10363 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
10363 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 10364 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
10364 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 10365 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
10365 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 10366 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
10366 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 10367 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
10367 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 10368 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
10368 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
| 10369 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5459:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
10369 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5459:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 10370 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_W, |
10370 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_W, |
| 10371 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10371 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10372 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10372 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10373 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10373 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10374 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10374 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10375 |
GIR_EraseFromParent, /*InsnID*/0, |
10375 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10376 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10376 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10377 |
// GIR_Coverage, 656, |
10377 |
// GIR_Coverage, 656, |
| 10378 |
GIR_Done, |
10378 |
GIR_Done, |
| 10379 |
// Label 706: @24660 |
10379 |
// Label 706: @24660 |
| 10380 |
GIM_Try, /*On fail goto*//*Label 707*/ 24724, // Rule ID 657 // |
10380 |
GIM_Try, /*On fail goto*//*Label 707*/ 24724, // Rule ID 657 // |
| 10381 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10381 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10382 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_d, |
10382 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_d, |
| 10383 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
10383 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 10384 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
10384 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10385 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
10385 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10386 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
10386 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 10387 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
10387 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 10388 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
10388 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 10389 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
10389 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 10390 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
10390 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
| 10391 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5457:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
10391 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5457:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 10392 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_D, |
10392 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_D, |
| 10393 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10393 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10394 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10394 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10395 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10395 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10396 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10396 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10397 |
GIR_EraseFromParent, /*InsnID*/0, |
10397 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10398 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10398 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10399 |
// GIR_Coverage, 657, |
10399 |
// GIR_Coverage, 657, |
| 10400 |
GIR_Done, |
10400 |
GIR_Done, |
| 10401 |
// Label 707: @24724 |
10401 |
// Label 707: @24724 |
| 10402 |
GIM_Try, /*On fail goto*//*Label 708*/ 24788, // Rule ID 824 // |
10402 |
GIM_Try, /*On fail goto*//*Label 708*/ 24788, // Rule ID 824 // |
| 10403 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10403 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10404 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_h, |
10404 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_h, |
| 10405 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
10405 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 10406 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
10406 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10407 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
10407 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 10408 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
10408 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 10409 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
10409 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 10410 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
10410 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 10411 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
10411 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 10412 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
10412 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
| 10413 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5625:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
10413 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5625:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 10414 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_H, |
10414 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_H, |
| 10415 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10415 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10416 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10416 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10417 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10417 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10418 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10418 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10419 |
GIR_EraseFromParent, /*InsnID*/0, |
10419 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10420 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10420 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10421 |
// GIR_Coverage, 824, |
10421 |
// GIR_Coverage, 824, |
| 10422 |
GIR_Done, |
10422 |
GIR_Done, |
| 10423 |
// Label 708: @24788 |
10423 |
// Label 708: @24788 |
| 10424 |
GIM_Try, /*On fail goto*//*Label 709*/ 24852, // Rule ID 825 // |
10424 |
GIM_Try, /*On fail goto*//*Label 709*/ 24852, // Rule ID 825 // |
| 10425 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10425 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10426 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_w, |
10426 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_w, |
| 10427 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
10427 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10428 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
10428 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10429 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
10429 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10430 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
10430 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 10431 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
10431 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 10432 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
10432 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 10433 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
10433 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 10434 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
10434 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
| 10435 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5626:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
10435 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5626:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 10436 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_W, |
10436 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_W, |
| 10437 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10437 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10438 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10438 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10439 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10439 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10440 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10440 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10441 |
GIR_EraseFromParent, /*InsnID*/0, |
10441 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10442 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10442 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10443 |
// GIR_Coverage, 825, |
10443 |
// GIR_Coverage, 825, |
| 10444 |
GIR_Done, |
10444 |
GIR_Done, |
| 10445 |
// Label 709: @24852 |
10445 |
// Label 709: @24852 |
| 10446 |
GIM_Try, /*On fail goto*//*Label 710*/ 24916, // Rule ID 826 // |
10446 |
GIM_Try, /*On fail goto*//*Label 710*/ 24916, // Rule ID 826 // |
| 10447 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10447 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10448 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_h, |
10448 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_h, |
| 10449 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
10449 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 10450 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
10450 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10451 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
10451 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 10452 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
10452 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 10453 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
10453 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 10454 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
10454 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 10455 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
10455 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 10456 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
10456 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
| 10457 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5627:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
10457 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5627:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 10458 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_H, |
10458 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_H, |
| 10459 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10459 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10460 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10460 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10461 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10461 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10462 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10462 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10463 |
GIR_EraseFromParent, /*InsnID*/0, |
10463 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10464 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10464 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10465 |
// GIR_Coverage, 826, |
10465 |
// GIR_Coverage, 826, |
| 10466 |
GIR_Done, |
10466 |
GIR_Done, |
| 10467 |
// Label 710: @24916 |
10467 |
// Label 710: @24916 |
| 10468 |
GIM_Try, /*On fail goto*//*Label 711*/ 24980, // Rule ID 827 // |
10468 |
GIM_Try, /*On fail goto*//*Label 711*/ 24980, // Rule ID 827 // |
| 10469 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10469 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10470 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_w, |
10470 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_w, |
| 10471 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
10471 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10472 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
10472 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10473 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
10473 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10474 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
10474 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 10475 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
10475 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 10476 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
10476 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 10477 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
10477 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 10478 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
10478 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
| 10479 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5628:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
10479 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5628:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 10480 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_W, |
10480 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_W, |
| 10481 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10481 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10482 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10482 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10483 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10483 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10484 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10484 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10485 |
GIR_EraseFromParent, /*InsnID*/0, |
10485 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10486 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10486 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10487 |
// GIR_Coverage, 827, |
10487 |
// GIR_Coverage, 827, |
| 10488 |
GIR_Done, |
10488 |
GIR_Done, |
| 10489 |
// Label 711: @24980 |
10489 |
// Label 711: @24980 |
| 10490 |
GIM_Try, /*On fail goto*//*Label 712*/ 25044, // Rule ID 880 // |
10490 |
GIM_Try, /*On fail goto*//*Label 712*/ 25044, // Rule ID 880 // |
| 10491 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10491 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10492 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_h, |
10492 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_h, |
| 10493 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
10493 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 10494 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
10494 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10495 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
10495 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 10496 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
10496 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 10497 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
10497 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 10498 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
10498 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 10499 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
10499 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 10500 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
10500 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
| 10501 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5689:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
10501 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5689:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 10502 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_H, |
10502 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_H, |
| 10503 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10503 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10504 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10504 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10505 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10505 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10506 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10506 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10507 |
GIR_EraseFromParent, /*InsnID*/0, |
10507 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10508 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10508 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10509 |
// GIR_Coverage, 880, |
10509 |
// GIR_Coverage, 880, |
| 10510 |
GIR_Done, |
10510 |
GIR_Done, |
| 10511 |
// Label 712: @25044 |
10511 |
// Label 712: @25044 |
| 10512 |
GIM_Try, /*On fail goto*//*Label 713*/ 25108, // Rule ID 881 // |
10512 |
GIM_Try, /*On fail goto*//*Label 713*/ 25108, // Rule ID 881 // |
| 10513 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10513 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10514 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_w, |
10514 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_w, |
| 10515 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
10515 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10516 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
10516 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10517 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
10517 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10518 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
10518 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 10519 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
10519 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 10520 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
10520 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 10521 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
10521 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 10522 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
10522 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
| 10523 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5690:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
10523 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5690:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 10524 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_W, |
10524 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_W, |
| 10525 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10525 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10526 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10526 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10527 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10527 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10528 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10528 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10529 |
GIR_EraseFromParent, /*InsnID*/0, |
10529 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10530 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10530 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10531 |
// GIR_Coverage, 881, |
10531 |
// GIR_Coverage, 881, |
| 10532 |
GIR_Done, |
10532 |
GIR_Done, |
| 10533 |
// Label 713: @25108 |
10533 |
// Label 713: @25108 |
| 10534 |
GIM_Try, /*On fail goto*//*Label 714*/ 25172, // Rule ID 882 // |
10534 |
GIM_Try, /*On fail goto*//*Label 714*/ 25172, // Rule ID 882 // |
| 10535 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10535 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10536 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_h, |
10536 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_h, |
| 10537 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
10537 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 10538 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
10538 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10539 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
10539 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 10540 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
10540 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, |
| 10541 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
10541 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 10542 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
10542 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 10543 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
10543 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 10544 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
10544 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID, |
| 10545 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5691:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
10545 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5691:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 10546 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_H, |
10546 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_H, |
| 10547 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10547 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10548 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10548 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10549 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10549 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10550 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10550 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10551 |
GIR_EraseFromParent, /*InsnID*/0, |
10551 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10552 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10552 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10553 |
// GIR_Coverage, 882, |
10553 |
// GIR_Coverage, 882, |
| 10554 |
GIR_Done, |
10554 |
GIR_Done, |
| 10555 |
// Label 714: @25172 |
10555 |
// Label 714: @25172 |
| 10556 |
GIM_Try, /*On fail goto*//*Label 715*/ 25236, // Rule ID 883 // |
10556 |
GIM_Try, /*On fail goto*//*Label 715*/ 25236, // Rule ID 883 // |
| 10557 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10557 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10558 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_w, |
10558 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_w, |
| 10559 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
10559 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10560 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
10560 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10561 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
10561 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10562 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
10562 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, |
| 10563 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
10563 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 10564 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
10564 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 10565 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
10565 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 10566 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
10566 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID, |
| 10567 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5692:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
10567 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5692:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 10568 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_W, |
10568 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_W, |
| 10569 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10569 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10570 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10570 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10571 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10571 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10572 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
10572 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt |
| 10573 |
GIR_EraseFromParent, /*InsnID*/0, |
10573 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10574 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10574 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10575 |
// GIR_Coverage, 883, |
10575 |
// GIR_Coverage, 883, |
| 10576 |
GIR_Done, |
10576 |
GIR_Done, |
| 10577 |
// Label 715: @25236 |
10577 |
// Label 715: @25236 |
| 10578 |
GIM_Try, /*On fail goto*//*Label 716*/ 25300, // Rule ID 937 // |
10578 |
GIM_Try, /*On fail goto*//*Label 716*/ 25300, // Rule ID 937 // |
| 10579 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10579 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10580 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_b, |
10580 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_b, |
| 10581 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
10581 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, |
| 10582 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
10582 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10583 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
10583 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, |
| 10584 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, |
10584 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, |
| 10585 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
10585 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 10586 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
10586 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 10587 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
10587 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID, |
| 10588 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID, |
10588 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID, |
| 10589 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5793:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) |
10589 |
// (intrinsic_wo_chain:{ *:[v16i8] } 5793:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) |
| 10590 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_B, |
10590 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_B, |
| 10591 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10591 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10592 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10592 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10593 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10593 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10594 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt |
10594 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt |
| 10595 |
GIR_EraseFromParent, /*InsnID*/0, |
10595 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10596 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10596 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10597 |
// GIR_Coverage, 937, |
10597 |
// GIR_Coverage, 937, |
| 10598 |
GIR_Done, |
10598 |
GIR_Done, |
| 10599 |
// Label 716: @25300 |
10599 |
// Label 716: @25300 |
| 10600 |
GIM_Try, /*On fail goto*//*Label 717*/ 25364, // Rule ID 938 // |
10600 |
GIM_Try, /*On fail goto*//*Label 717*/ 25364, // Rule ID 938 // |
| 10601 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10601 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10602 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_h, |
10602 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_h, |
| 10603 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
10603 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, |
| 10604 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
10604 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10605 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
10605 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, |
| 10606 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, |
10606 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, |
| 10607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
10607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 10608 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
10608 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 10609 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
10609 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID, |
| 10610 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID, |
10610 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID, |
| 10611 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5795:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) |
10611 |
// (intrinsic_wo_chain:{ *:[v8i16] } 5795:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) |
| 10612 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_H, |
10612 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_H, |
| 10613 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10613 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10614 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10614 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10615 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10615 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10616 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt |
10616 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt |
| 10617 |
GIR_EraseFromParent, /*InsnID*/0, |
10617 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10618 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10618 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10619 |
// GIR_Coverage, 938, |
10619 |
// GIR_Coverage, 938, |
| 10620 |
GIR_Done, |
10620 |
GIR_Done, |
| 10621 |
// Label 717: @25364 |
10621 |
// Label 717: @25364 |
| 10622 |
GIM_Try, /*On fail goto*//*Label 718*/ 25428, // Rule ID 939 // |
10622 |
GIM_Try, /*On fail goto*//*Label 718*/ 25428, // Rule ID 939 // |
| 10623 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10623 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10624 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_w, |
10624 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_w, |
| 10625 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
10625 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, |
| 10626 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
10626 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10627 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
10627 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 10628 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, |
10628 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, |
| 10629 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
10629 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 10630 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
10630 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 10631 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
10631 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 10632 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID, |
10632 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID, |
| 10633 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5796:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) |
10633 |
// (intrinsic_wo_chain:{ *:[v4i32] } 5796:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) |
| 10634 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_W, |
10634 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_W, |
| 10635 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10635 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10636 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10636 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10637 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10637 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10638 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt |
10638 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt |
| 10639 |
GIR_EraseFromParent, /*InsnID*/0, |
10639 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10640 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10640 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10641 |
// GIR_Coverage, 939, |
10641 |
// GIR_Coverage, 939, |
| 10642 |
GIR_Done, |
10642 |
GIR_Done, |
| 10643 |
// Label 718: @25428 |
10643 |
// Label 718: @25428 |
| 10644 |
GIM_Try, /*On fail goto*//*Label 719*/ 25492, // Rule ID 940 // |
10644 |
GIM_Try, /*On fail goto*//*Label 719*/ 25492, // Rule ID 940 // |
| 10645 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
10645 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 10646 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_d, |
10646 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_d, |
| 10647 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
10647 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, |
| 10648 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
10648 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 10649 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
10649 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 10650 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, |
10650 |
GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32, |
| 10651 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
10651 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 10652 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
10652 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 10653 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
10653 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 10654 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID, |
10654 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID, |
| 10655 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5794:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) |
10655 |
// (intrinsic_wo_chain:{ *:[v2i64] } 5794:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) |
| 10656 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_D, |
10656 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_D, |
| 10657 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
10657 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 10658 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
10658 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in |
| 10659 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
10659 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws |
| 10660 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt |
10660 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt |
| 10661 |
GIR_EraseFromParent, /*InsnID*/0, |
10661 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10662 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10662 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10663 |
// GIR_Coverage, 940, |
10663 |
// GIR_Coverage, 940, |
| 10664 |
GIR_Done, |
10664 |
GIR_Done, |
| 10665 |
// Label 719: @25492 |
10665 |
// Label 719: @25492 |
| 10666 |
GIM_Reject, |
10666 |
GIM_Reject, |
| 10667 |
// Label 673: @25493 |
10667 |
// Label 673: @25493 |
| 10668 |
GIM_Reject, |
10668 |
GIM_Reject, |
| 10669 |
// Label 17: @25494 |
10669 |
// Label 17: @25494 |
| 10670 |
GIM_Try, /*On fail goto*//*Label 720*/ 25527, // Rule ID 342 // |
10670 |
GIM_Try, /*On fail goto*//*Label 720*/ 25527, // Rule ID 342 // |
| 10671 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, |
10671 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, |
| 10672 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bposge32, |
10672 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bposge32, |
| 10673 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
10673 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 10674 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
10674 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 10675 |
// (intrinsic_w_chain:{ *:[i32] } 5340:{ *:[iPTR] }) => (BPOSGE32_PSEUDO:{ *:[i32] }) |
10675 |
// (intrinsic_w_chain:{ *:[i32] } 5340:{ *:[iPTR] }) => (BPOSGE32_PSEUDO:{ *:[i32] }) |
| 10676 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BPOSGE32_PSEUDO, |
10676 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BPOSGE32_PSEUDO, |
| 10677 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
10677 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 10678 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10678 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10679 |
GIR_EraseFromParent, /*InsnID*/0, |
10679 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10680 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10680 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10681 |
// GIR_Coverage, 342, |
10681 |
// GIR_Coverage, 342, |
| 10682 |
GIR_Done, |
10682 |
GIR_Done, |
| 10683 |
// Label 720: @25527 |
10683 |
// Label 720: @25527 |
| 10684 |
GIM_Try, /*On fail goto*//*Label 721*/ 26489, |
10684 |
GIM_Try, /*On fail goto*//*Label 721*/ 26489, |
| 10685 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
10685 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 10686 |
GIM_Try, /*On fail goto*//*Label 722*/ 25575, // Rule ID 429 // |
10686 |
GIM_Try, /*On fail goto*//*Label 722*/ 25575, // Rule ID 429 // |
| 10687 |
GIM_CheckFeatures, GIFBS_HasDSP, |
10687 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 10688 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_rddsp, |
10688 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_rddsp, |
| 10689 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
10689 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 10690 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
10690 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 10691 |
// MIs[0] mask |
10691 |
// MIs[0] mask |
| 10692 |
GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
10692 |
GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 10693 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GICXXPred_I64_Predicate_timmZExt10, |
10693 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GICXXPred_I64_Predicate_timmZExt10, |
| 10694 |
// (intrinsic_w_chain:{ *:[i32] } 5767:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$mask) => (RDDSP:{ *:[i32] } (timm:{ *:[i32] }):$mask) |
10694 |
// (intrinsic_w_chain:{ *:[i32] } 5767:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$mask) => (RDDSP:{ *:[i32] } (timm:{ *:[i32] }):$mask) |
| 10695 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RDDSP, |
10695 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RDDSP, |
| 10696 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
10696 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 10697 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask |
10697 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask |
| 10698 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10698 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10699 |
GIR_EraseFromParent, /*InsnID*/0, |
10699 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10700 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10700 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10701 |
// GIR_Coverage, 429, |
10701 |
// GIR_Coverage, 429, |
| 10702 |
GIR_Done, |
10702 |
GIR_Done, |
| 10703 |
// Label 722: @25575 |
10703 |
// Label 722: @25575 |
| 10704 |
GIM_Try, /*On fail goto*//*Label 723*/ 25614, // Rule ID 1275 // |
10704 |
GIM_Try, /*On fail goto*//*Label 723*/ 25614, // Rule ID 1275 // |
| 10705 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
10705 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 10706 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_rddsp, |
10706 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_rddsp, |
| 10707 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
10707 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 10708 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
10708 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 10709 |
// MIs[0] mask |
10709 |
// MIs[0] mask |
| 10710 |
GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
10710 |
GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 10711 |
// (intrinsic_w_chain:{ *:[i32] } 5767:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$mask) => (RDDSP_MM:{ *:[i32] } (timm:{ *:[i32] }):$mask) |
10711 |
// (intrinsic_w_chain:{ *:[i32] } 5767:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$mask) => (RDDSP_MM:{ *:[i32] } (timm:{ *:[i32] }):$mask) |
| 10712 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RDDSP_MM, |
10712 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RDDSP_MM, |
| 10713 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
10713 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 10714 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask |
10714 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask |
| 10715 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10715 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10716 |
GIR_EraseFromParent, /*InsnID*/0, |
10716 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10717 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10717 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10718 |
// GIR_Coverage, 1275, |
10718 |
// GIR_Coverage, 1275, |
| 10719 |
GIR_Done, |
10719 |
GIR_Done, |
| 10720 |
// Label 723: @25614 |
10720 |
// Label 723: @25614 |
| 10721 |
GIM_Try, /*On fail goto*//*Label 724*/ 25657, // Rule ID 430 // |
10721 |
GIM_Try, /*On fail goto*//*Label 724*/ 25657, // Rule ID 430 // |
| 10722 |
GIM_CheckFeatures, GIFBS_HasDSP_NotInMicroMips, |
10722 |
GIM_CheckFeatures, GIFBS_HasDSP_NotInMicroMips, |
| 10723 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_wrdsp, |
10723 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_wrdsp, |
| 10724 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
10724 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 10725 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
10725 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 10726 |
// MIs[0] mask |
10726 |
// MIs[0] mask |
| 10727 |
GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
10727 |
GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 10728 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GICXXPred_I64_Predicate_timmZExt10, |
10728 |
GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GICXXPred_I64_Predicate_timmZExt10, |
| 10729 |
// (intrinsic_void 5896:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$mask) => (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$mask) |
10729 |
// (intrinsic_void 5896:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<>:$mask) => (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$mask) |
| 10730 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::WRDSP, |
10730 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::WRDSP, |
| 10731 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
10731 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 10732 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask |
10732 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask |
| 10733 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10733 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10734 |
GIR_EraseFromParent, /*InsnID*/0, |
10734 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10735 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10735 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10736 |
// GIR_Coverage, 430, |
10736 |
// GIR_Coverage, 430, |
| 10737 |
GIR_Done, |
10737 |
GIR_Done, |
| 10738 |
// Label 724: @25657 |
10738 |
// Label 724: @25657 |
| 10739 |
GIM_Try, /*On fail goto*//*Label 725*/ 25696, // Rule ID 1286 // |
10739 |
GIM_Try, /*On fail goto*//*Label 725*/ 25696, // Rule ID 1286 // |
| 10740 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
10740 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 10741 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_wrdsp, |
10741 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_wrdsp, |
| 10742 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
10742 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 10743 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
10743 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 10744 |
// MIs[0] mask |
10744 |
// MIs[0] mask |
| 10745 |
GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
10745 |
GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 10746 |
// (intrinsic_void 5896:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] })<>:$mask) => (WRDSP_MM GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] }):$mask) |
10746 |
// (intrinsic_void 5896:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] })<>:$mask) => (WRDSP_MM GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] }):$mask) |
| 10747 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::WRDSP_MM, |
10747 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::WRDSP_MM, |
| 10748 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
10748 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 10749 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask |
10749 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask |
| 10750 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10750 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10751 |
GIR_EraseFromParent, /*InsnID*/0, |
10751 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10752 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10752 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10753 |
// GIR_Coverage, 1286, |
10753 |
// GIR_Coverage, 1286, |
| 10754 |
GIR_Done, |
10754 |
GIR_Done, |
| 10755 |
// Label 725: @25696 |
10755 |
// Label 725: @25696 |
| 10756 |
GIM_Try, /*On fail goto*//*Label 726*/ 25740, // Rule ID 351 // |
10756 |
GIM_Try, /*On fail goto*//*Label 726*/ 25740, // Rule ID 351 // |
| 10757 |
GIM_CheckFeatures, GIFBS_HasDSP, |
10757 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 10758 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph, |
10758 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph, |
| 10759 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
10759 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 10760 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
10760 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 10761 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
10761 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 10762 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
10762 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 10763 |
// (intrinsic_w_chain:{ *:[v2i16] } 5228:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt) |
10763 |
// (intrinsic_w_chain:{ *:[v2i16] } 5228:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt) |
| 10764 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH, |
10764 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH, |
| 10765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
10765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 10766 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
10766 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 10767 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10767 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10768 |
GIR_EraseFromParent, /*InsnID*/0, |
10768 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10769 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10769 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10770 |
// GIR_Coverage, 351, |
10770 |
// GIR_Coverage, 351, |
| 10771 |
GIR_Done, |
10771 |
GIR_Done, |
| 10772 |
// Label 726: @25740 |
10772 |
// Label 726: @25740 |
| 10773 |
GIM_Try, /*On fail goto*//*Label 727*/ 25784, // Rule ID 352 // |
10773 |
GIM_Try, /*On fail goto*//*Label 727*/ 25784, // Rule ID 352 // |
| 10774 |
GIM_CheckFeatures, GIFBS_HasDSP, |
10774 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 10775 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w, |
10775 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w, |
| 10776 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
10776 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 10777 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
10777 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 10778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
10778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 10779 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
10779 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 10780 |
// (intrinsic_w_chain:{ *:[i32] } 5230:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt) |
10780 |
// (intrinsic_w_chain:{ *:[i32] } 5230:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt) |
| 10781 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W, |
10781 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W, |
| 10782 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
10782 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 10783 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
10783 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 10784 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10784 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10785 |
GIR_EraseFromParent, /*InsnID*/0, |
10785 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10786 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10786 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10787 |
// GIR_Coverage, 352, |
10787 |
// GIR_Coverage, 352, |
| 10788 |
GIR_Done, |
10788 |
GIR_Done, |
| 10789 |
// Label 727: @25784 |
10789 |
// Label 727: @25784 |
| 10790 |
GIM_Try, /*On fail goto*//*Label 728*/ 25828, // Rule ID 438 // |
10790 |
GIM_Try, /*On fail goto*//*Label 728*/ 25828, // Rule ID 438 // |
| 10791 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
10791 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 10792 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb, |
10792 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb, |
| 10793 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
10793 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 10794 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
10794 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 10795 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
10795 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 10796 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
10796 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 10797 |
// (intrinsic_w_chain:{ *:[v4i8] } 5229:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt) |
10797 |
// (intrinsic_w_chain:{ *:[v4i8] } 5229:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt) |
| 10798 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB, |
10798 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB, |
| 10799 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
10799 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 10800 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
10800 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 10801 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10801 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10802 |
GIR_EraseFromParent, /*InsnID*/0, |
10802 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10803 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10803 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10804 |
// GIR_Coverage, 438, |
10804 |
// GIR_Coverage, 438, |
| 10805 |
GIR_Done, |
10805 |
GIR_Done, |
| 10806 |
// Label 728: @25828 |
10806 |
// Label 728: @25828 |
| 10807 |
GIM_Try, /*On fail goto*//*Label 729*/ 25872, // Rule ID 1218 // |
10807 |
GIM_Try, /*On fail goto*//*Label 729*/ 25872, // Rule ID 1218 // |
| 10808 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
10808 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 10809 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph, |
10809 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph, |
| 10810 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
10810 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 10811 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
10811 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 10812 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
10812 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 10813 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
10813 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 10814 |
// (intrinsic_w_chain:{ *:[v2i16] } 5228:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs) |
10814 |
// (intrinsic_w_chain:{ *:[v2i16] } 5228:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs) |
| 10815 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH_MM, |
10815 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH_MM, |
| 10816 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
10816 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 10817 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
10817 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 10818 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10818 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10819 |
GIR_EraseFromParent, /*InsnID*/0, |
10819 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10820 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10820 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10821 |
// GIR_Coverage, 1218, |
10821 |
// GIR_Coverage, 1218, |
| 10822 |
GIR_Done, |
10822 |
GIR_Done, |
| 10823 |
// Label 729: @25872 |
10823 |
// Label 729: @25872 |
| 10824 |
GIM_Try, /*On fail goto*//*Label 730*/ 25916, // Rule ID 1219 // |
10824 |
GIM_Try, /*On fail goto*//*Label 730*/ 25916, // Rule ID 1219 // |
| 10825 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
10825 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 10826 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w, |
10826 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w, |
| 10827 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
10827 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 10828 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
10828 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 10829 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
10829 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 10830 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
10830 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 10831 |
// (intrinsic_w_chain:{ *:[i32] } 5230:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
10831 |
// (intrinsic_w_chain:{ *:[i32] } 5230:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
| 10832 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W_MM, |
10832 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W_MM, |
| 10833 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
10833 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 10834 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
10834 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 10835 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10835 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10836 |
GIR_EraseFromParent, /*InsnID*/0, |
10836 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10837 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10837 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10838 |
// GIR_Coverage, 1219, |
10838 |
// GIR_Coverage, 1219, |
| 10839 |
GIR_Done, |
10839 |
GIR_Done, |
| 10840 |
// Label 730: @25916 |
10840 |
// Label 730: @25916 |
| 10841 |
GIM_Try, /*On fail goto*//*Label 731*/ 25960, // Rule ID 1299 // |
10841 |
GIM_Try, /*On fail goto*//*Label 731*/ 25960, // Rule ID 1299 // |
| 10842 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
10842 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 10843 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb, |
10843 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb, |
| 10844 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
10844 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 10845 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
10845 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 10846 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
10846 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 10847 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
10847 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 10848 |
// (intrinsic_w_chain:{ *:[v4i8] } 5229:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs) |
10848 |
// (intrinsic_w_chain:{ *:[v4i8] } 5229:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs) |
| 10849 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB_MMR2, |
10849 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB_MMR2, |
| 10850 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
10850 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 10851 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
10851 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 10852 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10852 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10853 |
GIR_EraseFromParent, /*InsnID*/0, |
10853 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10854 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10854 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10855 |
// GIR_Coverage, 1299, |
10855 |
// GIR_Coverage, 1299, |
| 10856 |
GIR_Done, |
10856 |
GIR_Done, |
| 10857 |
// Label 731: @25960 |
10857 |
// Label 731: @25960 |
| 10858 |
GIM_Try, /*On fail goto*//*Label 732*/ 26004, // Rule ID 405 // |
10858 |
GIM_Try, /*On fail goto*//*Label 732*/ 26004, // Rule ID 405 // |
| 10859 |
GIM_CheckFeatures, GIFBS_HasDSP, |
10859 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 10860 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb, |
10860 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb, |
| 10861 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
10861 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
| 10862 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
10862 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 10863 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
10863 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 10864 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
10864 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 10865 |
// (intrinsic_void 5406:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
10865 |
// (intrinsic_void 5406:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 10866 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB, |
10866 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB, |
| 10867 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
10867 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 10868 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
10868 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 10869 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10869 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10870 |
GIR_EraseFromParent, /*InsnID*/0, |
10870 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10871 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10871 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10872 |
// GIR_Coverage, 405, |
10872 |
// GIR_Coverage, 405, |
| 10873 |
GIR_Done, |
10873 |
GIR_Done, |
| 10874 |
// Label 732: @26004 |
10874 |
// Label 732: @26004 |
| 10875 |
GIM_Try, /*On fail goto*//*Label 733*/ 26048, // Rule ID 406 // |
10875 |
GIM_Try, /*On fail goto*//*Label 733*/ 26048, // Rule ID 406 // |
| 10876 |
GIM_CheckFeatures, GIFBS_HasDSP, |
10876 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 10877 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb, |
10877 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb, |
| 10878 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
10878 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
| 10879 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
10879 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 10880 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
10880 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 10881 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
10881 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 10882 |
// (intrinsic_void 5408:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
10882 |
// (intrinsic_void 5408:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 10883 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB, |
10883 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB, |
| 10884 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
10884 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 10885 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
10885 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 10886 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10886 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10887 |
GIR_EraseFromParent, /*InsnID*/0, |
10887 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10888 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10888 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10889 |
// GIR_Coverage, 406, |
10889 |
// GIR_Coverage, 406, |
| 10890 |
GIR_Done, |
10890 |
GIR_Done, |
| 10891 |
// Label 733: @26048 |
10891 |
// Label 733: @26048 |
| 10892 |
GIM_Try, /*On fail goto*//*Label 734*/ 26092, // Rule ID 407 // |
10892 |
GIM_Try, /*On fail goto*//*Label 734*/ 26092, // Rule ID 407 // |
| 10893 |
GIM_CheckFeatures, GIFBS_HasDSP, |
10893 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 10894 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb, |
10894 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb, |
| 10895 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
10895 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
| 10896 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
10896 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 10897 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
10897 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 10898 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
10898 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 10899 |
// (intrinsic_void 5407:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
10899 |
// (intrinsic_void 5407:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 10900 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB, |
10900 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB, |
| 10901 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
10901 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 10902 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
10902 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 10903 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10903 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10904 |
GIR_EraseFromParent, /*InsnID*/0, |
10904 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10905 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10905 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10906 |
// GIR_Coverage, 407, |
10906 |
// GIR_Coverage, 407, |
| 10907 |
GIR_Done, |
10907 |
GIR_Done, |
| 10908 |
// Label 734: @26092 |
10908 |
// Label 734: @26092 |
| 10909 |
GIM_Try, /*On fail goto*//*Label 735*/ 26136, // Rule ID 411 // |
10909 |
GIM_Try, /*On fail goto*//*Label 735*/ 26136, // Rule ID 411 // |
| 10910 |
GIM_CheckFeatures, GIFBS_HasDSP, |
10910 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 10911 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph, |
10911 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph, |
| 10912 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
10912 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
| 10913 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
10913 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 10914 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
10914 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 10915 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
10915 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 10916 |
// (intrinsic_void 5397:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
10916 |
// (intrinsic_void 5397:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 10917 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH, |
10917 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH, |
| 10918 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
10918 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 10919 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
10919 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 10920 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10920 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10921 |
GIR_EraseFromParent, /*InsnID*/0, |
10921 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10922 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10922 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10923 |
// GIR_Coverage, 411, |
10923 |
// GIR_Coverage, 411, |
| 10924 |
GIR_Done, |
10924 |
GIR_Done, |
| 10925 |
// Label 735: @26136 |
10925 |
// Label 735: @26136 |
| 10926 |
GIM_Try, /*On fail goto*//*Label 736*/ 26180, // Rule ID 412 // |
10926 |
GIM_Try, /*On fail goto*//*Label 736*/ 26180, // Rule ID 412 // |
| 10927 |
GIM_CheckFeatures, GIFBS_HasDSP, |
10927 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 10928 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph, |
10928 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph, |
| 10929 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
10929 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
| 10930 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
10930 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 10931 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
10931 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 10932 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
10932 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 10933 |
// (intrinsic_void 5399:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
10933 |
// (intrinsic_void 5399:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 10934 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH, |
10934 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH, |
| 10935 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
10935 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 10936 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
10936 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 10937 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10937 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10938 |
GIR_EraseFromParent, /*InsnID*/0, |
10938 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10939 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10939 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10940 |
// GIR_Coverage, 412, |
10940 |
// GIR_Coverage, 412, |
| 10941 |
GIR_Done, |
10941 |
GIR_Done, |
| 10942 |
// Label 736: @26180 |
10942 |
// Label 736: @26180 |
| 10943 |
GIM_Try, /*On fail goto*//*Label 737*/ 26224, // Rule ID 413 // |
10943 |
GIM_Try, /*On fail goto*//*Label 737*/ 26224, // Rule ID 413 // |
| 10944 |
GIM_CheckFeatures, GIFBS_HasDSP, |
10944 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 10945 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph, |
10945 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph, |
| 10946 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
10946 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
| 10947 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
10947 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 10948 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
10948 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 10949 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
10949 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 10950 |
// (intrinsic_void 5398:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
10950 |
// (intrinsic_void 5398:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 10951 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH, |
10951 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH, |
| 10952 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
10952 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 10953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
10953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 10954 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10954 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10955 |
GIR_EraseFromParent, /*InsnID*/0, |
10955 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10956 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10956 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10957 |
// GIR_Coverage, 413, |
10957 |
// GIR_Coverage, 413, |
| 10958 |
GIR_Done, |
10958 |
GIR_Done, |
| 10959 |
// Label 737: @26224 |
10959 |
// Label 737: @26224 |
| 10960 |
GIM_Try, /*On fail goto*//*Label 738*/ 26268, // Rule ID 1290 // |
10960 |
GIM_Try, /*On fail goto*//*Label 738*/ 26268, // Rule ID 1290 // |
| 10961 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
10961 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 10962 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph, |
10962 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph, |
| 10963 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
10963 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
| 10964 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
10964 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 10965 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
10965 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 10966 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
10966 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 10967 |
// (intrinsic_void 5397:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
10967 |
// (intrinsic_void 5397:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 10968 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH_MM, |
10968 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH_MM, |
| 10969 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
10969 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 10970 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
10970 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 10971 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10971 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10972 |
GIR_EraseFromParent, /*InsnID*/0, |
10972 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10973 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10973 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10974 |
// GIR_Coverage, 1290, |
10974 |
// GIR_Coverage, 1290, |
| 10975 |
GIR_Done, |
10975 |
GIR_Done, |
| 10976 |
// Label 738: @26268 |
10976 |
// Label 738: @26268 |
| 10977 |
GIM_Try, /*On fail goto*//*Label 739*/ 26312, // Rule ID 1291 // |
10977 |
GIM_Try, /*On fail goto*//*Label 739*/ 26312, // Rule ID 1291 // |
| 10978 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
10978 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 10979 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph, |
10979 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph, |
| 10980 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
10980 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
| 10981 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
10981 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 10982 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
10982 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 10983 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
10983 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 10984 |
// (intrinsic_void 5399:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
10984 |
// (intrinsic_void 5399:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 10985 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH_MM, |
10985 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH_MM, |
| 10986 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
10986 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 10987 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
10987 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 10988 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
10988 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 10989 |
GIR_EraseFromParent, /*InsnID*/0, |
10989 |
GIR_EraseFromParent, /*InsnID*/0, |
| 10990 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
10990 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 10991 |
// GIR_Coverage, 1291, |
10991 |
// GIR_Coverage, 1291, |
| 10992 |
GIR_Done, |
10992 |
GIR_Done, |
| 10993 |
// Label 739: @26312 |
10993 |
// Label 739: @26312 |
| 10994 |
GIM_Try, /*On fail goto*//*Label 740*/ 26356, // Rule ID 1292 // |
10994 |
GIM_Try, /*On fail goto*//*Label 740*/ 26356, // Rule ID 1292 // |
| 10995 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
10995 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 10996 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph, |
10996 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph, |
| 10997 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
10997 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16, |
| 10998 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
10998 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 10999 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
10999 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 11000 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11000 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11001 |
// (intrinsic_void 5398:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11001 |
// (intrinsic_void 5398:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11002 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH_MM, |
11002 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH_MM, |
| 11003 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
11003 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 11004 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11004 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11005 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11005 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11006 |
GIR_EraseFromParent, /*InsnID*/0, |
11006 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11007 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11007 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11008 |
// GIR_Coverage, 1292, |
11008 |
// GIR_Coverage, 1292, |
| 11009 |
GIR_Done, |
11009 |
GIR_Done, |
| 11010 |
// Label 740: @26356 |
11010 |
// Label 740: @26356 |
| 11011 |
GIM_Try, /*On fail goto*//*Label 741*/ 26400, // Rule ID 1296 // |
11011 |
GIM_Try, /*On fail goto*//*Label 741*/ 26400, // Rule ID 1296 // |
| 11012 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11012 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11013 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb, |
11013 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb, |
| 11014 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
11014 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
| 11015 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11015 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
11016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 11017 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11017 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11018 |
// (intrinsic_void 5406:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
11018 |
// (intrinsic_void 5406:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 11019 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB_MM, |
11019 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB_MM, |
| 11020 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
11020 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 11021 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11021 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11022 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11022 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11023 |
GIR_EraseFromParent, /*InsnID*/0, |
11023 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11024 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11024 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11025 |
// GIR_Coverage, 1296, |
11025 |
// GIR_Coverage, 1296, |
| 11026 |
GIR_Done, |
11026 |
GIR_Done, |
| 11027 |
// Label 741: @26400 |
11027 |
// Label 741: @26400 |
| 11028 |
GIM_Try, /*On fail goto*//*Label 742*/ 26444, // Rule ID 1297 // |
11028 |
GIM_Try, /*On fail goto*//*Label 742*/ 26444, // Rule ID 1297 // |
| 11029 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11029 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11030 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb, |
11030 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb, |
| 11031 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
11031 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
| 11032 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11032 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11033 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
11033 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 11034 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11034 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11035 |
// (intrinsic_void 5408:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
11035 |
// (intrinsic_void 5408:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 11036 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB_MM, |
11036 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB_MM, |
| 11037 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
11037 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 11038 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11038 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11039 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11039 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11040 |
GIR_EraseFromParent, /*InsnID*/0, |
11040 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11041 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11041 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11042 |
// GIR_Coverage, 1297, |
11042 |
// GIR_Coverage, 1297, |
| 11043 |
GIR_Done, |
11043 |
GIR_Done, |
| 11044 |
// Label 742: @26444 |
11044 |
// Label 742: @26444 |
| 11045 |
GIM_Try, /*On fail goto*//*Label 743*/ 26488, // Rule ID 1298 // |
11045 |
GIM_Try, /*On fail goto*//*Label 743*/ 26488, // Rule ID 1298 // |
| 11046 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11046 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11047 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb, |
11047 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb, |
| 11048 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
11048 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8, |
| 11049 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11049 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11050 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
11050 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID, |
| 11051 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11051 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11052 |
// (intrinsic_void 5407:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
11052 |
// (intrinsic_void 5407:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 11053 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB_MM, |
11053 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB_MM, |
| 11054 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
11054 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs |
| 11055 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11055 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11056 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11056 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11057 |
GIR_EraseFromParent, /*InsnID*/0, |
11057 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11058 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11058 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11059 |
// GIR_Coverage, 1298, |
11059 |
// GIR_Coverage, 1298, |
| 11060 |
GIR_Done, |
11060 |
GIR_Done, |
| 11061 |
// Label 743: @26488 |
11061 |
// Label 743: @26488 |
| 11062 |
GIM_Reject, |
11062 |
GIM_Reject, |
| 11063 |
// Label 721: @26489 |
11063 |
// Label 721: @26489 |
| 11064 |
GIM_Try, /*On fail goto*//*Label 744*/ 30477, |
11064 |
GIM_Try, /*On fail goto*//*Label 744*/ 30477, |
| 11065 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
11065 |
GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 11066 |
GIM_Try, /*On fail goto*//*Label 745*/ 26558, // Rule ID 370 // |
11066 |
GIM_Try, /*On fail goto*//*Label 745*/ 26558, // Rule ID 370 // |
| 11067 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11067 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11068 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph, |
11068 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph, |
| 11069 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11069 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11070 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11070 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11071 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11071 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11072 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11072 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11073 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11073 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11074 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
11074 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 11075 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
11075 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 11076 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
11076 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
| 11077 |
// MIs[1] Operand 1 |
11077 |
// MIs[1] Operand 1 |
| 11078 |
// No operand predicates |
11078 |
// No operand predicates |
| 11079 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
11079 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11080 |
// (intrinsic_w_chain:{ *:[v2i16] } 5784:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<>:$rs_sa) => (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa) |
11080 |
// (intrinsic_w_chain:{ *:[v2i16] } 5784:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<>:$rs_sa) => (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa) |
| 11081 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH, |
11081 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH, |
| 11082 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11082 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11083 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11083 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11084 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa |
11084 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa |
| 11085 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
11085 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 11086 |
GIR_EraseFromParent, /*InsnID*/0, |
11086 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11087 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11087 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11088 |
// GIR_Coverage, 370, |
11088 |
// GIR_Coverage, 370, |
| 11089 |
GIR_Done, |
11089 |
GIR_Done, |
| 11090 |
// Label 745: @26558 |
11090 |
// Label 745: @26558 |
| 11091 |
GIM_Try, /*On fail goto*//*Label 746*/ 26622, // Rule ID 375 // |
11091 |
GIM_Try, /*On fail goto*//*Label 746*/ 26622, // Rule ID 375 // |
| 11092 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11092 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11093 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w, |
11093 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w, |
| 11094 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11094 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11095 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
11095 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 11096 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11096 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11097 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11097 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11098 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
11098 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 11099 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
11099 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 11100 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
11100 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 11101 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
11101 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 11102 |
// MIs[1] Operand 1 |
11102 |
// MIs[1] Operand 1 |
| 11103 |
// No operand predicates |
11103 |
// No operand predicates |
| 11104 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
11104 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11105 |
// (intrinsic_w_chain:{ *:[i32] } 5785:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$rs_sa) => (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa) |
11105 |
// (intrinsic_w_chain:{ *:[i32] } 5785:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$rs_sa) => (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa) |
| 11106 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W, |
11106 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W, |
| 11107 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11107 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11108 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11108 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11109 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa |
11109 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa |
| 11110 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
11110 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 11111 |
GIR_EraseFromParent, /*InsnID*/0, |
11111 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11112 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11112 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11113 |
// GIR_Coverage, 375, |
11113 |
// GIR_Coverage, 375, |
| 11114 |
GIR_Done, |
11114 |
GIR_Done, |
| 11115 |
// Label 746: @26622 |
11115 |
// Label 746: @26622 |
| 11116 |
GIM_Try, /*On fail goto*//*Label 747*/ 26686, // Rule ID 1227 // |
11116 |
GIM_Try, /*On fail goto*//*Label 747*/ 26686, // Rule ID 1227 // |
| 11117 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11117 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11118 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph, |
11118 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph, |
| 11119 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11119 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11120 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11120 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11121 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11121 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11122 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11122 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11123 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11123 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11124 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
11124 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 11125 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
11125 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 11126 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
11126 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
| 11127 |
// MIs[1] Operand 1 |
11127 |
// MIs[1] Operand 1 |
| 11128 |
// No operand predicates |
11128 |
// No operand predicates |
| 11129 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
11129 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11130 |
// (intrinsic_w_chain:{ *:[v2i16] } 5784:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<>:$sa) => (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa) |
11130 |
// (intrinsic_w_chain:{ *:[v2i16] } 5784:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<>:$sa) => (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa) |
| 11131 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH_MM, |
11131 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH_MM, |
| 11132 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
11132 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 11133 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11133 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11134 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa |
11134 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa |
| 11135 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
11135 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 11136 |
GIR_EraseFromParent, /*InsnID*/0, |
11136 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11137 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11137 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11138 |
// GIR_Coverage, 1227, |
11138 |
// GIR_Coverage, 1227, |
| 11139 |
GIR_Done, |
11139 |
GIR_Done, |
| 11140 |
// Label 747: @26686 |
11140 |
// Label 747: @26686 |
| 11141 |
GIM_Try, /*On fail goto*//*Label 748*/ 26750, // Rule ID 1232 // |
11141 |
GIM_Try, /*On fail goto*//*Label 748*/ 26750, // Rule ID 1232 // |
| 11142 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11142 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11143 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w, |
11143 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w, |
| 11144 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11144 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11145 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
11145 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 11146 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11146 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11147 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11147 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11148 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
11148 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 11149 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
11149 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 11150 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
11150 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 11151 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
11151 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 11152 |
// MIs[1] Operand 1 |
11152 |
// MIs[1] Operand 1 |
| 11153 |
// No operand predicates |
11153 |
// No operand predicates |
| 11154 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
11154 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11155 |
// (intrinsic_w_chain:{ *:[i32] } 5785:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$sa) => (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa) |
11155 |
// (intrinsic_w_chain:{ *:[i32] } 5785:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<>:$sa) => (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa) |
| 11156 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W_MM, |
11156 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W_MM, |
| 11157 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
11157 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 11158 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11158 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11159 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa |
11159 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa |
| 11160 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
11160 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, |
| 11161 |
GIR_EraseFromParent, /*InsnID*/0, |
11161 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11162 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11162 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11163 |
// GIR_Coverage, 1232, |
11163 |
// GIR_Coverage, 1232, |
| 11164 |
GIR_Done, |
11164 |
GIR_Done, |
| 11165 |
// Label 748: @26750 |
11165 |
// Label 748: @26750 |
| 11166 |
GIM_Try, /*On fail goto*//*Label 749*/ 26805, // Rule ID 1898 // |
11166 |
GIM_Try, /*On fail goto*//*Label 749*/ 26805, // Rule ID 1898 // |
| 11167 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11167 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11168 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph, |
11168 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph, |
| 11169 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11169 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11170 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11170 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11171 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11171 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11172 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11172 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11173 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
11173 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 11174 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
11174 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 11175 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
11175 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
| 11176 |
// MIs[1] Operand 1 |
11176 |
// MIs[1] Operand 1 |
| 11177 |
// No operand predicates |
11177 |
// No operand predicates |
| 11178 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
11178 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11179 |
// (intrinsic_w_chain:{ *:[v2i16] } 5782:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<>:$shamt) => (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<>:$shamt) |
11179 |
// (intrinsic_w_chain:{ *:[v2i16] } 5782:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<>:$shamt) => (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<>:$shamt) |
| 11180 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_PH, |
11180 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_PH, |
| 11181 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11181 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11182 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
11182 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 11183 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
11183 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 11184 |
GIR_EraseFromParent, /*InsnID*/0, |
11184 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11185 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11185 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11186 |
// GIR_Coverage, 1898, |
11186 |
// GIR_Coverage, 1898, |
| 11187 |
GIR_Done, |
11187 |
GIR_Done, |
| 11188 |
// Label 749: @26805 |
11188 |
// Label 749: @26805 |
| 11189 |
GIM_Try, /*On fail goto*//*Label 750*/ 26860, // Rule ID 1904 // |
11189 |
GIM_Try, /*On fail goto*//*Label 750*/ 26860, // Rule ID 1904 // |
| 11190 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11190 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11191 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb, |
11191 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb, |
| 11192 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
11192 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 11193 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11193 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11194 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11194 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11195 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11195 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11196 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
11196 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 11197 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
11197 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 11198 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt3, |
11198 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt3, |
| 11199 |
// MIs[1] Operand 1 |
11199 |
// MIs[1] Operand 1 |
| 11200 |
// No operand predicates |
11200 |
// No operand predicates |
| 11201 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
11201 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 11202 |
// (intrinsic_w_chain:{ *:[v4i8] } 5783:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<>:$shamt) => (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<>:$shamt) |
11202 |
// (intrinsic_w_chain:{ *:[v4i8] } 5783:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<>:$shamt) => (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<>:$shamt) |
| 11203 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_QB, |
11203 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_QB, |
| 11204 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11204 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11205 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
11205 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 11206 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
11206 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 11207 |
GIR_EraseFromParent, /*InsnID*/0, |
11207 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11208 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11208 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11209 |
// GIR_Coverage, 1904, |
11209 |
// GIR_Coverage, 1904, |
| 11210 |
GIR_Done, |
11210 |
GIR_Done, |
| 11211 |
// Label 750: @26860 |
11211 |
// Label 750: @26860 |
| 11212 |
GIM_Try, /*On fail goto*//*Label 751*/ 26916, // Rule ID 347 // |
11212 |
GIM_Try, /*On fail goto*//*Label 751*/ 26916, // Rule ID 347 // |
| 11213 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11213 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11214 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w, |
11214 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w, |
| 11215 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11215 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11216 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
11216 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 11217 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11217 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11218 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11218 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11219 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
11219 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 11220 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11220 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11221 |
// (intrinsic_w_chain:{ *:[i32] } 5237:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
11221 |
// (intrinsic_w_chain:{ *:[i32] } 5237:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 11222 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W, |
11222 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W, |
| 11223 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11223 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11224 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11224 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11225 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11225 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11226 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11226 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11227 |
GIR_EraseFromParent, /*InsnID*/0, |
11227 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11228 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11228 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11229 |
// GIR_Coverage, 347, |
11229 |
// GIR_Coverage, 347, |
| 11230 |
GIR_Done, |
11230 |
GIR_Done, |
| 11231 |
// Label 751: @26916 |
11231 |
// Label 751: @26916 |
| 11232 |
GIM_Try, /*On fail goto*//*Label 752*/ 26972, // Rule ID 348 // |
11232 |
GIM_Try, /*On fail goto*//*Label 752*/ 26972, // Rule ID 348 // |
| 11233 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11233 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11234 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w, |
11234 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w, |
| 11235 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11235 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11236 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
11236 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 11237 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11237 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11238 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11238 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11239 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
11239 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 11240 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11240 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11241 |
// (intrinsic_w_chain:{ *:[i32] } 5857:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
11241 |
// (intrinsic_w_chain:{ *:[i32] } 5857:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 11242 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W, |
11242 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W, |
| 11243 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11243 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11244 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11244 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11245 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11245 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11246 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11246 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11247 |
GIR_EraseFromParent, /*InsnID*/0, |
11247 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11248 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11248 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11249 |
// GIR_Coverage, 348, |
11249 |
// GIR_Coverage, 348, |
| 11250 |
GIR_Done, |
11250 |
GIR_Done, |
| 11251 |
// Label 752: @26972 |
11251 |
// Label 752: @26972 |
| 11252 |
GIM_Try, /*On fail goto*//*Label 753*/ 27028, // Rule ID 355 // |
11252 |
GIM_Try, /*On fail goto*//*Label 753*/ 27028, // Rule ID 355 // |
| 11253 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11253 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11254 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w, |
11254 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w, |
| 11255 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11255 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11256 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
11256 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 11257 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11257 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11258 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11258 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11259 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
11259 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 11260 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11260 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11261 |
// (intrinsic_w_chain:{ *:[v2i16] } 5763:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
11261 |
// (intrinsic_w_chain:{ *:[v2i16] } 5763:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 11262 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W, |
11262 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W, |
| 11263 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11263 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11264 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11264 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11265 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11265 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11266 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11266 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11267 |
GIR_EraseFromParent, /*InsnID*/0, |
11267 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11268 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11268 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11269 |
// GIR_Coverage, 355, |
11269 |
// GIR_Coverage, 355, |
| 11270 |
GIR_Done, |
11270 |
GIR_Done, |
| 11271 |
// Label 753: @27028 |
11271 |
// Label 753: @27028 |
| 11272 |
GIM_Try, /*On fail goto*//*Label 754*/ 27084, // Rule ID 356 // |
11272 |
GIM_Try, /*On fail goto*//*Label 754*/ 27084, // Rule ID 356 // |
| 11273 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11273 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11274 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph, |
11274 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph, |
| 11275 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
11275 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 11276 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11276 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11277 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11277 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11281 |
// (intrinsic_w_chain:{ *:[v4i8] } 5764:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11281 |
// (intrinsic_w_chain:{ *:[v4i8] } 5764:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11282 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH, |
11282 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH, |
| 11283 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11283 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11284 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11284 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11285 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11285 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11286 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11286 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11287 |
GIR_EraseFromParent, /*InsnID*/0, |
11287 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11288 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11288 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11289 |
// GIR_Coverage, 356, |
11289 |
// GIR_Coverage, 356, |
| 11290 |
GIR_Done, |
11290 |
GIR_Done, |
| 11291 |
// Label 754: @27084 |
11291 |
// Label 754: @27084 |
| 11292 |
GIM_Try, /*On fail goto*//*Label 755*/ 27140, // Rule ID 367 // |
11292 |
GIM_Try, /*On fail goto*//*Label 755*/ 27140, // Rule ID 367 // |
| 11293 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11293 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11294 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb, |
11294 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb, |
| 11295 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
11295 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 11296 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11296 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11297 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11297 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11298 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11298 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11299 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11299 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11300 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11300 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11301 |
// (intrinsic_w_chain:{ *:[v4i8] } 5783:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
11301 |
// (intrinsic_w_chain:{ *:[v4i8] } 5783:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
| 11302 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB, |
11302 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB, |
| 11303 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11303 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11304 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11304 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11305 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
11305 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
| 11306 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11306 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11307 |
GIR_EraseFromParent, /*InsnID*/0, |
11307 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11308 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11308 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11309 |
// GIR_Coverage, 367, |
11309 |
// GIR_Coverage, 367, |
| 11310 |
GIR_Done, |
11310 |
GIR_Done, |
| 11311 |
// Label 755: @27140 |
11311 |
// Label 755: @27140 |
| 11312 |
GIM_Try, /*On fail goto*//*Label 756*/ 27196, // Rule ID 369 // |
11312 |
GIM_Try, /*On fail goto*//*Label 756*/ 27196, // Rule ID 369 // |
| 11313 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11313 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11314 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph, |
11314 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph, |
| 11315 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11315 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11316 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11316 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11317 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11317 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11318 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11318 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11319 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11319 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11320 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11320 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11321 |
// (intrinsic_w_chain:{ *:[v2i16] } 5782:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
11321 |
// (intrinsic_w_chain:{ *:[v2i16] } 5782:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
| 11322 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH, |
11322 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH, |
| 11323 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11323 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11324 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11324 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11325 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
11325 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
| 11326 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11326 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11327 |
GIR_EraseFromParent, /*InsnID*/0, |
11327 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11329 |
// GIR_Coverage, 369, |
11329 |
// GIR_Coverage, 369, |
| 11330 |
GIR_Done, |
11330 |
GIR_Done, |
| 11331 |
// Label 756: @27196 |
11331 |
// Label 756: @27196 |
| 11332 |
GIM_Try, /*On fail goto*//*Label 757*/ 27252, // Rule ID 371 // |
11332 |
GIM_Try, /*On fail goto*//*Label 757*/ 27252, // Rule ID 371 // |
| 11333 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11333 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11334 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph, |
11334 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph, |
| 11335 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11335 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11336 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11336 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11337 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11337 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11338 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11338 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11339 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11339 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11340 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11340 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11341 |
// (intrinsic_w_chain:{ *:[v2i16] } 5784:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
11341 |
// (intrinsic_w_chain:{ *:[v2i16] } 5784:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
| 11342 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH, |
11342 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH, |
| 11343 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11343 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11344 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11344 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11345 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
11345 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
| 11346 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11346 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11347 |
GIR_EraseFromParent, /*InsnID*/0, |
11347 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11348 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11348 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11349 |
// GIR_Coverage, 371, |
11349 |
// GIR_Coverage, 371, |
| 11350 |
GIR_Done, |
11350 |
GIR_Done, |
| 11351 |
// Label 757: @27252 |
11351 |
// Label 757: @27252 |
| 11352 |
GIM_Try, /*On fail goto*//*Label 758*/ 27308, // Rule ID 376 // |
11352 |
GIM_Try, /*On fail goto*//*Label 758*/ 27308, // Rule ID 376 // |
| 11353 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11353 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11354 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w, |
11354 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w, |
| 11355 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11355 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11356 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
11356 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 11357 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11357 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11358 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11358 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11359 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
11359 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 11360 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11360 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11361 |
// (intrinsic_w_chain:{ *:[i32] } 5785:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
11361 |
// (intrinsic_w_chain:{ *:[i32] } 5785:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) |
| 11362 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W, |
11362 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W, |
| 11363 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11363 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11364 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11364 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11365 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
11365 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa |
| 11366 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11366 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11367 |
GIR_EraseFromParent, /*InsnID*/0, |
11367 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11368 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11368 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11369 |
// GIR_Coverage, 376, |
11369 |
// GIR_Coverage, 376, |
| 11370 |
GIR_Done, |
11370 |
GIR_Done, |
| 11371 |
// Label 758: @27308 |
11371 |
// Label 758: @27308 |
| 11372 |
GIM_Try, /*On fail goto*//*Label 759*/ 27364, // Rule ID 379 // |
11372 |
GIM_Try, /*On fail goto*//*Label 759*/ 27364, // Rule ID 379 // |
| 11373 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11373 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11374 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl, |
11374 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl, |
| 11375 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11375 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11376 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11376 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11377 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11377 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11378 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11378 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11379 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11379 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11380 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11380 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11381 |
// (intrinsic_w_chain:{ *:[v2i16] } 5705:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11381 |
// (intrinsic_w_chain:{ *:[v2i16] } 5705:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11382 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL, |
11382 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL, |
| 11383 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11383 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11384 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11384 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11385 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11385 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11386 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11386 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11387 |
GIR_EraseFromParent, /*InsnID*/0, |
11387 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11388 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11388 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11389 |
// GIR_Coverage, 379, |
11389 |
// GIR_Coverage, 379, |
| 11390 |
GIR_Done, |
11390 |
GIR_Done, |
| 11391 |
// Label 759: @27364 |
11391 |
// Label 759: @27364 |
| 11392 |
GIM_Try, /*On fail goto*//*Label 760*/ 27420, // Rule ID 380 // |
11392 |
GIM_Try, /*On fail goto*//*Label 760*/ 27420, // Rule ID 380 // |
| 11393 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11393 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11394 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr, |
11394 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr, |
| 11395 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11395 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11396 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11396 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11397 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11397 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11398 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11398 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11399 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11399 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11400 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11400 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11401 |
// (intrinsic_w_chain:{ *:[v2i16] } 5706:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11401 |
// (intrinsic_w_chain:{ *:[v2i16] } 5706:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11402 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR, |
11402 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR, |
| 11403 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11403 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11404 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11404 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11405 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11405 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11406 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11406 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11407 |
GIR_EraseFromParent, /*InsnID*/0, |
11407 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11408 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11408 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11409 |
// GIR_Coverage, 380, |
11409 |
// GIR_Coverage, 380, |
| 11410 |
GIR_Done, |
11410 |
GIR_Done, |
| 11411 |
// Label 760: @27420 |
11411 |
// Label 760: @27420 |
| 11412 |
GIM_Try, /*On fail goto*//*Label 761*/ 27476, // Rule ID 381 // |
11412 |
GIM_Try, /*On fail goto*//*Label 761*/ 27476, // Rule ID 381 // |
| 11413 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11413 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11414 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl, |
11414 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl, |
| 11415 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11415 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11416 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11416 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11417 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11417 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11418 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11418 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11419 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11419 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11420 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11420 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11421 |
// (intrinsic_w_chain:{ *:[i32] } 5703:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11421 |
// (intrinsic_w_chain:{ *:[i32] } 5703:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11422 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL, |
11422 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL, |
| 11423 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11423 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11424 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11424 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11425 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11425 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11426 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11426 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11427 |
GIR_EraseFromParent, /*InsnID*/0, |
11427 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11428 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11428 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11429 |
// GIR_Coverage, 381, |
11429 |
// GIR_Coverage, 381, |
| 11430 |
GIR_Done, |
11430 |
GIR_Done, |
| 11431 |
// Label 761: @27476 |
11431 |
// Label 761: @27476 |
| 11432 |
GIM_Try, /*On fail goto*//*Label 762*/ 27532, // Rule ID 382 // |
11432 |
GIM_Try, /*On fail goto*//*Label 762*/ 27532, // Rule ID 382 // |
| 11433 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11433 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11434 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr, |
11434 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr, |
| 11435 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11435 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11436 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11436 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11437 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11437 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11438 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11438 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11439 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11439 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11440 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11440 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11441 |
// (intrinsic_w_chain:{ *:[i32] } 5704:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11441 |
// (intrinsic_w_chain:{ *:[i32] } 5704:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11442 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR, |
11442 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR, |
| 11443 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11443 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11444 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11444 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11445 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11445 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11446 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11446 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11447 |
GIR_EraseFromParent, /*InsnID*/0, |
11447 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11448 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11448 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11449 |
// GIR_Coverage, 382, |
11449 |
// GIR_Coverage, 382, |
| 11450 |
GIR_Done, |
11450 |
GIR_Done, |
| 11451 |
// Label 762: @27532 |
11451 |
// Label 762: @27532 |
| 11452 |
GIM_Try, /*On fail goto*//*Label 763*/ 27588, // Rule ID 383 // |
11452 |
GIM_Try, /*On fail goto*//*Label 763*/ 27588, // Rule ID 383 // |
| 11453 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11453 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11454 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph, |
11454 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph, |
| 11455 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11455 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11456 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11456 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11457 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11457 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11458 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11458 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11459 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11459 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11460 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11460 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11461 |
// (intrinsic_w_chain:{ *:[v2i16] } 5707:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11461 |
// (intrinsic_w_chain:{ *:[v2i16] } 5707:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11462 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH, |
11462 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH, |
| 11463 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11463 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11464 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11464 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11465 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11465 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11466 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11466 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11467 |
GIR_EraseFromParent, /*InsnID*/0, |
11467 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11468 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11468 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11469 |
// GIR_Coverage, 383, |
11469 |
// GIR_Coverage, 383, |
| 11470 |
GIR_Done, |
11470 |
GIR_Done, |
| 11471 |
// Label 763: @27588 |
11471 |
// Label 763: @27588 |
| 11472 |
GIM_Try, /*On fail goto*//*Label 764*/ 27644, // Rule ID 408 // |
11472 |
GIM_Try, /*On fail goto*//*Label 764*/ 27644, // Rule ID 408 // |
| 11473 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11473 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11474 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb, |
11474 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb, |
| 11475 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11475 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11476 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11476 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11477 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
11477 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 11478 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11478 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11479 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11479 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11480 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11480 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11481 |
// (intrinsic_w_chain:{ *:[i32] } 5403:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
11481 |
// (intrinsic_w_chain:{ *:[i32] } 5403:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 11482 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB, |
11482 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB, |
| 11483 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11483 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11484 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11484 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11485 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11485 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11486 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11486 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11487 |
GIR_EraseFromParent, /*InsnID*/0, |
11487 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11488 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11488 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11489 |
// GIR_Coverage, 408, |
11489 |
// GIR_Coverage, 408, |
| 11490 |
GIR_Done, |
11490 |
GIR_Done, |
| 11491 |
// Label 764: @27644 |
11491 |
// Label 764: @27644 |
| 11492 |
GIM_Try, /*On fail goto*//*Label 765*/ 27700, // Rule ID 409 // |
11492 |
GIM_Try, /*On fail goto*//*Label 765*/ 27700, // Rule ID 409 // |
| 11493 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11493 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11494 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb, |
11494 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb, |
| 11495 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11495 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11496 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11496 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11497 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
11497 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 11498 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11498 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11499 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11499 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11500 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11500 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11501 |
// (intrinsic_w_chain:{ *:[i32] } 5405:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
11501 |
// (intrinsic_w_chain:{ *:[i32] } 5405:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 11502 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB, |
11502 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB, |
| 11503 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11503 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11504 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11504 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11505 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11505 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11506 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11506 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11507 |
GIR_EraseFromParent, /*InsnID*/0, |
11507 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11508 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11508 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11509 |
// GIR_Coverage, 409, |
11509 |
// GIR_Coverage, 409, |
| 11510 |
GIR_Done, |
11510 |
GIR_Done, |
| 11511 |
// Label 765: @27700 |
11511 |
// Label 765: @27700 |
| 11512 |
GIM_Try, /*On fail goto*//*Label 766*/ 27756, // Rule ID 410 // |
11512 |
GIM_Try, /*On fail goto*//*Label 766*/ 27756, // Rule ID 410 // |
| 11513 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11513 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11514 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb, |
11514 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb, |
| 11515 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11515 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11516 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11516 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11517 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
11517 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 11518 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11518 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11519 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11519 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11520 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11520 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11521 |
// (intrinsic_w_chain:{ *:[i32] } 5404:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
11521 |
// (intrinsic_w_chain:{ *:[i32] } 5404:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 11522 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB, |
11522 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB, |
| 11523 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11523 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11524 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11524 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11525 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11525 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11526 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11526 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11527 |
GIR_EraseFromParent, /*InsnID*/0, |
11527 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11528 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11528 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11529 |
// GIR_Coverage, 410, |
11529 |
// GIR_Coverage, 410, |
| 11530 |
GIR_Done, |
11530 |
GIR_Done, |
| 11531 |
// Label 766: @27756 |
11531 |
// Label 766: @27756 |
| 11532 |
GIM_Try, /*On fail goto*//*Label 767*/ 27812, // Rule ID 420 // |
11532 |
GIM_Try, /*On fail goto*//*Label 767*/ 27812, // Rule ID 420 // |
| 11533 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11533 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11534 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb, |
11534 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb, |
| 11535 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
11535 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 11536 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11536 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11537 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
11537 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 11538 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11538 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11539 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11539 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11540 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11540 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11541 |
// (intrinsic_w_chain:{ *:[v4i8] } 5747:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
11541 |
// (intrinsic_w_chain:{ *:[v4i8] } 5747:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 11542 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB, |
11542 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB, |
| 11543 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11543 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11544 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11544 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11545 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11545 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11546 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11546 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11547 |
GIR_EraseFromParent, /*InsnID*/0, |
11547 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11548 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11548 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11549 |
// GIR_Coverage, 420, |
11549 |
// GIR_Coverage, 420, |
| 11550 |
GIR_Done, |
11550 |
GIR_Done, |
| 11551 |
// Label 767: @27812 |
11551 |
// Label 767: @27812 |
| 11552 |
GIM_Try, /*On fail goto*//*Label 768*/ 27868, // Rule ID 421 // |
11552 |
GIM_Try, /*On fail goto*//*Label 768*/ 27868, // Rule ID 421 // |
| 11553 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11553 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11554 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph, |
11554 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph, |
| 11555 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11555 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11556 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11556 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11557 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11557 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11558 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11558 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11559 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11559 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11560 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11560 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11561 |
// (intrinsic_w_chain:{ *:[v2i16] } 5746:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11561 |
// (intrinsic_w_chain:{ *:[v2i16] } 5746:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11562 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH, |
11562 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH, |
| 11563 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11563 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11564 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11564 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11565 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11565 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11566 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11566 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11567 |
GIR_EraseFromParent, /*InsnID*/0, |
11567 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11568 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11568 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11569 |
// GIR_Coverage, 421, |
11569 |
// GIR_Coverage, 421, |
| 11570 |
GIR_Done, |
11570 |
GIR_Done, |
| 11571 |
// Label 768: @27868 |
11571 |
// Label 768: @27868 |
| 11572 |
GIM_Try, /*On fail goto*//*Label 769*/ 27924, // Rule ID 425 // |
11572 |
GIM_Try, /*On fail goto*//*Label 769*/ 27924, // Rule ID 425 // |
| 11573 |
GIM_CheckFeatures, GIFBS_HasDSP, |
11573 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 11574 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv, |
11574 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv, |
| 11575 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11575 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11576 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
11576 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 11577 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11577 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11578 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11578 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11579 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
11579 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 11580 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11580 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11581 |
// (intrinsic_w_chain:{ *:[i32] } 5605:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) |
11581 |
// (intrinsic_w_chain:{ *:[i32] } 5605:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) |
| 11582 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV, |
11582 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV, |
| 11583 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
11583 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 11584 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
11584 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 11585 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
11585 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 11586 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11586 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11587 |
GIR_EraseFromParent, /*InsnID*/0, |
11587 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11588 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11588 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11589 |
// GIR_Coverage, 425, |
11589 |
// GIR_Coverage, 425, |
| 11590 |
GIR_Done, |
11590 |
GIR_Done, |
| 11591 |
// Label 769: @27924 |
11591 |
// Label 769: @27924 |
| 11592 |
GIM_Try, /*On fail goto*//*Label 770*/ 27980, // Rule ID 431 // |
11592 |
GIM_Try, /*On fail goto*//*Label 770*/ 27980, // Rule ID 431 // |
| 11593 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
11593 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 11594 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph, |
11594 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph, |
| 11595 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11595 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11596 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11596 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11597 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11597 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11598 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11598 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11599 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11599 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11600 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11600 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11601 |
// (intrinsic_w_chain:{ *:[v2i16] } 5255:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11601 |
// (intrinsic_w_chain:{ *:[v2i16] } 5255:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11602 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH, |
11602 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH, |
| 11603 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11603 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11604 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11604 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11605 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11605 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11606 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11606 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11607 |
GIR_EraseFromParent, /*InsnID*/0, |
11607 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11608 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11608 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11609 |
// GIR_Coverage, 431, |
11609 |
// GIR_Coverage, 431, |
| 11610 |
GIR_Done, |
11610 |
GIR_Done, |
| 11611 |
// Label 770: @27980 |
11611 |
// Label 770: @27980 |
| 11612 |
GIM_Try, /*On fail goto*//*Label 771*/ 28036, // Rule ID 432 // |
11612 |
GIM_Try, /*On fail goto*//*Label 771*/ 28036, // Rule ID 432 // |
| 11613 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
11613 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 11614 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph, |
11614 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph, |
| 11615 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11615 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11616 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11616 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11617 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11617 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11618 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11618 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11619 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11619 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11620 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11620 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11621 |
// (intrinsic_w_chain:{ *:[v2i16] } 5257:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11621 |
// (intrinsic_w_chain:{ *:[v2i16] } 5257:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11622 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH, |
11622 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH, |
| 11623 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11623 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11624 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11624 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11625 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11625 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11626 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11626 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11627 |
GIR_EraseFromParent, /*InsnID*/0, |
11627 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11628 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11628 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11629 |
// GIR_Coverage, 432, |
11629 |
// GIR_Coverage, 432, |
| 11630 |
GIR_Done, |
11630 |
GIR_Done, |
| 11631 |
// Label 771: @28036 |
11631 |
// Label 771: @28036 |
| 11632 |
GIM_Try, /*On fail goto*//*Label 772*/ 28092, // Rule ID 433 // |
11632 |
GIM_Try, /*On fail goto*//*Label 772*/ 28092, // Rule ID 433 // |
| 11633 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
11633 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 11634 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph, |
11634 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph, |
| 11635 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11635 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11636 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11636 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11637 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11637 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11638 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11638 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11639 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11639 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11640 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11640 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11641 |
// (intrinsic_w_chain:{ *:[v2i16] } 5878:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11641 |
// (intrinsic_w_chain:{ *:[v2i16] } 5878:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11642 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH, |
11642 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH, |
| 11643 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11643 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11644 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11644 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11645 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11645 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11646 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11646 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11647 |
GIR_EraseFromParent, /*InsnID*/0, |
11647 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11648 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11648 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11649 |
// GIR_Coverage, 433, |
11649 |
// GIR_Coverage, 433, |
| 11650 |
GIR_Done, |
11650 |
GIR_Done, |
| 11651 |
// Label 772: @28092 |
11651 |
// Label 772: @28092 |
| 11652 |
GIM_Try, /*On fail goto*//*Label 773*/ 28148, // Rule ID 434 // |
11652 |
GIM_Try, /*On fail goto*//*Label 773*/ 28148, // Rule ID 434 // |
| 11653 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
11653 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 11654 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph, |
11654 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph, |
| 11655 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11655 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11656 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11656 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11657 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11657 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11658 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11658 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11659 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11659 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11660 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11660 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11661 |
// (intrinsic_w_chain:{ *:[v2i16] } 5880:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11661 |
// (intrinsic_w_chain:{ *:[v2i16] } 5880:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11662 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH, |
11662 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH, |
| 11663 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11663 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11664 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11664 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11665 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11665 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11666 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11666 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11667 |
GIR_EraseFromParent, /*InsnID*/0, |
11667 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11668 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11668 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11669 |
// GIR_Coverage, 434, |
11669 |
// GIR_Coverage, 434, |
| 11670 |
GIR_Done, |
11670 |
GIR_Done, |
| 11671 |
// Label 773: @28148 |
11671 |
// Label 773: @28148 |
| 11672 |
GIM_Try, /*On fail goto*//*Label 774*/ 28204, // Rule ID 435 // |
11672 |
GIM_Try, /*On fail goto*//*Label 774*/ 28204, // Rule ID 435 // |
| 11673 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
11673 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 11674 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb, |
11674 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb, |
| 11675 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11675 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11676 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11676 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11677 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
11677 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 11678 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11678 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11679 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11679 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11680 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11680 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11681 |
// (intrinsic_w_chain:{ *:[i32] } 5400:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
11681 |
// (intrinsic_w_chain:{ *:[i32] } 5400:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 11682 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB, |
11682 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB, |
| 11683 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11683 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11684 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11684 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11685 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11685 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11686 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11686 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11687 |
GIR_EraseFromParent, /*InsnID*/0, |
11687 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11688 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11688 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11689 |
// GIR_Coverage, 435, |
11689 |
// GIR_Coverage, 435, |
| 11690 |
GIR_Done, |
11690 |
GIR_Done, |
| 11691 |
// Label 774: @28204 |
11691 |
// Label 774: @28204 |
| 11692 |
GIM_Try, /*On fail goto*//*Label 775*/ 28260, // Rule ID 436 // |
11692 |
GIM_Try, /*On fail goto*//*Label 775*/ 28260, // Rule ID 436 // |
| 11693 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
11693 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 11694 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb, |
11694 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb, |
| 11695 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11695 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11696 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11696 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11697 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
11697 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 11698 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11698 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11699 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11699 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11700 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11700 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11701 |
// (intrinsic_w_chain:{ *:[i32] } 5402:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
11701 |
// (intrinsic_w_chain:{ *:[i32] } 5402:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 11702 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB, |
11702 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB, |
| 11703 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11703 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11704 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11704 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11705 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11705 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11706 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11706 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11707 |
GIR_EraseFromParent, /*InsnID*/0, |
11707 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11708 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11708 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11709 |
// GIR_Coverage, 436, |
11709 |
// GIR_Coverage, 436, |
| 11710 |
GIR_Done, |
11710 |
GIR_Done, |
| 11711 |
// Label 775: @28260 |
11711 |
// Label 775: @28260 |
| 11712 |
GIM_Try, /*On fail goto*//*Label 776*/ 28316, // Rule ID 437 // |
11712 |
GIM_Try, /*On fail goto*//*Label 776*/ 28316, // Rule ID 437 // |
| 11713 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
11713 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 11714 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb, |
11714 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb, |
| 11715 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11715 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11716 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11716 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11717 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
11717 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 11718 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11718 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11719 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11719 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11720 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11720 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11721 |
// (intrinsic_w_chain:{ *:[i32] } 5401:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
11721 |
// (intrinsic_w_chain:{ *:[i32] } 5401:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 11722 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB, |
11722 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB, |
| 11723 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11723 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11724 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11724 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11725 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11725 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11726 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11726 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11727 |
GIR_EraseFromParent, /*InsnID*/0, |
11727 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11728 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11728 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11729 |
// GIR_Coverage, 437, |
11729 |
// GIR_Coverage, 437, |
| 11730 |
GIR_Done, |
11730 |
GIR_Done, |
| 11731 |
// Label 776: @28316 |
11731 |
// Label 776: @28316 |
| 11732 |
GIM_Try, /*On fail goto*//*Label 777*/ 28372, // Rule ID 451 // |
11732 |
GIM_Try, /*On fail goto*//*Label 777*/ 28372, // Rule ID 451 // |
| 11733 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
11733 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 11734 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph, |
11734 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph, |
| 11735 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11735 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11736 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11736 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11737 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11737 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11738 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11738 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11739 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11739 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11740 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11740 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11741 |
// (intrinsic_w_chain:{ *:[v2i16] } 5702:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11741 |
// (intrinsic_w_chain:{ *:[v2i16] } 5702:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11742 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH, |
11742 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH, |
| 11743 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11743 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11744 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11744 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11745 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11745 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11746 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11746 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11747 |
GIR_EraseFromParent, /*InsnID*/0, |
11747 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11748 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11748 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11749 |
// GIR_Coverage, 451, |
11749 |
// GIR_Coverage, 451, |
| 11750 |
GIR_Done, |
11750 |
GIR_Done, |
| 11751 |
// Label 777: @28372 |
11751 |
// Label 777: @28372 |
| 11752 |
GIM_Try, /*On fail goto*//*Label 778*/ 28428, // Rule ID 452 // |
11752 |
GIM_Try, /*On fail goto*//*Label 778*/ 28428, // Rule ID 452 // |
| 11753 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
11753 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 11754 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w, |
11754 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w, |
| 11755 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11755 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11756 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
11756 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 11757 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11757 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11759 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
11759 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 11760 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11760 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11761 |
// (intrinsic_w_chain:{ *:[i32] } 5710:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
11761 |
// (intrinsic_w_chain:{ *:[i32] } 5710:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 11762 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W, |
11762 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W, |
| 11763 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11763 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11764 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11764 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11766 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11766 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11767 |
GIR_EraseFromParent, /*InsnID*/0, |
11767 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11768 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11768 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11769 |
// GIR_Coverage, 452, |
11769 |
// GIR_Coverage, 452, |
| 11770 |
GIR_Done, |
11770 |
GIR_Done, |
| 11771 |
// Label 778: @28428 |
11771 |
// Label 778: @28428 |
| 11772 |
GIM_Try, /*On fail goto*//*Label 779*/ 28484, // Rule ID 453 // |
11772 |
GIM_Try, /*On fail goto*//*Label 779*/ 28484, // Rule ID 453 // |
| 11773 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
11773 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 11774 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w, |
11774 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w, |
| 11775 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11775 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11776 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
11776 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 11777 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11777 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11779 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
11779 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 11780 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11780 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11781 |
// (intrinsic_w_chain:{ *:[i32] } 5708:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
11781 |
// (intrinsic_w_chain:{ *:[i32] } 5708:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 11782 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W, |
11782 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W, |
| 11783 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11783 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11784 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11784 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11785 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11785 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11786 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11786 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11787 |
GIR_EraseFromParent, /*InsnID*/0, |
11787 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11788 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11788 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11789 |
// GIR_Coverage, 453, |
11789 |
// GIR_Coverage, 453, |
| 11790 |
GIR_Done, |
11790 |
GIR_Done, |
| 11791 |
// Label 779: @28484 |
11791 |
// Label 779: @28484 |
| 11792 |
GIM_Try, /*On fail goto*//*Label 780*/ 28540, // Rule ID 454 // |
11792 |
GIM_Try, /*On fail goto*//*Label 780*/ 28540, // Rule ID 454 // |
| 11793 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
11793 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 11794 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph, |
11794 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph, |
| 11795 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11795 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11796 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11796 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11797 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11797 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11798 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11798 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11799 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11799 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11800 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11800 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11801 |
// (intrinsic_w_chain:{ *:[v2i16] } 5709:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11801 |
// (intrinsic_w_chain:{ *:[v2i16] } 5709:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11802 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH, |
11802 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH, |
| 11803 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11803 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11804 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11804 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11805 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11805 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11806 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11806 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11807 |
GIR_EraseFromParent, /*InsnID*/0, |
11807 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11808 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11808 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11809 |
// GIR_Coverage, 454, |
11809 |
// GIR_Coverage, 454, |
| 11810 |
GIR_Done, |
11810 |
GIR_Done, |
| 11811 |
// Label 780: @28540 |
11811 |
// Label 780: @28540 |
| 11812 |
GIM_Try, /*On fail goto*//*Label 781*/ 28596, // Rule ID 464 // |
11812 |
GIM_Try, /*On fail goto*//*Label 781*/ 28596, // Rule ID 464 // |
| 11813 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
11813 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 11814 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph, |
11814 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph, |
| 11815 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
11815 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 11816 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11816 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11817 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11817 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11818 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11818 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11819 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11819 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11820 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11820 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11821 |
// (intrinsic_w_chain:{ *:[v4i8] } 5758:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11821 |
// (intrinsic_w_chain:{ *:[v4i8] } 5758:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11822 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH, |
11822 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH, |
| 11823 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11823 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11824 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11824 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11825 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11825 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11826 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11826 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11827 |
GIR_EraseFromParent, /*InsnID*/0, |
11827 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11828 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11828 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11829 |
// GIR_Coverage, 464, |
11829 |
// GIR_Coverage, 464, |
| 11830 |
GIR_Done, |
11830 |
GIR_Done, |
| 11831 |
// Label 781: @28596 |
11831 |
// Label 781: @28596 |
| 11832 |
GIM_Try, /*On fail goto*//*Label 782*/ 28652, // Rule ID 1212 // |
11832 |
GIM_Try, /*On fail goto*//*Label 782*/ 28652, // Rule ID 1212 // |
| 11833 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11833 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11834 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w, |
11834 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w, |
| 11835 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11835 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11836 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
11836 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 11837 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11837 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11838 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11838 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11839 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
11839 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 11840 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11840 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11841 |
// (intrinsic_w_chain:{ *:[i32] } 5237:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
11841 |
// (intrinsic_w_chain:{ *:[i32] } 5237:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 11842 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W_MM, |
11842 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W_MM, |
| 11843 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11843 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11844 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11844 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11845 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11845 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11846 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11846 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11847 |
GIR_EraseFromParent, /*InsnID*/0, |
11847 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11848 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11848 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11849 |
// GIR_Coverage, 1212, |
11849 |
// GIR_Coverage, 1212, |
| 11850 |
GIR_Done, |
11850 |
GIR_Done, |
| 11851 |
// Label 782: @28652 |
11851 |
// Label 782: @28652 |
| 11852 |
GIM_Try, /*On fail goto*//*Label 783*/ 28708, // Rule ID 1220 // |
11852 |
GIM_Try, /*On fail goto*//*Label 783*/ 28708, // Rule ID 1220 // |
| 11853 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11853 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11854 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv, |
11854 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv, |
| 11855 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11855 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11856 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
11856 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 11857 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11857 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11858 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11858 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11859 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
11859 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 11860 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11860 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11861 |
// (intrinsic_w_chain:{ *:[i32] } 5605:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) |
11861 |
// (intrinsic_w_chain:{ *:[i32] } 5605:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) |
| 11862 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV_MM, |
11862 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV_MM, |
| 11863 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
11863 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 11864 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
11864 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 11865 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
11865 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 11866 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11866 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11867 |
GIR_EraseFromParent, /*InsnID*/0, |
11867 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11868 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11868 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11869 |
// GIR_Coverage, 1220, |
11869 |
// GIR_Coverage, 1220, |
| 11870 |
GIR_Done, |
11870 |
GIR_Done, |
| 11871 |
// Label 783: @28708 |
11871 |
// Label 783: @28708 |
| 11872 |
GIM_Try, /*On fail goto*//*Label 784*/ 28764, // Rule ID 1228 // |
11872 |
GIM_Try, /*On fail goto*//*Label 784*/ 28764, // Rule ID 1228 // |
| 11873 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11873 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11874 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph, |
11874 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph, |
| 11875 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11875 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11876 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11876 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11877 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11877 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11878 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11878 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11879 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11879 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11880 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11880 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11881 |
// (intrinsic_w_chain:{ *:[v2i16] } 5782:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
11881 |
// (intrinsic_w_chain:{ *:[v2i16] } 5782:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 11882 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH_MM, |
11882 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH_MM, |
| 11883 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11883 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11884 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11884 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11885 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
11885 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 11886 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11886 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11887 |
GIR_EraseFromParent, /*InsnID*/0, |
11887 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11888 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11888 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11889 |
// GIR_Coverage, 1228, |
11889 |
// GIR_Coverage, 1228, |
| 11890 |
GIR_Done, |
11890 |
GIR_Done, |
| 11891 |
// Label 784: @28764 |
11891 |
// Label 784: @28764 |
| 11892 |
GIM_Try, /*On fail goto*//*Label 785*/ 28820, // Rule ID 1229 // |
11892 |
GIM_Try, /*On fail goto*//*Label 785*/ 28820, // Rule ID 1229 // |
| 11893 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11893 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11894 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph, |
11894 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph, |
| 11895 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
11895 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 11896 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11896 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11897 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11897 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11898 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11898 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11899 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11899 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11900 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11900 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11901 |
// (intrinsic_w_chain:{ *:[v2i16] } 5784:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
11901 |
// (intrinsic_w_chain:{ *:[v2i16] } 5784:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 11902 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH_MM, |
11902 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH_MM, |
| 11903 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11903 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11904 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11904 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11905 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
11905 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 11906 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11906 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11907 |
GIR_EraseFromParent, /*InsnID*/0, |
11907 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11908 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11908 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11909 |
// GIR_Coverage, 1229, |
11909 |
// GIR_Coverage, 1229, |
| 11910 |
GIR_Done, |
11910 |
GIR_Done, |
| 11911 |
// Label 785: @28820 |
11911 |
// Label 785: @28820 |
| 11912 |
GIM_Try, /*On fail goto*//*Label 786*/ 28876, // Rule ID 1230 // |
11912 |
GIM_Try, /*On fail goto*//*Label 786*/ 28876, // Rule ID 1230 // |
| 11913 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11913 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11914 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb, |
11914 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb, |
| 11915 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
11915 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 11916 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
11916 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 11917 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11917 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11918 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
11918 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 11919 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11919 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11920 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11920 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11921 |
// (intrinsic_w_chain:{ *:[v4i8] } 5783:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
11921 |
// (intrinsic_w_chain:{ *:[v4i8] } 5783:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 11922 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB_MM, |
11922 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB_MM, |
| 11923 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11923 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11924 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11924 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11925 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
11925 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 11926 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11926 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11927 |
GIR_EraseFromParent, /*InsnID*/0, |
11927 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11928 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11928 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11929 |
// GIR_Coverage, 1230, |
11929 |
// GIR_Coverage, 1230, |
| 11930 |
GIR_Done, |
11930 |
GIR_Done, |
| 11931 |
// Label 786: @28876 |
11931 |
// Label 786: @28876 |
| 11932 |
GIM_Try, /*On fail goto*//*Label 787*/ 28932, // Rule ID 1231 // |
11932 |
GIM_Try, /*On fail goto*//*Label 787*/ 28932, // Rule ID 1231 // |
| 11933 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11933 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11934 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w, |
11934 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w, |
| 11935 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11935 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11936 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
11936 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 11937 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11937 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11938 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11938 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11939 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
11939 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 11940 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11940 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11941 |
// (intrinsic_w_chain:{ *:[i32] } 5785:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
11941 |
// (intrinsic_w_chain:{ *:[i32] } 5785:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 11942 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W_MM, |
11942 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W_MM, |
| 11943 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11943 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11944 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
11944 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt |
| 11945 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
11945 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs |
| 11946 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11946 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11947 |
GIR_EraseFromParent, /*InsnID*/0, |
11947 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11948 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11948 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11949 |
// GIR_Coverage, 1231, |
11949 |
// GIR_Coverage, 1231, |
| 11950 |
GIR_Done, |
11950 |
GIR_Done, |
| 11951 |
// Label 787: @28932 |
11951 |
// Label 787: @28932 |
| 11952 |
GIM_Try, /*On fail goto*//*Label 788*/ 28988, // Rule ID 1250 // |
11952 |
GIM_Try, /*On fail goto*//*Label 788*/ 28988, // Rule ID 1250 // |
| 11953 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11953 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11954 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w, |
11954 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w, |
| 11955 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11955 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11956 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
11956 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 11957 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
11957 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 11958 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11958 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11959 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
11959 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 11960 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
11960 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 11961 |
// (intrinsic_w_chain:{ *:[i32] } 5857:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
11961 |
// (intrinsic_w_chain:{ *:[i32] } 5857:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 11962 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W_MM, |
11962 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W_MM, |
| 11963 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11963 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11964 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11964 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11965 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11965 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11966 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11966 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11967 |
GIR_EraseFromParent, /*InsnID*/0, |
11967 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11968 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11968 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11969 |
// GIR_Coverage, 1250, |
11969 |
// GIR_Coverage, 1250, |
| 11970 |
GIR_Done, |
11970 |
GIR_Done, |
| 11971 |
// Label 788: @28988 |
11971 |
// Label 788: @28988 |
| 11972 |
GIM_Try, /*On fail goto*//*Label 789*/ 29044, // Rule ID 1256 // |
11972 |
GIM_Try, /*On fail goto*//*Label 789*/ 29044, // Rule ID 1256 // |
| 11973 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11973 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11974 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl, |
11974 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl, |
| 11975 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11975 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11976 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11976 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11977 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11977 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11978 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11978 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11979 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11979 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 11980 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
11980 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 11981 |
// (intrinsic_w_chain:{ *:[i32] } 5703:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
11981 |
// (intrinsic_w_chain:{ *:[i32] } 5703:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 11982 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL_MM, |
11982 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL_MM, |
| 11983 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
11983 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 11984 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
11984 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 11985 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
11985 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 11986 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
11986 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 11987 |
GIR_EraseFromParent, /*InsnID*/0, |
11987 |
GIR_EraseFromParent, /*InsnID*/0, |
| 11988 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
11988 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 11989 |
// GIR_Coverage, 1256, |
11989 |
// GIR_Coverage, 1256, |
| 11990 |
GIR_Done, |
11990 |
GIR_Done, |
| 11991 |
// Label 789: @29044 |
11991 |
// Label 789: @29044 |
| 11992 |
GIM_Try, /*On fail goto*//*Label 790*/ 29100, // Rule ID 1257 // |
11992 |
GIM_Try, /*On fail goto*//*Label 790*/ 29100, // Rule ID 1257 // |
| 11993 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
11993 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 11994 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr, |
11994 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr, |
| 11995 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
11995 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 11996 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
11996 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 11997 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
11997 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 11998 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
11998 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 11999 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
11999 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12000 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12000 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12001 |
// (intrinsic_w_chain:{ *:[i32] } 5704:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
12001 |
// (intrinsic_w_chain:{ *:[i32] } 5704:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 12002 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR_MM, |
12002 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR_MM, |
| 12003 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12003 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12004 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12004 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12005 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12005 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12006 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12006 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12007 |
GIR_EraseFromParent, /*InsnID*/0, |
12007 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12008 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12008 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12009 |
// GIR_Coverage, 1257, |
12009 |
// GIR_Coverage, 1257, |
| 12010 |
GIR_Done, |
12010 |
GIR_Done, |
| 12011 |
// Label 790: @29100 |
12011 |
// Label 790: @29100 |
| 12012 |
GIM_Try, /*On fail goto*//*Label 791*/ 29156, // Rule ID 1258 // |
12012 |
GIM_Try, /*On fail goto*//*Label 791*/ 29156, // Rule ID 1258 // |
| 12013 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
12013 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 12014 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl, |
12014 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl, |
| 12015 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
12015 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 12016 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
12016 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 12017 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
12017 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 12018 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12018 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12019 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12019 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12020 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12020 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12021 |
// (intrinsic_w_chain:{ *:[v2i16] } 5705:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
12021 |
// (intrinsic_w_chain:{ *:[v2i16] } 5705:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 12022 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL_MM, |
12022 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL_MM, |
| 12023 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12023 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12024 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12024 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12025 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12025 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12026 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12026 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12027 |
GIR_EraseFromParent, /*InsnID*/0, |
12027 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12028 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12028 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12029 |
// GIR_Coverage, 1258, |
12029 |
// GIR_Coverage, 1258, |
| 12030 |
GIR_Done, |
12030 |
GIR_Done, |
| 12031 |
// Label 791: @29156 |
12031 |
// Label 791: @29156 |
| 12032 |
GIM_Try, /*On fail goto*//*Label 792*/ 29212, // Rule ID 1259 // |
12032 |
GIM_Try, /*On fail goto*//*Label 792*/ 29212, // Rule ID 1259 // |
| 12033 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
12033 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 12034 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr, |
12034 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr, |
| 12035 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
12035 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 12036 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
12036 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 12037 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
12037 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 12038 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12038 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12039 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12039 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12040 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12040 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12041 |
// (intrinsic_w_chain:{ *:[v2i16] } 5706:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
12041 |
// (intrinsic_w_chain:{ *:[v2i16] } 5706:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 12042 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR_MM, |
12042 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR_MM, |
| 12043 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12043 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12044 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12044 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12045 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12045 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12046 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12046 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12047 |
GIR_EraseFromParent, /*InsnID*/0, |
12047 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12048 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12048 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12049 |
// GIR_Coverage, 1259, |
12049 |
// GIR_Coverage, 1259, |
| 12050 |
GIR_Done, |
12050 |
GIR_Done, |
| 12051 |
// Label 792: @29212 |
12051 |
// Label 792: @29212 |
| 12052 |
GIM_Try, /*On fail goto*//*Label 793*/ 29268, // Rule ID 1260 // |
12052 |
GIM_Try, /*On fail goto*//*Label 793*/ 29268, // Rule ID 1260 // |
| 12053 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
12053 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 12054 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph, |
12054 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph, |
| 12055 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
12055 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 12056 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
12056 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 12057 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
12057 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 12058 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12058 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12059 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12059 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12060 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12060 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12061 |
// (intrinsic_w_chain:{ *:[v2i16] } 5707:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
12061 |
// (intrinsic_w_chain:{ *:[v2i16] } 5707:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 12062 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH_MM, |
12062 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH_MM, |
| 12063 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12063 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12064 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12064 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12065 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12065 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12066 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12066 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12067 |
GIR_EraseFromParent, /*InsnID*/0, |
12067 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12068 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12068 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12069 |
// GIR_Coverage, 1260, |
12069 |
// GIR_Coverage, 1260, |
| 12070 |
GIR_Done, |
12070 |
GIR_Done, |
| 12071 |
// Label 793: @29268 |
12071 |
// Label 793: @29268 |
| 12072 |
GIM_Try, /*On fail goto*//*Label 794*/ 29324, // Rule ID 1263 // |
12072 |
GIM_Try, /*On fail goto*//*Label 794*/ 29324, // Rule ID 1263 // |
| 12073 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
12073 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 12074 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph, |
12074 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph, |
| 12075 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
12075 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 12076 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
12076 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 12077 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
12077 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 12078 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12078 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12079 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12079 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12080 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12080 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12081 |
// (intrinsic_w_chain:{ *:[v4i8] } 5764:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
12081 |
// (intrinsic_w_chain:{ *:[v4i8] } 5764:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 12082 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH_MM, |
12082 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH_MM, |
| 12083 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12083 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12084 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12084 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12085 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12085 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12086 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12086 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12087 |
GIR_EraseFromParent, /*InsnID*/0, |
12087 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12088 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12088 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12089 |
// GIR_Coverage, 1263, |
12089 |
// GIR_Coverage, 1263, |
| 12090 |
GIR_Done, |
12090 |
GIR_Done, |
| 12091 |
// Label 794: @29324 |
12091 |
// Label 794: @29324 |
| 12092 |
GIM_Try, /*On fail goto*//*Label 795*/ 29380, // Rule ID 1264 // |
12092 |
GIM_Try, /*On fail goto*//*Label 795*/ 29380, // Rule ID 1264 // |
| 12093 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
12093 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 12094 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w, |
12094 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w, |
| 12095 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
12095 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 12096 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
12096 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 12097 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
12097 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 12098 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12098 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12099 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
12099 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 12100 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
12100 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 12101 |
// (intrinsic_w_chain:{ *:[v2i16] } 5763:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
12101 |
// (intrinsic_w_chain:{ *:[v2i16] } 5763:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 12102 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W_MM, |
12102 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W_MM, |
| 12103 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12103 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12104 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12104 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12105 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12105 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12106 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12106 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12107 |
GIR_EraseFromParent, /*InsnID*/0, |
12107 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12108 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12108 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12109 |
// GIR_Coverage, 1264, |
12109 |
// GIR_Coverage, 1264, |
| 12110 |
GIR_Done, |
12110 |
GIR_Done, |
| 12111 |
// Label 795: @29380 |
12111 |
// Label 795: @29380 |
| 12112 |
GIM_Try, /*On fail goto*//*Label 796*/ 29436, // Rule ID 1282 // |
12112 |
GIM_Try, /*On fail goto*//*Label 796*/ 29436, // Rule ID 1282 // |
| 12113 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
12113 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 12114 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph, |
12114 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph, |
| 12115 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
12115 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 12116 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
12116 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 12117 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
12117 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 12118 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12118 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12119 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12119 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12120 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12120 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12121 |
// (intrinsic_w_chain:{ *:[v2i16] } 5746:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
12121 |
// (intrinsic_w_chain:{ *:[v2i16] } 5746:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 12122 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH_MM, |
12122 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH_MM, |
| 12123 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12123 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12124 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12124 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12125 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12125 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12126 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12126 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12127 |
GIR_EraseFromParent, /*InsnID*/0, |
12127 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12128 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12128 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12129 |
// GIR_Coverage, 1282, |
12129 |
// GIR_Coverage, 1282, |
| 12130 |
GIR_Done, |
12130 |
GIR_Done, |
| 12131 |
// Label 796: @29436 |
12131 |
// Label 796: @29436 |
| 12132 |
GIM_Try, /*On fail goto*//*Label 797*/ 29492, // Rule ID 1283 // |
12132 |
GIM_Try, /*On fail goto*//*Label 797*/ 29492, // Rule ID 1283 // |
| 12133 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
12133 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 12134 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb, |
12134 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb, |
| 12135 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
12135 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 12136 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
12136 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 12137 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
12137 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 12138 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12138 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12139 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12139 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12140 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12140 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12141 |
// (intrinsic_w_chain:{ *:[v4i8] } 5747:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
12141 |
// (intrinsic_w_chain:{ *:[v4i8] } 5747:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 12142 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB_MM, |
12142 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB_MM, |
| 12143 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12143 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12144 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12144 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12145 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12145 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12146 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12146 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12147 |
GIR_EraseFromParent, /*InsnID*/0, |
12147 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12148 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12148 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12149 |
// GIR_Coverage, 1283, |
12149 |
// GIR_Coverage, 1283, |
| 12150 |
GIR_Done, |
12150 |
GIR_Done, |
| 12151 |
// Label 797: @29492 |
12151 |
// Label 797: @29492 |
| 12152 |
GIM_Try, /*On fail goto*//*Label 798*/ 29548, // Rule ID 1293 // |
12152 |
GIM_Try, /*On fail goto*//*Label 798*/ 29548, // Rule ID 1293 // |
| 12153 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
12153 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 12154 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb, |
12154 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb, |
| 12155 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
12155 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 12156 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
12156 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 12157 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
12157 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 12158 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
12158 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 12159 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12159 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12160 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12160 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12161 |
// (intrinsic_w_chain:{ *:[i32] } 5403:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
12161 |
// (intrinsic_w_chain:{ *:[i32] } 5403:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 12162 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB_MM, |
12162 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB_MM, |
| 12163 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12163 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12164 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12164 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12165 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12165 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12166 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12166 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12167 |
GIR_EraseFromParent, /*InsnID*/0, |
12167 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12168 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12168 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12169 |
// GIR_Coverage, 1293, |
12169 |
// GIR_Coverage, 1293, |
| 12170 |
GIR_Done, |
12170 |
GIR_Done, |
| 12171 |
// Label 798: @29548 |
12171 |
// Label 798: @29548 |
| 12172 |
GIM_Try, /*On fail goto*//*Label 799*/ 29604, // Rule ID 1294 // |
12172 |
GIM_Try, /*On fail goto*//*Label 799*/ 29604, // Rule ID 1294 // |
| 12173 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
12173 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 12174 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb, |
12174 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb, |
| 12175 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
12175 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 12176 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
12176 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 12177 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
12177 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 12178 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
12178 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 12179 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12179 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12180 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12180 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12181 |
// (intrinsic_w_chain:{ *:[i32] } 5405:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
12181 |
// (intrinsic_w_chain:{ *:[i32] } 5405:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 12182 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB_MM, |
12182 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB_MM, |
| 12183 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12183 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12184 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12184 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12185 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12185 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12186 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12186 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12187 |
GIR_EraseFromParent, /*InsnID*/0, |
12187 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12188 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12188 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12189 |
// GIR_Coverage, 1294, |
12189 |
// GIR_Coverage, 1294, |
| 12190 |
GIR_Done, |
12190 |
GIR_Done, |
| 12191 |
// Label 799: @29604 |
12191 |
// Label 799: @29604 |
| 12192 |
GIM_Try, /*On fail goto*//*Label 800*/ 29660, // Rule ID 1295 // |
12192 |
GIM_Try, /*On fail goto*//*Label 800*/ 29660, // Rule ID 1295 // |
| 12193 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
12193 |
GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips, |
| 12194 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb, |
12194 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb, |
| 12195 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
12195 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 12196 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
12196 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 12197 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
12197 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 12198 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
12198 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 12199 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12199 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12200 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12200 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12201 |
// (intrinsic_w_chain:{ *:[i32] } 5404:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
12201 |
// (intrinsic_w_chain:{ *:[i32] } 5404:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 12202 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB_MM, |
12202 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB_MM, |
| 12203 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12203 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12204 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12204 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12205 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12205 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12206 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12206 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12207 |
GIR_EraseFromParent, /*InsnID*/0, |
12207 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12208 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12208 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12209 |
// GIR_Coverage, 1295, |
12209 |
// GIR_Coverage, 1295, |
| 12210 |
GIR_Done, |
12210 |
GIR_Done, |
| 12211 |
// Label 800: @29660 |
12211 |
// Label 800: @29660 |
| 12212 |
GIM_Try, /*On fail goto*//*Label 801*/ 29716, // Rule ID 1304 // |
12212 |
GIM_Try, /*On fail goto*//*Label 801*/ 29716, // Rule ID 1304 // |
| 12213 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
12213 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 12214 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph, |
12214 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph, |
| 12215 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
12215 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 12216 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
12216 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 12217 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
12217 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 12218 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12218 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12219 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12219 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12220 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12220 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12221 |
// (intrinsic_w_chain:{ *:[v2i16] } 5255:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
12221 |
// (intrinsic_w_chain:{ *:[v2i16] } 5255:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 12222 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH_MMR2, |
12222 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH_MMR2, |
| 12223 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12223 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12224 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12224 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12225 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12225 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12226 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12226 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12227 |
GIR_EraseFromParent, /*InsnID*/0, |
12227 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12228 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12228 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12229 |
// GIR_Coverage, 1304, |
12229 |
// GIR_Coverage, 1304, |
| 12230 |
GIR_Done, |
12230 |
GIR_Done, |
| 12231 |
// Label 801: @29716 |
12231 |
// Label 801: @29716 |
| 12232 |
GIM_Try, /*On fail goto*//*Label 802*/ 29772, // Rule ID 1305 // |
12232 |
GIM_Try, /*On fail goto*//*Label 802*/ 29772, // Rule ID 1305 // |
| 12233 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
12233 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 12234 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph, |
12234 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph, |
| 12235 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
12235 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 12236 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
12236 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 12237 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
12237 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 12238 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12238 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12239 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12239 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12240 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12240 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12241 |
// (intrinsic_w_chain:{ *:[v2i16] } 5257:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
12241 |
// (intrinsic_w_chain:{ *:[v2i16] } 5257:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 12242 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH_MMR2, |
12242 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH_MMR2, |
| 12243 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12243 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12244 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12244 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12245 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12245 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12246 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12246 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12247 |
GIR_EraseFromParent, /*InsnID*/0, |
12247 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12248 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12248 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12249 |
// GIR_Coverage, 1305, |
12249 |
// GIR_Coverage, 1305, |
| 12250 |
GIR_Done, |
12250 |
GIR_Done, |
| 12251 |
// Label 802: @29772 |
12251 |
// Label 802: @29772 |
| 12252 |
GIM_Try, /*On fail goto*//*Label 803*/ 29828, // Rule ID 1316 // |
12252 |
GIM_Try, /*On fail goto*//*Label 803*/ 29828, // Rule ID 1316 // |
| 12253 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
12253 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 12254 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb, |
12254 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb, |
| 12255 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
12255 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 12256 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
12256 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 12257 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
12257 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 12258 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
12258 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 12259 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12259 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12260 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12260 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12261 |
// (intrinsic_w_chain:{ *:[i32] } 5400:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
12261 |
// (intrinsic_w_chain:{ *:[i32] } 5400:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 12262 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB_MMR2, |
12262 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB_MMR2, |
| 12263 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12263 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12264 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12264 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12265 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12265 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12266 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12266 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12267 |
GIR_EraseFromParent, /*InsnID*/0, |
12267 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12268 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12268 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12269 |
// GIR_Coverage, 1316, |
12269 |
// GIR_Coverage, 1316, |
| 12270 |
GIR_Done, |
12270 |
GIR_Done, |
| 12271 |
// Label 803: @29828 |
12271 |
// Label 803: @29828 |
| 12272 |
GIM_Try, /*On fail goto*//*Label 804*/ 29884, // Rule ID 1317 // |
12272 |
GIM_Try, /*On fail goto*//*Label 804*/ 29884, // Rule ID 1317 // |
| 12273 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
12273 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 12274 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb, |
12274 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb, |
| 12275 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
12275 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 12276 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
12276 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 12277 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
12277 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 12278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
12278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 12279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12281 |
// (intrinsic_w_chain:{ *:[i32] } 5402:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
12281 |
// (intrinsic_w_chain:{ *:[i32] } 5402:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 12282 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB_MMR2, |
12282 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB_MMR2, |
| 12283 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12283 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12284 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12284 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12285 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12285 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12286 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12286 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12287 |
GIR_EraseFromParent, /*InsnID*/0, |
12287 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12288 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12288 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12289 |
// GIR_Coverage, 1317, |
12289 |
// GIR_Coverage, 1317, |
| 12290 |
GIR_Done, |
12290 |
GIR_Done, |
| 12291 |
// Label 804: @29884 |
12291 |
// Label 804: @29884 |
| 12292 |
GIM_Try, /*On fail goto*//*Label 805*/ 29940, // Rule ID 1318 // |
12292 |
GIM_Try, /*On fail goto*//*Label 805*/ 29940, // Rule ID 1318 // |
| 12293 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
12293 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 12294 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb, |
12294 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb, |
| 12295 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
12295 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 12296 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
12296 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8, |
| 12297 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
12297 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8, |
| 12298 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
12298 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 12299 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12299 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12300 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12300 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12301 |
// (intrinsic_w_chain:{ *:[i32] } 5401:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
12301 |
// (intrinsic_w_chain:{ *:[i32] } 5401:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) |
| 12302 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB_MMR2, |
12302 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB_MMR2, |
| 12303 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12303 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12304 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12304 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12305 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12305 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12306 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12306 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12307 |
GIR_EraseFromParent, /*InsnID*/0, |
12307 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12308 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12308 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12309 |
// GIR_Coverage, 1318, |
12309 |
// GIR_Coverage, 1318, |
| 12310 |
GIR_Done, |
12310 |
GIR_Done, |
| 12311 |
// Label 805: @29940 |
12311 |
// Label 805: @29940 |
| 12312 |
GIM_Try, /*On fail goto*//*Label 806*/ 29996, // Rule ID 1324 // |
12312 |
GIM_Try, /*On fail goto*//*Label 806*/ 29996, // Rule ID 1324 // |
| 12313 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
12313 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 12314 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph, |
12314 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph, |
| 12315 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
12315 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 12316 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
12316 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 12317 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
12317 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 12318 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12318 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12319 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12319 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12320 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12320 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12321 |
// (intrinsic_w_chain:{ *:[v2i16] } 5878:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
12321 |
// (intrinsic_w_chain:{ *:[v2i16] } 5878:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 12322 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH_MMR2, |
12322 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH_MMR2, |
| 12323 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12323 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12324 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12324 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12325 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12325 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12326 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12326 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12327 |
GIR_EraseFromParent, /*InsnID*/0, |
12327 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12329 |
// GIR_Coverage, 1324, |
12329 |
// GIR_Coverage, 1324, |
| 12330 |
GIR_Done, |
12330 |
GIR_Done, |
| 12331 |
// Label 806: @29996 |
12331 |
// Label 806: @29996 |
| 12332 |
GIM_Try, /*On fail goto*//*Label 807*/ 30052, // Rule ID 1325 // |
12332 |
GIM_Try, /*On fail goto*//*Label 807*/ 30052, // Rule ID 1325 // |
| 12333 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
12333 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 12334 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph, |
12334 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph, |
| 12335 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
12335 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 12336 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
12336 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 12337 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
12337 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 12338 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12338 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12339 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12339 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12340 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12340 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12341 |
// (intrinsic_w_chain:{ *:[v2i16] } 5880:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
12341 |
// (intrinsic_w_chain:{ *:[v2i16] } 5880:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 12342 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH_MMR2, |
12342 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH_MMR2, |
| 12343 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12343 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12344 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12344 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12345 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12345 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12346 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12346 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12347 |
GIR_EraseFromParent, /*InsnID*/0, |
12347 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12348 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12348 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12349 |
// GIR_Coverage, 1325, |
12349 |
// GIR_Coverage, 1325, |
| 12350 |
GIR_Done, |
12350 |
GIR_Done, |
| 12351 |
// Label 807: @30052 |
12351 |
// Label 807: @30052 |
| 12352 |
GIM_Try, /*On fail goto*//*Label 808*/ 30108, // Rule ID 1332 // |
12352 |
GIM_Try, /*On fail goto*//*Label 808*/ 30108, // Rule ID 1332 // |
| 12353 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
12353 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 12354 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph, |
12354 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph, |
| 12355 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
12355 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 12356 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
12356 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 12357 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
12357 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 12358 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12358 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12359 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12359 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12360 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12360 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12361 |
// (intrinsic_w_chain:{ *:[v2i16] } 5702:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
12361 |
// (intrinsic_w_chain:{ *:[v2i16] } 5702:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 12362 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH_MMR2, |
12362 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH_MMR2, |
| 12363 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12363 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12364 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12364 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12365 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12365 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12366 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12366 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12367 |
GIR_EraseFromParent, /*InsnID*/0, |
12367 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12368 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12368 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12369 |
// GIR_Coverage, 1332, |
12369 |
// GIR_Coverage, 1332, |
| 12370 |
GIR_Done, |
12370 |
GIR_Done, |
| 12371 |
// Label 808: @30108 |
12371 |
// Label 808: @30108 |
| 12372 |
GIM_Try, /*On fail goto*//*Label 809*/ 30164, // Rule ID 1333 // |
12372 |
GIM_Try, /*On fail goto*//*Label 809*/ 30164, // Rule ID 1333 // |
| 12373 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
12373 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 12374 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w, |
12374 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w, |
| 12375 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
12375 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 12376 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
12376 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 12377 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
12377 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 12378 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
12378 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 12379 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
12379 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 12380 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
12380 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 12381 |
// (intrinsic_w_chain:{ *:[i32] } 5708:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
12381 |
// (intrinsic_w_chain:{ *:[i32] } 5708:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 12382 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W_MMR2, |
12382 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W_MMR2, |
| 12383 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12383 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12384 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12384 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12385 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12385 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12386 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12386 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12387 |
GIR_EraseFromParent, /*InsnID*/0, |
12387 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12388 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12388 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12389 |
// GIR_Coverage, 1333, |
12389 |
// GIR_Coverage, 1333, |
| 12390 |
GIR_Done, |
12390 |
GIR_Done, |
| 12391 |
// Label 809: @30164 |
12391 |
// Label 809: @30164 |
| 12392 |
GIM_Try, /*On fail goto*//*Label 810*/ 30220, // Rule ID 1334 // |
12392 |
GIM_Try, /*On fail goto*//*Label 810*/ 30220, // Rule ID 1334 // |
| 12393 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
12393 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 12394 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph, |
12394 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph, |
| 12395 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
12395 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 12396 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
12396 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 12397 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
12397 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 12398 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12398 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12399 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12399 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12400 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12400 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12401 |
// (intrinsic_w_chain:{ *:[v2i16] } 5709:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
12401 |
// (intrinsic_w_chain:{ *:[v2i16] } 5709:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 12402 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH_MMR2, |
12402 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH_MMR2, |
| 12403 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12403 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12404 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12404 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12405 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12405 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12406 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12406 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12407 |
GIR_EraseFromParent, /*InsnID*/0, |
12407 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12408 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12408 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12409 |
// GIR_Coverage, 1334, |
12409 |
// GIR_Coverage, 1334, |
| 12410 |
GIR_Done, |
12410 |
GIR_Done, |
| 12411 |
// Label 810: @30220 |
12411 |
// Label 810: @30220 |
| 12412 |
GIM_Try, /*On fail goto*//*Label 811*/ 30276, // Rule ID 1335 // |
12412 |
GIM_Try, /*On fail goto*//*Label 811*/ 30276, // Rule ID 1335 // |
| 12413 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
12413 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 12414 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w, |
12414 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w, |
| 12415 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
12415 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 12416 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
12416 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 12417 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
12417 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 12418 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
12418 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 12419 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
12419 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 12420 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
12420 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 12421 |
// (intrinsic_w_chain:{ *:[i32] } 5710:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
12421 |
// (intrinsic_w_chain:{ *:[i32] } 5710:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 12422 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W_MMR2, |
12422 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W_MMR2, |
| 12423 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12423 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12424 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12424 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12425 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12425 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12426 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12426 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12427 |
GIR_EraseFromParent, /*InsnID*/0, |
12427 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12428 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12428 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12429 |
// GIR_Coverage, 1335, |
12429 |
// GIR_Coverage, 1335, |
| 12430 |
GIR_Done, |
12430 |
GIR_Done, |
| 12431 |
// Label 811: @30276 |
12431 |
// Label 811: @30276 |
| 12432 |
GIM_Try, /*On fail goto*//*Label 812*/ 30332, // Rule ID 1336 // |
12432 |
GIM_Try, /*On fail goto*//*Label 812*/ 30332, // Rule ID 1336 // |
| 12433 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
12433 |
GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips, |
| 12434 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph, |
12434 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph, |
| 12435 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
12435 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8, |
| 12436 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
12436 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 12437 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
12437 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 12438 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12438 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12439 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
12439 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID, |
| 12440 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
12440 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID, |
| 12441 |
// (intrinsic_w_chain:{ *:[v4i8] } 5758:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
12441 |
// (intrinsic_w_chain:{ *:[v4i8] } 5758:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) |
| 12442 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH_MMR2, |
12442 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH_MMR2, |
| 12443 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12443 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12444 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
12444 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 12445 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
12445 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 12446 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12446 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12447 |
GIR_EraseFromParent, /*InsnID*/0, |
12447 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12448 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12448 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12449 |
// GIR_Coverage, 1336, |
12449 |
// GIR_Coverage, 1336, |
| 12450 |
GIR_Done, |
12450 |
GIR_Done, |
| 12451 |
// Label 812: @30332 |
12451 |
// Label 812: @30332 |
| 12452 |
GIM_Try, /*On fail goto*//*Label 813*/ 30380, // Rule ID 1885 // |
12452 |
GIM_Try, /*On fail goto*//*Label 813*/ 30380, // Rule ID 1885 // |
| 12453 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
12453 |
GIM_CheckFeatures, GIFBS_HasDSPR2, |
| 12454 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_ph, |
12454 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_ph, |
| 12455 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
12455 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16, |
| 12456 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
12456 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16, |
| 12457 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
12457 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16, |
| 12458 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
12458 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID, |
| 12459 |
// (intrinsic_w_chain:{ *:[v2i16] } 5699:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) |
12459 |
// (intrinsic_w_chain:{ *:[v2i16] } 5699:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) |
| 12460 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_PH, |
12460 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_PH, |
| 12461 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12461 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12462 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
12462 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 12463 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
12463 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
| 12464 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12464 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12465 |
GIR_EraseFromParent, /*InsnID*/0, |
12465 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12466 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12466 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12467 |
// GIR_Coverage, 1885, |
12467 |
// GIR_Coverage, 1885, |
| 12468 |
GIR_Done, |
12468 |
GIR_Done, |
| 12469 |
// Label 813: @30380 |
12469 |
// Label 813: @30380 |
| 12470 |
GIM_Try, /*On fail goto*//*Label 814*/ 30428, // Rule ID 1891 // |
12470 |
GIM_Try, /*On fail goto*//*Label 814*/ 30428, // Rule ID 1891 // |
| 12471 |
GIM_CheckFeatures, GIFBS_HasDSP, |
12471 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 12472 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addsc, |
12472 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addsc, |
| 12473 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
12473 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 12474 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
12474 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 12475 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
12475 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 12476 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
12476 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 12477 |
// (intrinsic_w_chain:{ *:[i32] } 5254:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) |
12477 |
// (intrinsic_w_chain:{ *:[i32] } 5254:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) |
| 12478 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDSC, |
12478 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDSC, |
| 12479 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12479 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12480 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
12480 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 12481 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
12481 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
| 12482 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12482 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12483 |
GIR_EraseFromParent, /*InsnID*/0, |
12483 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12484 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12484 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12485 |
// GIR_Coverage, 1891, |
12485 |
// GIR_Coverage, 1891, |
| 12486 |
GIR_Done, |
12486 |
GIR_Done, |
| 12487 |
// Label 814: @30428 |
12487 |
// Label 814: @30428 |
| 12488 |
GIM_Try, /*On fail goto*//*Label 815*/ 30476, // Rule ID 1893 // |
12488 |
GIM_Try, /*On fail goto*//*Label 815*/ 30476, // Rule ID 1893 // |
| 12489 |
GIM_CheckFeatures, GIFBS_HasDSP, |
12489 |
GIM_CheckFeatures, GIFBS_HasDSP, |
| 12490 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addwc, |
12490 |
GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addwc, |
| 12491 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
12491 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 12492 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
12492 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 12493 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
12493 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 12494 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
12494 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 12495 |
// (intrinsic_w_chain:{ *:[i32] } 5269:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) |
12495 |
// (intrinsic_w_chain:{ *:[i32] } 5269:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) |
| 12496 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDWC, |
12496 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDWC, |
| 12497 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12497 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12498 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
12498 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a |
| 12499 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
12499 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b |
| 12500 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
12500 |
GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, |
| 12501 |
GIR_EraseFromParent, /*InsnID*/0, |
12501 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12502 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12502 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12503 |
// GIR_Coverage, 1893, |
12503 |
// GIR_Coverage, 1893, |
| 12504 |
GIR_Done, |
12504 |
GIR_Done, |
| 12505 |
// Label 815: @30476 |
12505 |
// Label 815: @30476 |
| 12506 |
GIM_Reject, |
12506 |
GIM_Reject, |
| 12507 |
// Label 744: @30477 |
12507 |
// Label 744: @30477 |
| 12508 |
GIM_Reject, |
12508 |
GIM_Reject, |
| 12509 |
// Label 18: @30478 |
12509 |
// Label 18: @30478 |
| 12510 |
GIM_Try, /*On fail goto*//*Label 816*/ 30543, // Rule ID 1566 // |
12510 |
GIM_Try, /*On fail goto*//*Label 816*/ 30543, // Rule ID 1566 // |
| 12511 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
12511 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
| 12512 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
12512 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 12513 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
12513 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 12514 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
12514 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 12515 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12515 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12516 |
// (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] }) |
12516 |
// (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] }) |
| 12517 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
12517 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12518 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
12518 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 12519 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12519 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12520 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
12520 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12521 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
12521 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 12522 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
12522 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12523 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12523 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12524 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
12524 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 12525 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
12525 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 12526 |
GIR_EraseFromParent, /*InsnID*/0, |
12526 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12527 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
12527 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 12528 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
12528 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 12529 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
12529 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 12530 |
// GIR_Coverage, 1566, |
12530 |
// GIR_Coverage, 1566, |
| 12531 |
GIR_Done, |
12531 |
GIR_Done, |
| 12532 |
// Label 816: @30543 |
12532 |
// Label 816: @30543 |
| 12533 |
GIM_Reject, |
12533 |
GIM_Reject, |
| 12534 |
// Label 19: @30544 |
12534 |
// Label 19: @30544 |
| 12535 |
GIM_Try, /*On fail goto*//*Label 817*/ 30606, // Rule ID 1561 // |
12535 |
GIM_Try, /*On fail goto*//*Label 817*/ 30606, // Rule ID 1561 // |
| 12536 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
12536 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
| 12537 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
12537 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 12538 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
12538 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 12539 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
12539 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 12540 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
12540 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 12541 |
// (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src) => (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] }) |
12541 |
// (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src) => (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] }) |
| 12542 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
12542 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 12543 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
12543 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 12544 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12544 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12545 |
GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src |
12545 |
GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src |
| 12546 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::GPR32RegClassID, |
12546 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::GPR32RegClassID, |
| 12547 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID, |
12547 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID, |
| 12548 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL, |
12548 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL, |
| 12549 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12549 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12550 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12550 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12551 |
GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
12551 |
GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 12552 |
GIR_EraseFromParent, /*InsnID*/0, |
12552 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12553 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12553 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12554 |
// GIR_Coverage, 1561, |
12554 |
// GIR_Coverage, 1561, |
| 12555 |
GIR_Done, |
12555 |
GIR_Done, |
| 12556 |
// Label 817: @30606 |
12556 |
// Label 817: @30606 |
| 12557 |
GIM_Reject, |
12557 |
GIM_Reject, |
| 12558 |
// Label 20: @30607 |
12558 |
// Label 20: @30607 |
| 12559 |
GIM_Try, /*On fail goto*//*Label 818*/ 30666, |
12559 |
GIM_Try, /*On fail goto*//*Label 818*/ 30666, |
| 12560 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
12560 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 12561 |
GIM_Try, /*On fail goto*//*Label 819*/ 30639, // Rule ID 2116 // |
12561 |
GIM_Try, /*On fail goto*//*Label 819*/ 30639, // Rule ID 2116 // |
| 12562 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
12562 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 12563 |
GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_I64_Predicate_immLi16, |
12563 |
GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_I64_Predicate_immLi16, |
| 12564 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
12564 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 12565 |
// MIs[0] Operand 1 |
12565 |
// MIs[0] Operand 1 |
| 12566 |
// No operand predicates |
12566 |
// No operand predicates |
| 12567 |
// (imm:{ *:[i32] })<>:$imm => (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<>:$imm) |
12567 |
// (imm:{ *:[i32] })<>:$imm => (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<>:$imm) |
| 12568 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LI16_MM, |
12568 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LI16_MM, |
| 12569 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
12569 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 12570 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
12570 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 12571 |
GIR_EraseFromParent, /*InsnID*/0, |
12571 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12572 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12572 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12573 |
// GIR_Coverage, 2116, |
12573 |
// GIR_Coverage, 2116, |
| 12574 |
GIR_Done, |
12574 |
GIR_Done, |
| 12575 |
// Label 819: @30639 |
12575 |
// Label 819: @30639 |
| 12576 |
GIM_Try, /*On fail goto*//*Label 820*/ 30665, // Rule ID 1809 // |
12576 |
GIM_Try, /*On fail goto*//*Label 820*/ 30665, // Rule ID 1809 // |
| 12577 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
12577 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 12578 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
12578 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 12579 |
// MIs[0] Operand 1 |
12579 |
// MIs[0] Operand 1 |
| 12580 |
// No operand predicates |
12580 |
// No operand predicates |
| 12581 |
// (imm:{ *:[i32] }):$imm => (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] }) |
12581 |
// (imm:{ *:[i32] }):$imm => (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] }) |
| 12582 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LwConstant32, |
12582 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LwConstant32, |
| 12583 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx |
12583 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx |
| 12584 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
12584 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 12585 |
GIR_AddImm, /*InsnID*/0, /*Imm*/-1, |
12585 |
GIR_AddImm, /*InsnID*/0, /*Imm*/-1, |
| 12586 |
GIR_EraseFromParent, /*InsnID*/0, |
12586 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12587 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
12587 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 12588 |
// GIR_Coverage, 1809, |
12588 |
// GIR_Coverage, 1809, |
| 12589 |
GIR_Done, |
12589 |
GIR_Done, |
| 12590 |
// Label 820: @30665 |
12590 |
// Label 820: @30665 |
| 12591 |
GIM_Reject, |
12591 |
GIM_Reject, |
| 12592 |
// Label 818: @30666 |
12592 |
// Label 818: @30666 |
| 12593 |
GIM_Reject, |
12593 |
GIM_Reject, |
| 12594 |
// Label 21: @30667 |
12594 |
// Label 21: @30667 |
| 12595 |
GIM_Try, /*On fail goto*//*Label 821*/ 31924, |
12595 |
GIM_Try, /*On fail goto*//*Label 821*/ 31924, |
| 12596 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
12596 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 12597 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
12597 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 12598 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
12598 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 12599 |
GIM_Try, /*On fail goto*//*Label 822*/ 30780, // Rule ID 1600 // |
12599 |
GIM_Try, /*On fail goto*//*Label 822*/ 30780, // Rule ID 1600 // |
| 12600 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
12600 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12601 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR, |
12601 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR, |
| 12602 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
12602 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12603 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
12603 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12604 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12604 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12605 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
12605 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12606 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
12606 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 12607 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
12607 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 12608 |
// MIs[2] Operand 1 |
12608 |
// MIs[2] Operand 1 |
| 12609 |
// No operand predicates |
12609 |
// No operand predicates |
| 12610 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
12610 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12611 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
12611 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12612 |
// (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRA:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm5), sub_32:{ *:[i32] }) |
12612 |
// (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRA:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm5), sub_32:{ *:[i32] }) |
| 12613 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
12613 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12614 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
12614 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 12615 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRA, |
12615 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRA, |
| 12616 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
12616 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 12617 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
12617 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 12618 |
GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5 |
12618 |
GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5 |
| 12619 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
12619 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12620 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
12620 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 12621 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12621 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12622 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
12622 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12623 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
12623 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 12624 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
12624 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12625 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12625 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12626 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
12626 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 12627 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
12627 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 12628 |
GIR_EraseFromParent, /*InsnID*/0, |
12628 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12629 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
12629 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 12630 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
12630 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 12631 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
12631 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 12632 |
// GIR_Coverage, 1600, |
12632 |
// GIR_Coverage, 1600, |
| 12633 |
GIR_Done, |
12633 |
GIR_Done, |
| 12634 |
// Label 822: @30780 |
12634 |
// Label 822: @30780 |
| 12635 |
GIM_Try, /*On fail goto*//*Label 823*/ 30879, // Rule ID 1598 // |
12635 |
GIM_Try, /*On fail goto*//*Label 823*/ 30879, // Rule ID 1598 // |
| 12636 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
12636 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12637 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR, |
12637 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR, |
| 12638 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
12638 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12639 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
12639 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12640 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12640 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12641 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
12641 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12642 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
12642 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 12643 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
12643 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 12644 |
// MIs[2] Operand 1 |
12644 |
// MIs[2] Operand 1 |
| 12645 |
// No operand predicates |
12645 |
// No operand predicates |
| 12646 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
12646 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12647 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
12647 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12648 |
// (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm5), sub_32:{ *:[i32] }) |
12648 |
// (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm5), sub_32:{ *:[i32] }) |
| 12649 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
12649 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12650 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
12650 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 12651 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRL, |
12651 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRL, |
| 12652 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
12652 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 12653 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
12653 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 12654 |
GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5 |
12654 |
GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5 |
| 12655 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
12655 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12656 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
12656 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 12657 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12657 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12658 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
12658 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12659 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
12659 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 12660 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
12660 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12661 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12661 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12662 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
12662 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 12663 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
12663 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 12664 |
GIR_EraseFromParent, /*InsnID*/0, |
12664 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12665 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
12665 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 12666 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
12666 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 12667 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
12667 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 12668 |
// GIR_Coverage, 1598, |
12668 |
// GIR_Coverage, 1598, |
| 12669 |
GIR_Done, |
12669 |
GIR_Done, |
| 12670 |
// Label 823: @30879 |
12670 |
// Label 823: @30879 |
| 12671 |
GIM_Try, /*On fail goto*//*Label 824*/ 30978, // Rule ID 1596 // |
12671 |
GIM_Try, /*On fail goto*//*Label 824*/ 30978, // Rule ID 1596 // |
| 12672 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
12672 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12673 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, |
12673 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, |
| 12674 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
12674 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12675 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
12675 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12676 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12676 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12677 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
12677 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 12678 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
12678 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, |
| 12679 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
12679 |
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 12680 |
// MIs[2] Operand 1 |
12680 |
// MIs[2] Operand 1 |
| 12681 |
// No operand predicates |
12681 |
// No operand predicates |
| 12682 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
12682 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12683 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
12683 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 12684 |
// (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm5), sub_32:{ *:[i32] }) |
12684 |
// (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm5)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm5), sub_32:{ *:[i32] }) |
| 12685 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
12685 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12686 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
12686 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 12687 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL, |
12687 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL, |
| 12688 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
12688 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 12689 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
12689 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 12690 |
GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5 |
12690 |
GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5 |
| 12691 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
12691 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12692 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
12692 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 12693 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12693 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12694 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
12694 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12695 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
12695 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 12696 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
12696 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12697 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12697 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12698 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
12698 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 12699 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
12699 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 12700 |
GIR_EraseFromParent, /*InsnID*/0, |
12700 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12701 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
12701 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 12702 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
12702 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 12703 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
12703 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 12704 |
// GIR_Coverage, 1596, |
12704 |
// GIR_Coverage, 1596, |
| 12705 |
GIR_Done, |
12705 |
GIR_Done, |
| 12706 |
// Label 824: @30978 |
12706 |
// Label 824: @30978 |
| 12707 |
GIM_Try, /*On fail goto*//*Label 825*/ 31070, // Rule ID 1591 // |
12707 |
GIM_Try, /*On fail goto*//*Label 825*/ 31070, // Rule ID 1591 // |
| 12708 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
12708 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12709 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, |
12709 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, |
| 12710 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
12710 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12711 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
12711 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12712 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12712 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12713 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
12713 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 12714 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
12714 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12715 |
// (sext:{ *:[i64] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ADDu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
12715 |
// (sext:{ *:[i64] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ADDu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
| 12716 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
12716 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12717 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
12717 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 12718 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::ADDu, |
12718 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::ADDu, |
| 12719 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
12719 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 12720 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
12720 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 12721 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
12721 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 12722 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
12722 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12723 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
12723 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 12724 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12724 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12725 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
12725 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12726 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
12726 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 12727 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
12727 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12728 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12728 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12729 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
12729 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 12730 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
12730 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 12731 |
GIR_EraseFromParent, /*InsnID*/0, |
12731 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12732 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
12732 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 12733 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
12733 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 12734 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
12734 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 12735 |
// GIR_Coverage, 1591, |
12735 |
// GIR_Coverage, 1591, |
| 12736 |
GIR_Done, |
12736 |
GIR_Done, |
| 12737 |
// Label 825: @31070 |
12737 |
// Label 825: @31070 |
| 12738 |
GIM_Try, /*On fail goto*//*Label 826*/ 31162, // Rule ID 1601 // |
12738 |
GIM_Try, /*On fail goto*//*Label 826*/ 31162, // Rule ID 1601 // |
| 12739 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
12739 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12740 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR, |
12740 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR, |
| 12741 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
12741 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12742 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
12742 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12743 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12743 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12744 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
12744 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 12745 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
12745 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12746 |
// (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRAV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
12746 |
// (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRAV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
| 12747 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
12747 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12748 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
12748 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 12749 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRAV, |
12749 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRAV, |
| 12750 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
12750 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 12751 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
12751 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 12752 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
12752 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 12753 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
12753 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12754 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
12754 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 12755 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12755 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12756 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
12756 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12757 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
12757 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 12758 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
12758 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12759 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12759 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12760 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
12760 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 12761 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
12761 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 12762 |
GIR_EraseFromParent, /*InsnID*/0, |
12762 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12763 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
12763 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 12764 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
12764 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 12765 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
12765 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 12766 |
// GIR_Coverage, 1601, |
12766 |
// GIR_Coverage, 1601, |
| 12767 |
GIR_Done, |
12767 |
GIR_Done, |
| 12768 |
// Label 826: @31162 |
12768 |
// Label 826: @31162 |
| 12769 |
GIM_Try, /*On fail goto*//*Label 827*/ 31254, // Rule ID 1599 // |
12769 |
GIM_Try, /*On fail goto*//*Label 827*/ 31254, // Rule ID 1599 // |
| 12770 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
12770 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12771 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR, |
12771 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR, |
| 12772 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
12772 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12773 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
12773 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12774 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12774 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12775 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
12775 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 12776 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
12776 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12777 |
// (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
12777 |
// (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
| 12778 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
12778 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12779 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
12779 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 12780 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRLV, |
12780 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SRLV, |
| 12781 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
12781 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 12782 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
12782 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 12783 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
12783 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 12784 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
12784 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12785 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
12785 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 12786 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12786 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12787 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
12787 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12788 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
12788 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 12789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
12789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12790 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12790 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12791 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
12791 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 12792 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
12792 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 12793 |
GIR_EraseFromParent, /*InsnID*/0, |
12793 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12794 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
12794 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 12795 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
12795 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 12796 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
12796 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 12797 |
// GIR_Coverage, 1599, |
12797 |
// GIR_Coverage, 1599, |
| 12798 |
GIR_Done, |
12798 |
GIR_Done, |
| 12799 |
// Label 827: @31254 |
12799 |
// Label 827: @31254 |
| 12800 |
GIM_Try, /*On fail goto*//*Label 828*/ 31348, // Rule ID 1776 // |
12800 |
GIM_Try, /*On fail goto*//*Label 828*/ 31348, // Rule ID 1776 // |
| 12801 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
12801 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
| 12802 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
12802 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12803 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
12803 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, |
| 12804 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
12804 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12805 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
12805 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12806 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12806 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12807 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
12807 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 12808 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
12808 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12809 |
// (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL_R6:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
12809 |
// (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL_R6:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
| 12810 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
12810 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12811 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
12811 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 12812 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MUL_R6, |
12812 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MUL_R6, |
| 12813 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
12813 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 12814 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
12814 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 12815 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
12815 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 12816 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
12816 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12817 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
12817 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 12818 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12818 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12819 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
12819 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12820 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
12820 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 12821 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
12821 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12822 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12822 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12823 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
12823 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 12824 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
12824 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 12825 |
GIR_EraseFromParent, /*InsnID*/0, |
12825 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12826 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
12826 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 12827 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
12827 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 12828 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
12828 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 12829 |
// GIR_Coverage, 1776, |
12829 |
// GIR_Coverage, 1776, |
| 12830 |
GIR_Done, |
12830 |
GIR_Done, |
| 12831 |
// Label 828: @31348 |
12831 |
// Label 828: @31348 |
| 12832 |
GIM_Try, /*On fail goto*//*Label 829*/ 31442, // Rule ID 1777 // |
12832 |
GIM_Try, /*On fail goto*//*Label 829*/ 31442, // Rule ID 1777 // |
| 12833 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
12833 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
| 12834 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
12834 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12835 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SDIV, |
12835 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SDIV, |
| 12836 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
12836 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12837 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
12837 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12838 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12838 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12839 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
12839 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 12840 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
12840 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12841 |
// (sext:{ *:[i64] } (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
12841 |
// (sext:{ *:[i64] } (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
| 12842 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
12842 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12843 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
12843 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 12844 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::DIV, |
12844 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::DIV, |
| 12845 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
12845 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 12846 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
12846 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 12847 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
12847 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 12848 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
12848 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12849 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
12849 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 12850 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12850 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12851 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
12851 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12852 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
12852 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 12853 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
12853 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12854 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12854 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12855 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
12855 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 12856 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
12856 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 12857 |
GIR_EraseFromParent, /*InsnID*/0, |
12857 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12858 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
12858 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 12859 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
12859 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 12860 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
12860 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 12861 |
// GIR_Coverage, 1777, |
12861 |
// GIR_Coverage, 1777, |
| 12862 |
GIR_Done, |
12862 |
GIR_Done, |
| 12863 |
// Label 829: @31442 |
12863 |
// Label 829: @31442 |
| 12864 |
GIM_Try, /*On fail goto*//*Label 830*/ 31534, // Rule ID 1597 // |
12864 |
GIM_Try, /*On fail goto*//*Label 830*/ 31534, // Rule ID 1597 // |
| 12865 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
12865 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12866 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, |
12866 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, |
| 12867 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
12867 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12868 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
12868 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12869 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12869 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12870 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
12870 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 12871 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
12871 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12872 |
// (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
12872 |
// (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
| 12873 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
12873 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12874 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
12874 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 12875 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLLV, |
12875 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLLV, |
| 12876 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
12876 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 12877 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
12877 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 12878 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
12878 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 12879 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
12879 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12880 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
12880 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 12881 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12881 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12882 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
12882 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12883 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
12883 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 12884 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
12884 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12885 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12885 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12886 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
12886 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 12887 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
12887 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 12888 |
GIR_EraseFromParent, /*InsnID*/0, |
12888 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12889 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
12889 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 12890 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
12890 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 12891 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
12891 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 12892 |
// GIR_Coverage, 1597, |
12892 |
// GIR_Coverage, 1597, |
| 12893 |
GIR_Done, |
12893 |
GIR_Done, |
| 12894 |
// Label 830: @31534 |
12894 |
// Label 830: @31534 |
| 12895 |
GIM_Try, /*On fail goto*//*Label 831*/ 31628, // Rule ID 1779 // |
12895 |
GIM_Try, /*On fail goto*//*Label 831*/ 31628, // Rule ID 1779 // |
| 12896 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
12896 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
| 12897 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
12897 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12898 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SREM, |
12898 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SREM, |
| 12899 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
12899 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12900 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
12900 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12901 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12901 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12902 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
12902 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 12903 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
12903 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12904 |
// (sext:{ *:[i64] } (srem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MOD:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
12904 |
// (sext:{ *:[i64] } (srem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MOD:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
| 12905 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
12905 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12906 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
12906 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 12907 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MOD, |
12907 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MOD, |
| 12908 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
12908 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 12909 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
12909 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 12910 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
12910 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 12911 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
12911 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12912 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
12912 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 12913 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12913 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12914 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
12914 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12915 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
12915 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 12916 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
12916 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12917 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12917 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12918 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
12918 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 12919 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
12919 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 12920 |
GIR_EraseFromParent, /*InsnID*/0, |
12920 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12921 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
12921 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 12922 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
12922 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 12923 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
12923 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 12924 |
// GIR_Coverage, 1779, |
12924 |
// GIR_Coverage, 1779, |
| 12925 |
GIR_Done, |
12925 |
GIR_Done, |
| 12926 |
// Label 831: @31628 |
12926 |
// Label 831: @31628 |
| 12927 |
GIM_Try, /*On fail goto*//*Label 832*/ 31720, // Rule ID 1592 // |
12927 |
GIM_Try, /*On fail goto*//*Label 832*/ 31720, // Rule ID 1592 // |
| 12928 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
12928 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12929 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, |
12929 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, |
| 12930 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
12930 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12931 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
12931 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12932 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12932 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12933 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
12933 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 12934 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
12934 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12935 |
// (sext:{ *:[i64] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SUBu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
12935 |
// (sext:{ *:[i64] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SUBu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
| 12936 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
12936 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12937 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
12937 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 12938 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SUBu, |
12938 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SUBu, |
| 12939 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
12939 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 12940 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
12940 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 12941 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
12941 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 12942 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
12942 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12943 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
12943 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 12944 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12944 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12945 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
12945 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12946 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
12946 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 12947 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
12947 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12948 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12948 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12949 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
12949 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 12950 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
12950 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 12951 |
GIR_EraseFromParent, /*InsnID*/0, |
12951 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12952 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
12952 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 12953 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
12953 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 12954 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
12954 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 12955 |
// GIR_Coverage, 1592, |
12955 |
// GIR_Coverage, 1592, |
| 12956 |
GIR_Done, |
12956 |
GIR_Done, |
| 12957 |
// Label 832: @31720 |
12957 |
// Label 832: @31720 |
| 12958 |
GIM_Try, /*On fail goto*//*Label 833*/ 31814, // Rule ID 1778 // |
12958 |
GIM_Try, /*On fail goto*//*Label 833*/ 31814, // Rule ID 1778 // |
| 12959 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
12959 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
| 12960 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
12960 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12961 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_UDIV, |
12961 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_UDIV, |
| 12962 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
12962 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12963 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
12963 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12964 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12964 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12965 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
12965 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 12966 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
12966 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12967 |
// (sext:{ *:[i64] } (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIVU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
12967 |
// (sext:{ *:[i64] } (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIVU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
| 12968 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
12968 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 12969 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
12969 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 12970 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::DIVU, |
12970 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::DIVU, |
| 12971 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
12971 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 12972 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
12972 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 12973 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
12973 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 12974 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
12974 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 12975 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
12975 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 12976 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
12976 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 12977 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
12977 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 12978 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
12978 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 12979 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
12979 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 12980 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
12980 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 12981 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
12981 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 12982 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
12982 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 12983 |
GIR_EraseFromParent, /*InsnID*/0, |
12983 |
GIR_EraseFromParent, /*InsnID*/0, |
| 12984 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
12984 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 12985 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
12985 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 12986 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
12986 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 12987 |
// GIR_Coverage, 1778, |
12987 |
// GIR_Coverage, 1778, |
| 12988 |
GIR_Done, |
12988 |
GIR_Done, |
| 12989 |
// Label 833: @31814 |
12989 |
// Label 833: @31814 |
| 12990 |
GIM_Try, /*On fail goto*//*Label 834*/ 31908, // Rule ID 1780 // |
12990 |
GIM_Try, /*On fail goto*//*Label 834*/ 31908, // Rule ID 1780 // |
| 12991 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
12991 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
| 12992 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
12992 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 12993 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_UREM, |
12993 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_UREM, |
| 12994 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
12994 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 12995 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
12995 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 12996 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
12996 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 12997 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
12997 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 12998 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
12998 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 12999 |
// (sext:{ *:[i64] } (urem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MODU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
12999 |
// (sext:{ *:[i64] } (urem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MODU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] }) |
| 13000 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
13000 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 13001 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
13001 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 13002 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MODU, |
13002 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::MODU, |
| 13003 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
13003 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 13004 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
13004 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 13005 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
13005 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 13006 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
13006 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 13007 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
13007 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, |
| 13008 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
13008 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 13009 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
13009 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13010 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
13010 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, |
| 13011 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
13011 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 13012 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
13012 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 13013 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
13013 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 13014 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
13014 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 13015 |
GIR_EraseFromParent, /*InsnID*/0, |
13015 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13016 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
13016 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::GPR64RegClassID, |
| 13017 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
13017 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::GPR64RegClassID, |
| 13018 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
13018 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Mips::GPR32RegClassID, |
| 13019 |
// GIR_Coverage, 1780, |
13019 |
// GIR_Coverage, 1780, |
| 13020 |
GIR_Done, |
13020 |
GIR_Done, |
| 13021 |
// Label 834: @31908 |
13021 |
// Label 834: @31908 |
| 13022 |
GIM_Try, /*On fail goto*//*Label 835*/ 31923, // Rule ID 1568 // |
13022 |
GIM_Try, /*On fail goto*//*Label 835*/ 31923, // Rule ID 1568 // |
| 13023 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
13023 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
| 13024 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
13024 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 13025 |
// (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src) |
13025 |
// (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src) |
| 13026 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL64_32, |
13026 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL64_32, |
| 13027 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13027 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13028 |
// GIR_Coverage, 1568, |
13028 |
// GIR_Coverage, 1568, |
| 13029 |
GIR_Done, |
13029 |
GIR_Done, |
| 13030 |
// Label 835: @31923 |
13030 |
// Label 835: @31923 |
| 13031 |
GIM_Reject, |
13031 |
GIM_Reject, |
| 13032 |
// Label 821: @31924 |
13032 |
// Label 821: @31924 |
| 13033 |
GIM_Reject, |
13033 |
GIM_Reject, |
| 13034 |
// Label 22: @31925 |
13034 |
// Label 22: @31925 |
| 13035 |
GIM_Try, /*On fail goto*//*Label 836*/ 32118, |
13035 |
GIM_Try, /*On fail goto*//*Label 836*/ 32118, |
| 13036 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
13036 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, |
| 13037 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
13037 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 13038 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
13038 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 13039 |
GIM_Try, /*On fail goto*//*Label 837*/ 31992, // Rule ID 268 // |
13039 |
GIM_Try, /*On fail goto*//*Label 837*/ 31992, // Rule ID 268 // |
| 13040 |
GIM_CheckFeatures, GIFBS_HasCnMips, |
13040 |
GIM_CheckFeatures, GIFBS_HasCnMips, |
| 13041 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
13041 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13042 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
13042 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 13043 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
13043 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 13044 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
13044 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 13045 |
// MIs[1] Operand 1 |
13045 |
// MIs[1] Operand 1 |
| 13046 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
13046 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 13047 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
13047 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 13048 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
13048 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 13049 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13049 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13050 |
// (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] })) => (SEQ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
13050 |
// (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] })) => (SEQ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 13051 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEQ, |
13051 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEQ, |
| 13052 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
13052 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 13053 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs |
13053 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs |
| 13054 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt |
13054 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt |
| 13055 |
GIR_EraseFromParent, /*InsnID*/0, |
13055 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13056 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13056 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13057 |
// GIR_Coverage, 268, |
13057 |
// GIR_Coverage, 268, |
| 13058 |
GIR_Done, |
13058 |
GIR_Done, |
| 13059 |
// Label 837: @31992 |
13059 |
// Label 837: @31992 |
| 13060 |
GIM_Try, /*On fail goto*//*Label 838*/ 32045, // Rule ID 270 // |
13060 |
GIM_Try, /*On fail goto*//*Label 838*/ 32045, // Rule ID 270 // |
| 13061 |
GIM_CheckFeatures, GIFBS_HasCnMips, |
13061 |
GIM_CheckFeatures, GIFBS_HasCnMips, |
| 13062 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
13062 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 13063 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
13063 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 13064 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
13064 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 13065 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
13065 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 13066 |
// MIs[1] Operand 1 |
13066 |
// MIs[1] Operand 1 |
| 13067 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
13067 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 13068 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
13068 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 13069 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
13069 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 13070 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13070 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13071 |
// (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] })) => (SNE:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
13071 |
// (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] })) => (SNE:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 13072 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SNE, |
13072 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SNE, |
| 13073 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
13073 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 13074 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs |
13074 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs |
| 13075 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt |
13075 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt |
| 13076 |
GIR_EraseFromParent, /*InsnID*/0, |
13076 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13077 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13077 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13078 |
// GIR_Coverage, 270, |
13078 |
// GIR_Coverage, 270, |
| 13079 |
GIR_Done, |
13079 |
GIR_Done, |
| 13080 |
// Label 838: @32045 |
13080 |
// Label 838: @32045 |
| 13081 |
GIM_Try, /*On fail goto*//*Label 839*/ 32117, |
13081 |
GIM_Try, /*On fail goto*//*Label 839*/ 32117, |
| 13082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
13082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 13083 |
GIM_Try, /*On fail goto*//*Label 840*/ 32090, // Rule ID 1567 // |
13083 |
GIM_Try, /*On fail goto*//*Label 840*/ 32090, // Rule ID 1567 // |
| 13084 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
13084 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
| 13085 |
// (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] }) |
13085 |
// (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] }) |
| 13086 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
13086 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 13087 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSLL64_32, |
13087 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSLL64_32, |
| 13088 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
13088 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 13089 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
13089 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 13090 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
13090 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 13091 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL, |
13091 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL, |
| 13092 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
13092 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 13093 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
13093 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 13094 |
GIR_AddImm, /*InsnID*/0, /*Imm*/32, |
13094 |
GIR_AddImm, /*InsnID*/0, /*Imm*/32, |
| 13095 |
GIR_EraseFromParent, /*InsnID*/0, |
13095 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13096 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13096 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13097 |
// GIR_Coverage, 1567, |
13097 |
// GIR_Coverage, 1567, |
| 13098 |
GIR_Done, |
13098 |
GIR_Done, |
| 13099 |
// Label 840: @32090 |
13099 |
// Label 840: @32090 |
| 13100 |
GIM_Try, /*On fail goto*//*Label 841*/ 32116, // Rule ID 1569 // |
13100 |
GIM_Try, /*On fail goto*//*Label 841*/ 32116, // Rule ID 1569 // |
| 13101 |
GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips, |
13101 |
GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips, |
| 13102 |
// (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] }) |
13102 |
// (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] }) |
| 13103 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DEXT64_32, |
13103 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DEXT64_32, |
| 13104 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
13104 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 13105 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
13105 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 13106 |
GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
13106 |
GIR_AddImm, /*InsnID*/0, /*Imm*/0, |
| 13107 |
GIR_AddImm, /*InsnID*/0, /*Imm*/32, |
13107 |
GIR_AddImm, /*InsnID*/0, /*Imm*/32, |
| 13108 |
GIR_EraseFromParent, /*InsnID*/0, |
13108 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13109 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13109 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13110 |
// GIR_Coverage, 1569, |
13110 |
// GIR_Coverage, 1569, |
| 13111 |
GIR_Done, |
13111 |
GIR_Done, |
| 13112 |
// Label 841: @32116 |
13112 |
// Label 841: @32116 |
| 13113 |
GIM_Reject, |
13113 |
GIM_Reject, |
| 13114 |
// Label 839: @32117 |
13114 |
// Label 839: @32117 |
| 13115 |
GIM_Reject, |
13115 |
GIM_Reject, |
| 13116 |
// Label 836: @32118 |
13116 |
// Label 836: @32118 |
| 13117 |
GIM_Reject, |
13117 |
GIM_Reject, |
| 13118 |
// Label 23: @32119 |
13118 |
// Label 23: @32119 |
| 13119 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 848*/ 33871, |
13119 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 848*/ 33871, |
| 13120 |
/*GILLT_s32*//*Label 842*/ 32133, |
13120 |
/*GILLT_s32*//*Label 842*/ 32133, |
| 13121 |
/*GILLT_s64*//*Label 843*/ 32386, 0, |
13121 |
/*GILLT_s64*//*Label 843*/ 32386, 0, |
| 13122 |
/*GILLT_v2s64*//*Label 844*/ 32520, 0, |
13122 |
/*GILLT_v2s64*//*Label 844*/ 32520, 0, |
| 13123 |
/*GILLT_v4s32*//*Label 845*/ 32552, |
13123 |
/*GILLT_v4s32*//*Label 845*/ 32552, |
| 13124 |
/*GILLT_v8s16*//*Label 846*/ 32821, |
13124 |
/*GILLT_v8s16*//*Label 846*/ 32821, |
| 13125 |
/*GILLT_v16s8*//*Label 847*/ 33218, |
13125 |
/*GILLT_v16s8*//*Label 847*/ 33218, |
| 13126 |
// Label 842: @32133 |
13126 |
// Label 842: @32133 |
| 13127 |
GIM_Try, /*On fail goto*//*Label 849*/ 32385, |
13127 |
GIM_Try, /*On fail goto*//*Label 849*/ 32385, |
| 13128 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
13128 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 13129 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
13129 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 13130 |
GIM_Try, /*On fail goto*//*Label 850*/ 32186, // Rule ID 55 // |
13130 |
GIM_Try, /*On fail goto*//*Label 850*/ 32186, // Rule ID 55 // |
| 13131 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
13131 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 13132 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
13132 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 13133 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
13133 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 13134 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13134 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13135 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
13135 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 13136 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
13136 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 13137 |
// MIs[1] Operand 1 |
13137 |
// MIs[1] Operand 1 |
| 13138 |
// No operand predicates |
13138 |
// No operand predicates |
| 13139 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13139 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13140 |
// (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt) |
13140 |
// (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt) |
| 13141 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL, |
13141 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL, |
| 13142 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
13142 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 13143 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
13143 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 13144 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
13144 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 13145 |
GIR_EraseFromParent, /*InsnID*/0, |
13145 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13146 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13146 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13147 |
// GIR_Coverage, 55, |
13147 |
// GIR_Coverage, 55, |
| 13148 |
GIR_Done, |
13148 |
GIR_Done, |
| 13149 |
// Label 850: @32186 |
13149 |
// Label 850: @32186 |
| 13150 |
GIM_Try, /*On fail goto*//*Label 851*/ 32229, // Rule ID 1791 // |
13150 |
GIM_Try, /*On fail goto*//*Label 851*/ 32229, // Rule ID 1791 // |
| 13151 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
13151 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 13152 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
13152 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 13153 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
13153 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 13154 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13154 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13155 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
13155 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 13156 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
13156 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 13157 |
// MIs[1] Operand 1 |
13157 |
// MIs[1] Operand 1 |
| 13158 |
// No operand predicates |
13158 |
// No operand predicates |
| 13159 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13159 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13160 |
// (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<>:$imm) => (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<>:$imm) |
13160 |
// (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<>:$imm) => (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<>:$imm) |
| 13161 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SllX16, |
13161 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SllX16, |
| 13162 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx |
13162 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx |
| 13163 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
13163 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
| 13164 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
13164 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 13165 |
GIR_EraseFromParent, /*InsnID*/0, |
13165 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13166 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13166 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13167 |
// GIR_Coverage, 1791, |
13167 |
// GIR_Coverage, 1791, |
| 13168 |
GIR_Done, |
13168 |
GIR_Done, |
| 13169 |
// Label 851: @32229 |
13169 |
// Label 851: @32229 |
| 13170 |
GIM_Try, /*On fail goto*//*Label 852*/ 32272, // Rule ID 2128 // |
13170 |
GIM_Try, /*On fail goto*//*Label 852*/ 32272, // Rule ID 2128 // |
| 13171 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
13171 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 13172 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
13172 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 13173 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
13173 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 13174 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13174 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13175 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
13175 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 13176 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt2Shift, |
13176 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt2Shift, |
| 13177 |
// MIs[1] Operand 1 |
13177 |
// MIs[1] Operand 1 |
| 13178 |
// No operand predicates |
13178 |
// No operand predicates |
| 13179 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13179 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13180 |
// (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
13180 |
// (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
| 13181 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL16_MM, |
13181 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL16_MM, |
| 13182 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
13182 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 13183 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
13183 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 13184 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
13184 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 13185 |
GIR_EraseFromParent, /*InsnID*/0, |
13185 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13186 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13186 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13187 |
// GIR_Coverage, 2128, |
13187 |
// GIR_Coverage, 2128, |
| 13188 |
GIR_Done, |
13188 |
GIR_Done, |
| 13189 |
// Label 852: @32272 |
13189 |
// Label 852: @32272 |
| 13190 |
GIM_Try, /*On fail goto*//*Label 853*/ 32315, // Rule ID 2129 // |
13190 |
GIM_Try, /*On fail goto*//*Label 853*/ 32315, // Rule ID 2129 // |
| 13191 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
13191 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 13192 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
13192 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 13193 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
13193 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 13194 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13194 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13195 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
13195 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 13196 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
13196 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 13197 |
// MIs[1] Operand 1 |
13197 |
// MIs[1] Operand 1 |
| 13198 |
// No operand predicates |
13198 |
// No operand predicates |
| 13199 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13199 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13200 |
// (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
13200 |
// (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
| 13201 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_MM, |
13201 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_MM, |
| 13202 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
13202 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 13203 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
13203 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 13204 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
13204 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 13205 |
GIR_EraseFromParent, /*InsnID*/0, |
13205 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13206 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13206 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13207 |
// GIR_Coverage, 2129, |
13207 |
// GIR_Coverage, 2129, |
| 13208 |
GIR_Done, |
13208 |
GIR_Done, |
| 13209 |
// Label 853: @32315 |
13209 |
// Label 853: @32315 |
| 13210 |
GIM_Try, /*On fail goto*//*Label 854*/ 32338, // Rule ID 58 // |
13210 |
GIM_Try, /*On fail goto*//*Label 854*/ 32338, // Rule ID 58 // |
| 13211 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
13211 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 13212 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
13212 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 13213 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
13213 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 13214 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
13214 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 13215 |
// (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
13215 |
// (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 13216 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV, |
13216 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV, |
| 13217 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13217 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13218 |
// GIR_Coverage, 58, |
13218 |
// GIR_Coverage, 58, |
| 13219 |
GIR_Done, |
13219 |
GIR_Done, |
| 13220 |
// Label 854: @32338 |
13220 |
// Label 854: @32338 |
| 13221 |
GIM_Try, /*On fail goto*//*Label 855*/ 32361, // Rule ID 1794 // |
13221 |
GIM_Try, /*On fail goto*//*Label 855*/ 32361, // Rule ID 1794 // |
| 13222 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
13222 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 13223 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
13223 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 13224 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
13224 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 13225 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
13225 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 13226 |
// (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) |
13226 |
// (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) |
| 13227 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SllvRxRy16, |
13227 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SllvRxRy16, |
| 13228 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13228 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13229 |
// GIR_Coverage, 1794, |
13229 |
// GIR_Coverage, 1794, |
| 13230 |
GIR_Done, |
13230 |
GIR_Done, |
| 13231 |
// Label 855: @32361 |
13231 |
// Label 855: @32361 |
| 13232 |
GIM_Try, /*On fail goto*//*Label 856*/ 32384, // Rule ID 2130 // |
13232 |
GIM_Try, /*On fail goto*//*Label 856*/ 32384, // Rule ID 2130 // |
| 13233 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
13233 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 13234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
13234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 13235 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
13235 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 13236 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
13236 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 13237 |
// (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) |
13237 |
// (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) |
| 13238 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV_MM, |
13238 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV_MM, |
| 13239 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13239 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13240 |
// GIR_Coverage, 2130, |
13240 |
// GIR_Coverage, 2130, |
| 13241 |
GIR_Done, |
13241 |
GIR_Done, |
| 13242 |
// Label 856: @32384 |
13242 |
// Label 856: @32384 |
| 13243 |
GIM_Reject, |
13243 |
GIM_Reject, |
| 13244 |
// Label 849: @32385 |
13244 |
// Label 849: @32385 |
| 13245 |
GIM_Reject, |
13245 |
GIM_Reject, |
| 13246 |
// Label 843: @32386 |
13246 |
// Label 843: @32386 |
| 13247 |
GIM_Try, /*On fail goto*//*Label 857*/ 32519, |
13247 |
GIM_Try, /*On fail goto*//*Label 857*/ 32519, |
| 13248 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
13248 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 13249 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
13249 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 13250 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
13250 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 13251 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
13251 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 13252 |
GIM_Try, /*On fail goto*//*Label 858*/ 32439, // Rule ID 204 // |
13252 |
GIM_Try, /*On fail goto*//*Label 858*/ 32439, // Rule ID 204 // |
| 13253 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
13253 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
| 13254 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13254 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13255 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
13255 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 13256 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt6, |
13256 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt6, |
| 13257 |
// MIs[1] Operand 1 |
13257 |
// MIs[1] Operand 1 |
| 13258 |
// No operand predicates |
13258 |
// No operand predicates |
| 13259 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13259 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13260 |
// (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt) |
13260 |
// (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt) |
| 13261 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLL, |
13261 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLL, |
| 13262 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
13262 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 13263 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
13263 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 13264 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
13264 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 13265 |
GIR_EraseFromParent, /*InsnID*/0, |
13265 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13266 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13266 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13267 |
// GIR_Coverage, 204, |
13267 |
// GIR_Coverage, 204, |
| 13268 |
GIR_Done, |
13268 |
GIR_Done, |
| 13269 |
// Label 858: @32439 |
13269 |
// Label 858: @32439 |
| 13270 |
GIM_Try, /*On fail goto*//*Label 859*/ 32503, // Rule ID 1562 // |
13270 |
GIM_Try, /*On fail goto*//*Label 859*/ 32503, // Rule ID 1562 // |
| 13271 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
13271 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
| 13272 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13272 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13273 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
13273 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 13274 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
13274 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 13275 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
13275 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 13276 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13276 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13277 |
// (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] })) |
13277 |
// (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] })) |
| 13278 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
13278 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 13279 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
13279 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 13280 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
13280 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 13281 |
GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs |
13281 |
GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs |
| 13282 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::GPR32RegClassID, |
13282 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::GPR32RegClassID, |
| 13283 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID, |
13283 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID, |
| 13284 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLLV, |
13284 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLLV, |
| 13285 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
13285 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 13286 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
13286 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 13287 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
13287 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 13288 |
GIR_EraseFromParent, /*InsnID*/0, |
13288 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13289 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13289 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13290 |
// GIR_Coverage, 1562, |
13290 |
// GIR_Coverage, 1562, |
| 13291 |
GIR_Done, |
13291 |
GIR_Done, |
| 13292 |
// Label 859: @32503 |
13292 |
// Label 859: @32503 |
| 13293 |
GIM_Try, /*On fail goto*//*Label 860*/ 32518, // Rule ID 207 // |
13293 |
GIM_Try, /*On fail goto*//*Label 860*/ 32518, // Rule ID 207 // |
| 13294 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
13294 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
| 13295 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
13295 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 13296 |
// (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
13296 |
// (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 13297 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSLLV, |
13297 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSLLV, |
| 13298 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13298 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13299 |
// GIR_Coverage, 207, |
13299 |
// GIR_Coverage, 207, |
| 13300 |
GIR_Done, |
13300 |
GIR_Done, |
| 13301 |
// Label 860: @32518 |
13301 |
// Label 860: @32518 |
| 13302 |
GIM_Reject, |
13302 |
GIM_Reject, |
| 13303 |
// Label 857: @32519 |
13303 |
// Label 857: @32519 |
| 13304 |
GIM_Reject, |
13304 |
GIM_Reject, |
| 13305 |
// Label 844: @32520 |
13305 |
// Label 844: @32520 |
| 13306 |
GIM_Try, /*On fail goto*//*Label 861*/ 32551, // Rule ID 948 // |
13306 |
GIM_Try, /*On fail goto*//*Label 861*/ 32551, // Rule ID 948 // |
| 13307 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
13307 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 13308 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
13308 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13309 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
13309 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 13310 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
13310 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 13311 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
13311 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 13312 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
13312 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 13313 |
// (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
13313 |
// (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 13314 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_D, |
13314 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_D, |
| 13315 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13315 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13316 |
// GIR_Coverage, 948, |
13316 |
// GIR_Coverage, 948, |
| 13317 |
GIR_Done, |
13317 |
GIR_Done, |
| 13318 |
// Label 861: @32551 |
13318 |
// Label 861: @32551 |
| 13319 |
GIM_Reject, |
13319 |
GIM_Reject, |
| 13320 |
// Label 845: @32552 |
13320 |
// Label 845: @32552 |
| 13321 |
GIM_Try, /*On fail goto*//*Label 862*/ 32820, |
13321 |
GIM_Try, /*On fail goto*//*Label 862*/ 32820, |
| 13322 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
13322 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13323 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
13323 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
13324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 13325 |
GIM_Try, /*On fail goto*//*Label 863*/ 32683, // Rule ID 2414 // |
13325 |
GIM_Try, /*On fail goto*//*Label 863*/ 32683, // Rule ID 2414 // |
| 13326 |
GIM_CheckFeatures, GIFBS_HasMSA, |
13326 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 13327 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13327 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13328 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
13328 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13329 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
13329 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13330 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
13330 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13331 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
13331 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13332 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
13332 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 13333 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/5, |
13333 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/5, |
| 13334 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
13334 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13335 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
13335 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 13336 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
13336 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 13337 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
13337 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 13338 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
13338 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13339 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
13339 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 13340 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
13340 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 13341 |
// MIs[3] Operand 1 |
13341 |
// MIs[3] Operand 1 |
| 13342 |
// No operand predicates |
13342 |
// No operand predicates |
| 13343 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
13343 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 13344 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
13344 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 13345 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
13345 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 13346 |
// MIs[4] Operand 1 |
13346 |
// MIs[4] Operand 1 |
| 13347 |
// No operand predicates |
13347 |
// No operand predicates |
| 13348 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
13348 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 13349 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
13349 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 13350 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
13350 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 13351 |
// MIs[5] Operand 1 |
13351 |
// MIs[5] Operand 1 |
| 13352 |
// No operand predicates |
13352 |
// No operand predicates |
| 13353 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
13353 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 13354 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
13354 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 13355 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
13355 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 13356 |
// MIs[6] Operand 1 |
13356 |
// MIs[6] Operand 1 |
| 13357 |
// No operand predicates |
13357 |
// No operand predicates |
| 13358 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13358 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13359 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
13359 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13360 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
13360 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13361 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
13361 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13362 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
13362 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 13363 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
13363 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 13364 |
// (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v4i32:{ *:[v4i32] }:$wt)) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt) |
13364 |
// (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v4i32:{ *:[v4i32] }:$wt)) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt) |
| 13365 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_W, |
13365 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_W, |
| 13366 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
13366 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 13367 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
13367 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 13368 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
13368 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 13369 |
GIR_EraseFromParent, /*InsnID*/0, |
13369 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13370 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13370 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13371 |
// GIR_Coverage, 2414, |
13371 |
// GIR_Coverage, 2414, |
| 13372 |
GIR_Done, |
13372 |
GIR_Done, |
| 13373 |
// Label 863: @32683 |
13373 |
// Label 863: @32683 |
| 13374 |
GIM_Try, /*On fail goto*//*Label 864*/ 32800, // Rule ID 2031 // |
13374 |
GIM_Try, /*On fail goto*//*Label 864*/ 32800, // Rule ID 2031 // |
| 13375 |
GIM_CheckFeatures, GIFBS_HasMSA, |
13375 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 13376 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13376 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13377 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
13377 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13378 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
13378 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13379 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
13379 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 13380 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
13380 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13381 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
13381 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 13382 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/5, |
13382 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/5, |
| 13383 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
13383 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13384 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
13384 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 13385 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
13385 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 13386 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
13386 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 13387 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
13387 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13388 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
13388 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 13389 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
13389 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 13390 |
// MIs[3] Operand 1 |
13390 |
// MIs[3] Operand 1 |
| 13391 |
// No operand predicates |
13391 |
// No operand predicates |
| 13392 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
13392 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 13393 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
13393 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 13394 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
13394 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 13395 |
// MIs[4] Operand 1 |
13395 |
// MIs[4] Operand 1 |
| 13396 |
// No operand predicates |
13396 |
// No operand predicates |
| 13397 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
13397 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 13398 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
13398 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 13399 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
13399 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 13400 |
// MIs[5] Operand 1 |
13400 |
// MIs[5] Operand 1 |
| 13401 |
// No operand predicates |
13401 |
// No operand predicates |
| 13402 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
13402 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 13403 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
13403 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 13404 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
13404 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 13405 |
// MIs[6] Operand 1 |
13405 |
// MIs[6] Operand 1 |
| 13406 |
// No operand predicates |
13406 |
// No operand predicates |
| 13407 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13407 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13408 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
13408 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13409 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
13409 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13410 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
13410 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13411 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
13411 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 13412 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
13412 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 13413 |
// (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt) |
13413 |
// (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt) |
| 13414 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_W, |
13414 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_W, |
| 13415 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
13415 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 13416 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
13416 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 13417 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
13417 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
| 13418 |
GIR_EraseFromParent, /*InsnID*/0, |
13418 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13419 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13419 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13420 |
// GIR_Coverage, 2031, |
13420 |
// GIR_Coverage, 2031, |
| 13421 |
GIR_Done, |
13421 |
GIR_Done, |
| 13422 |
// Label 864: @32800 |
13422 |
// Label 864: @32800 |
| 13423 |
GIM_Try, /*On fail goto*//*Label 865*/ 32819, // Rule ID 947 // |
13423 |
GIM_Try, /*On fail goto*//*Label 865*/ 32819, // Rule ID 947 // |
| 13424 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
13424 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 13425 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
13425 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 13426 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
13426 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 13427 |
// (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
13427 |
// (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 13428 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_W, |
13428 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_W, |
| 13429 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13429 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13430 |
// GIR_Coverage, 947, |
13430 |
// GIR_Coverage, 947, |
| 13431 |
GIR_Done, |
13431 |
GIR_Done, |
| 13432 |
// Label 865: @32819 |
13432 |
// Label 865: @32819 |
| 13433 |
GIM_Reject, |
13433 |
GIM_Reject, |
| 13434 |
// Label 862: @32820 |
13434 |
// Label 862: @32820 |
| 13435 |
GIM_Reject, |
13435 |
GIM_Reject, |
| 13436 |
// Label 846: @32821 |
13436 |
// Label 846: @32821 |
| 13437 |
GIM_Try, /*On fail goto*//*Label 866*/ 33217, |
13437 |
GIM_Try, /*On fail goto*//*Label 866*/ 33217, |
| 13438 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
13438 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13439 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
13439 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13440 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
13440 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 13441 |
GIM_Try, /*On fail goto*//*Label 867*/ 33016, // Rule ID 2413 // |
13441 |
GIM_Try, /*On fail goto*//*Label 867*/ 33016, // Rule ID 2413 // |
| 13442 |
GIM_CheckFeatures, GIFBS_HasMSA, |
13442 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 13443 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13443 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13444 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
13444 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13445 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
13445 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13446 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
13446 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13447 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
13447 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13448 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
13448 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 13449 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/9, |
13449 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/9, |
| 13450 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
13450 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13451 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
13451 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 13452 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
13452 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 13453 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
13453 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 13454 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
13454 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
| 13455 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
13455 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
| 13456 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
13456 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
| 13457 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
13457 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
| 13458 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
13458 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13459 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
13459 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 13460 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13460 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13461 |
// MIs[3] Operand 1 |
13461 |
// MIs[3] Operand 1 |
| 13462 |
// No operand predicates |
13462 |
// No operand predicates |
| 13463 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
13463 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 13464 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
13464 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 13465 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13465 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13466 |
// MIs[4] Operand 1 |
13466 |
// MIs[4] Operand 1 |
| 13467 |
// No operand predicates |
13467 |
// No operand predicates |
| 13468 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
13468 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 13469 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
13469 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 13470 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13470 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13471 |
// MIs[5] Operand 1 |
13471 |
// MIs[5] Operand 1 |
| 13472 |
// No operand predicates |
13472 |
// No operand predicates |
| 13473 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
13473 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 13474 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
13474 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 13475 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13475 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13476 |
// MIs[6] Operand 1 |
13476 |
// MIs[6] Operand 1 |
| 13477 |
// No operand predicates |
13477 |
// No operand predicates |
| 13478 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
13478 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
| 13479 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
13479 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
| 13480 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13480 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13481 |
// MIs[7] Operand 1 |
13481 |
// MIs[7] Operand 1 |
| 13482 |
// No operand predicates |
13482 |
// No operand predicates |
| 13483 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
13483 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
| 13484 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
13484 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
| 13485 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13485 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13486 |
// MIs[8] Operand 1 |
13486 |
// MIs[8] Operand 1 |
| 13487 |
// No operand predicates |
13487 |
// No operand predicates |
| 13488 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
13488 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
| 13489 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
13489 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
| 13490 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13490 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13491 |
// MIs[9] Operand 1 |
13491 |
// MIs[9] Operand 1 |
| 13492 |
// No operand predicates |
13492 |
// No operand predicates |
| 13493 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
13493 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
| 13494 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
13494 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
| 13495 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13495 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13496 |
// MIs[10] Operand 1 |
13496 |
// MIs[10] Operand 1 |
| 13497 |
// No operand predicates |
13497 |
// No operand predicates |
| 13498 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13498 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13499 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
13499 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13500 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
13500 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13501 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
13501 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13502 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
13502 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 13503 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
13503 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 13504 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
13504 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
| 13505 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
13505 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
| 13506 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
13506 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
| 13507 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
13507 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
| 13508 |
// (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v8i16:{ *:[v8i16] }:$wt)) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt) |
13508 |
// (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v8i16:{ *:[v8i16] }:$wt)) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt) |
| 13509 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_H, |
13509 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_H, |
| 13510 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
13510 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 13511 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
13511 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 13512 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
13512 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 13513 |
GIR_EraseFromParent, /*InsnID*/0, |
13513 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13514 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13514 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13515 |
// GIR_Coverage, 2413, |
13515 |
// GIR_Coverage, 2413, |
| 13516 |
GIR_Done, |
13516 |
GIR_Done, |
| 13517 |
// Label 867: @33016 |
13517 |
// Label 867: @33016 |
| 13518 |
GIM_Try, /*On fail goto*//*Label 868*/ 33197, // Rule ID 2030 // |
13518 |
GIM_Try, /*On fail goto*//*Label 868*/ 33197, // Rule ID 2030 // |
| 13519 |
GIM_CheckFeatures, GIFBS_HasMSA, |
13519 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 13520 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13520 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13521 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
13521 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13522 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
13522 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13523 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
13523 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 13524 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
13524 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13525 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
13525 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 13526 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/9, |
13526 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/9, |
| 13527 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
13527 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13528 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
13528 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 13529 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
13529 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 13530 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
13530 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 13531 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
13531 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
| 13532 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
13532 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
| 13533 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
13533 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
| 13534 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
13534 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
| 13535 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
13535 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13536 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
13536 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 13537 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13537 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13538 |
// MIs[3] Operand 1 |
13538 |
// MIs[3] Operand 1 |
| 13539 |
// No operand predicates |
13539 |
// No operand predicates |
| 13540 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
13540 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 13541 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
13541 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 13542 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13542 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13543 |
// MIs[4] Operand 1 |
13543 |
// MIs[4] Operand 1 |
| 13544 |
// No operand predicates |
13544 |
// No operand predicates |
| 13545 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
13545 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 13546 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
13546 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 13547 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13547 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13548 |
// MIs[5] Operand 1 |
13548 |
// MIs[5] Operand 1 |
| 13549 |
// No operand predicates |
13549 |
// No operand predicates |
| 13550 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
13550 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 13551 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
13551 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 13552 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13552 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13553 |
// MIs[6] Operand 1 |
13553 |
// MIs[6] Operand 1 |
| 13554 |
// No operand predicates |
13554 |
// No operand predicates |
| 13555 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
13555 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
| 13556 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
13556 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
| 13557 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13557 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13558 |
// MIs[7] Operand 1 |
13558 |
// MIs[7] Operand 1 |
| 13559 |
// No operand predicates |
13559 |
// No operand predicates |
| 13560 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
13560 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
| 13561 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
13561 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
| 13562 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13562 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13563 |
// MIs[8] Operand 1 |
13563 |
// MIs[8] Operand 1 |
| 13564 |
// No operand predicates |
13564 |
// No operand predicates |
| 13565 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
13565 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
| 13566 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
13566 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
| 13567 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13567 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13568 |
// MIs[9] Operand 1 |
13568 |
// MIs[9] Operand 1 |
| 13569 |
// No operand predicates |
13569 |
// No operand predicates |
| 13570 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
13570 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
| 13571 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
13571 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
| 13572 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
13572 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 13573 |
// MIs[10] Operand 1 |
13573 |
// MIs[10] Operand 1 |
| 13574 |
// No operand predicates |
13574 |
// No operand predicates |
| 13575 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13575 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13576 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
13576 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13577 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
13577 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13578 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
13578 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13579 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
13579 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 13580 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
13580 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 13581 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
13581 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
| 13582 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
13582 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
| 13583 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
13583 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
| 13584 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
13584 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
| 13585 |
// (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt) |
13585 |
// (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt) |
| 13586 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_H, |
13586 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_H, |
| 13587 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
13587 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 13588 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
13588 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 13589 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
13589 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
| 13590 |
GIR_EraseFromParent, /*InsnID*/0, |
13590 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13591 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13591 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13592 |
// GIR_Coverage, 2030, |
13592 |
// GIR_Coverage, 2030, |
| 13593 |
GIR_Done, |
13593 |
GIR_Done, |
| 13594 |
// Label 868: @33197 |
13594 |
// Label 868: @33197 |
| 13595 |
GIM_Try, /*On fail goto*//*Label 869*/ 33216, // Rule ID 946 // |
13595 |
GIM_Try, /*On fail goto*//*Label 869*/ 33216, // Rule ID 946 // |
| 13596 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
13596 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 13597 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
13597 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 13598 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
13598 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 13599 |
// (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
13599 |
// (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 13600 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_H, |
13600 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_H, |
| 13601 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13601 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13602 |
// GIR_Coverage, 946, |
13602 |
// GIR_Coverage, 946, |
| 13603 |
GIR_Done, |
13603 |
GIR_Done, |
| 13604 |
// Label 869: @33216 |
13604 |
// Label 869: @33216 |
| 13605 |
GIM_Reject, |
13605 |
GIM_Reject, |
| 13606 |
// Label 866: @33217 |
13606 |
// Label 866: @33217 |
| 13607 |
GIM_Reject, |
13607 |
GIM_Reject, |
| 13608 |
// Label 847: @33218 |
13608 |
// Label 847: @33218 |
| 13609 |
GIM_Try, /*On fail goto*//*Label 870*/ 33870, |
13609 |
GIM_Try, /*On fail goto*//*Label 870*/ 33870, |
| 13610 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
13610 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13611 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
13611 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 13612 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
13612 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 13613 |
GIM_Try, /*On fail goto*//*Label 871*/ 33541, // Rule ID 2412 // |
13613 |
GIM_Try, /*On fail goto*//*Label 871*/ 33541, // Rule ID 2412 // |
| 13614 |
GIM_CheckFeatures, GIFBS_HasMSA, |
13614 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 13615 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13615 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13616 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
13616 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13617 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
13617 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13618 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
13618 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 13619 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
13619 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 13620 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
13620 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 13621 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/17, |
13621 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/17, |
| 13622 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
13622 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13623 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
13623 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 13624 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
13624 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 13625 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
13625 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 13626 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
13626 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
| 13627 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
13627 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
| 13628 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
13628 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
| 13629 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
13629 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
| 13630 |
GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32, |
13630 |
GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32, |
| 13631 |
GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32, |
13631 |
GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32, |
| 13632 |
GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32, |
13632 |
GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32, |
| 13633 |
GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32, |
13633 |
GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32, |
| 13634 |
GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32, |
13634 |
GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32, |
| 13635 |
GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32, |
13635 |
GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32, |
| 13636 |
GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32, |
13636 |
GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32, |
| 13637 |
GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32, |
13637 |
GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32, |
| 13638 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
13638 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13639 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
13639 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 13640 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13640 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13641 |
// MIs[3] Operand 1 |
13641 |
// MIs[3] Operand 1 |
| 13642 |
// No operand predicates |
13642 |
// No operand predicates |
| 13643 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
13643 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 13644 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
13644 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 13645 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13645 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13646 |
// MIs[4] Operand 1 |
13646 |
// MIs[4] Operand 1 |
| 13647 |
// No operand predicates |
13647 |
// No operand predicates |
| 13648 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
13648 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 13649 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
13649 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 13650 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13650 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13651 |
// MIs[5] Operand 1 |
13651 |
// MIs[5] Operand 1 |
| 13652 |
// No operand predicates |
13652 |
// No operand predicates |
| 13653 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
13653 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 13654 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
13654 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 13655 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13655 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13656 |
// MIs[6] Operand 1 |
13656 |
// MIs[6] Operand 1 |
| 13657 |
// No operand predicates |
13657 |
// No operand predicates |
| 13658 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
13658 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
| 13659 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
13659 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
| 13660 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13660 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13661 |
// MIs[7] Operand 1 |
13661 |
// MIs[7] Operand 1 |
| 13662 |
// No operand predicates |
13662 |
// No operand predicates |
| 13663 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
13663 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
| 13664 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
13664 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
| 13665 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13665 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13666 |
// MIs[8] Operand 1 |
13666 |
// MIs[8] Operand 1 |
| 13667 |
// No operand predicates |
13667 |
// No operand predicates |
| 13668 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
13668 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
| 13669 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
13669 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
| 13670 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13670 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13671 |
// MIs[9] Operand 1 |
13671 |
// MIs[9] Operand 1 |
| 13672 |
// No operand predicates |
13672 |
// No operand predicates |
| 13673 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
13673 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
| 13674 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
13674 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
| 13675 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13675 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13676 |
// MIs[10] Operand 1 |
13676 |
// MIs[10] Operand 1 |
| 13677 |
// No operand predicates |
13677 |
// No operand predicates |
| 13678 |
GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11] |
13678 |
GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11] |
| 13679 |
GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT, |
13679 |
GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT, |
| 13680 |
GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13680 |
GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13681 |
// MIs[11] Operand 1 |
13681 |
// MIs[11] Operand 1 |
| 13682 |
// No operand predicates |
13682 |
// No operand predicates |
| 13683 |
GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12] |
13683 |
GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12] |
| 13684 |
GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT, |
13684 |
GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT, |
| 13685 |
GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13685 |
GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13686 |
// MIs[12] Operand 1 |
13686 |
// MIs[12] Operand 1 |
| 13687 |
// No operand predicates |
13687 |
// No operand predicates |
| 13688 |
GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13] |
13688 |
GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13] |
| 13689 |
GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT, |
13689 |
GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT, |
| 13690 |
GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13690 |
GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13691 |
// MIs[13] Operand 1 |
13691 |
// MIs[13] Operand 1 |
| 13692 |
// No operand predicates |
13692 |
// No operand predicates |
| 13693 |
GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14] |
13693 |
GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14] |
| 13694 |
GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT, |
13694 |
GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT, |
| 13695 |
GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13695 |
GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13696 |
// MIs[14] Operand 1 |
13696 |
// MIs[14] Operand 1 |
| 13697 |
// No operand predicates |
13697 |
// No operand predicates |
| 13698 |
GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15] |
13698 |
GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15] |
| 13699 |
GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT, |
13699 |
GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT, |
| 13700 |
GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13700 |
GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13701 |
// MIs[15] Operand 1 |
13701 |
// MIs[15] Operand 1 |
| 13702 |
// No operand predicates |
13702 |
// No operand predicates |
| 13703 |
GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16] |
13703 |
GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16] |
| 13704 |
GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT, |
13704 |
GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT, |
| 13705 |
GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13705 |
GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13706 |
// MIs[16] Operand 1 |
13706 |
// MIs[16] Operand 1 |
| 13707 |
// No operand predicates |
13707 |
// No operand predicates |
| 13708 |
GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17] |
13708 |
GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17] |
| 13709 |
GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT, |
13709 |
GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT, |
| 13710 |
GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13710 |
GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13711 |
// MIs[17] Operand 1 |
13711 |
// MIs[17] Operand 1 |
| 13712 |
// No operand predicates |
13712 |
// No operand predicates |
| 13713 |
GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18] |
13713 |
GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18] |
| 13714 |
GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT, |
13714 |
GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT, |
| 13715 |
GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13715 |
GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13716 |
// MIs[18] Operand 1 |
13716 |
// MIs[18] Operand 1 |
| 13717 |
// No operand predicates |
13717 |
// No operand predicates |
| 13718 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13718 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13719 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
13719 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13720 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
13720 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13721 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
13721 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13722 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
13722 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 13723 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
13723 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 13724 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
13724 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
| 13725 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
13725 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
| 13726 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
13726 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
| 13727 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
13727 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
| 13728 |
GIM_CheckIsSafeToFold, /*InsnID*/11, |
13728 |
GIM_CheckIsSafeToFold, /*InsnID*/11, |
| 13729 |
GIM_CheckIsSafeToFold, /*InsnID*/12, |
13729 |
GIM_CheckIsSafeToFold, /*InsnID*/12, |
| 13730 |
GIM_CheckIsSafeToFold, /*InsnID*/13, |
13730 |
GIM_CheckIsSafeToFold, /*InsnID*/13, |
| 13731 |
GIM_CheckIsSafeToFold, /*InsnID*/14, |
13731 |
GIM_CheckIsSafeToFold, /*InsnID*/14, |
| 13732 |
GIM_CheckIsSafeToFold, /*InsnID*/15, |
13732 |
GIM_CheckIsSafeToFold, /*InsnID*/15, |
| 13733 |
GIM_CheckIsSafeToFold, /*InsnID*/16, |
13733 |
GIM_CheckIsSafeToFold, /*InsnID*/16, |
| 13734 |
GIM_CheckIsSafeToFold, /*InsnID*/17, |
13734 |
GIM_CheckIsSafeToFold, /*InsnID*/17, |
| 13735 |
GIM_CheckIsSafeToFold, /*InsnID*/18, |
13735 |
GIM_CheckIsSafeToFold, /*InsnID*/18, |
| 13736 |
// (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v16i8:{ *:[v16i8] }:$wt)) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt) |
13736 |
// (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v16i8:{ *:[v16i8] }:$wt)) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt) |
| 13737 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_B, |
13737 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_B, |
| 13738 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
13738 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 13739 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
13739 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 13740 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
13740 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 13741 |
GIR_EraseFromParent, /*InsnID*/0, |
13741 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13742 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13742 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13743 |
// GIR_Coverage, 2412, |
13743 |
// GIR_Coverage, 2412, |
| 13744 |
GIR_Done, |
13744 |
GIR_Done, |
| 13745 |
// Label 871: @33541 |
13745 |
// Label 871: @33541 |
| 13746 |
GIM_Try, /*On fail goto*//*Label 872*/ 33850, // Rule ID 2029 // |
13746 |
GIM_Try, /*On fail goto*//*Label 872*/ 33850, // Rule ID 2029 // |
| 13747 |
GIM_CheckFeatures, GIFBS_HasMSA, |
13747 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 13748 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13748 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13749 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
13749 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 13750 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
13750 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 13751 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
13751 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 13752 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
13752 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 13753 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
13753 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 13754 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/17, |
13754 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/17, |
| 13755 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
13755 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 13756 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
13756 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 13757 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
13757 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 13758 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
13758 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 13759 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
13759 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
| 13760 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
13760 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
| 13761 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
13761 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
| 13762 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
13762 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
| 13763 |
GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32, |
13763 |
GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32, |
| 13764 |
GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32, |
13764 |
GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32, |
| 13765 |
GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32, |
13765 |
GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32, |
| 13766 |
GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32, |
13766 |
GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32, |
| 13767 |
GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32, |
13767 |
GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32, |
| 13768 |
GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32, |
13768 |
GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32, |
| 13769 |
GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32, |
13769 |
GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32, |
| 13770 |
GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32, |
13770 |
GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32, |
| 13771 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
13771 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 13772 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
13772 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 13773 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13773 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13774 |
// MIs[3] Operand 1 |
13774 |
// MIs[3] Operand 1 |
| 13775 |
// No operand predicates |
13775 |
// No operand predicates |
| 13776 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
13776 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 13777 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
13777 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 13778 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13778 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13779 |
// MIs[4] Operand 1 |
13779 |
// MIs[4] Operand 1 |
| 13780 |
// No operand predicates |
13780 |
// No operand predicates |
| 13781 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
13781 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 13782 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
13782 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 13783 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13783 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13784 |
// MIs[5] Operand 1 |
13784 |
// MIs[5] Operand 1 |
| 13785 |
// No operand predicates |
13785 |
// No operand predicates |
| 13786 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
13786 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 13787 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
13787 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 13788 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13788 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13789 |
// MIs[6] Operand 1 |
13789 |
// MIs[6] Operand 1 |
| 13790 |
// No operand predicates |
13790 |
// No operand predicates |
| 13791 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
13791 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
| 13792 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
13792 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
| 13793 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13793 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13794 |
// MIs[7] Operand 1 |
13794 |
// MIs[7] Operand 1 |
| 13795 |
// No operand predicates |
13795 |
// No operand predicates |
| 13796 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
13796 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
| 13797 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
13797 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
| 13798 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13798 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13799 |
// MIs[8] Operand 1 |
13799 |
// MIs[8] Operand 1 |
| 13800 |
// No operand predicates |
13800 |
// No operand predicates |
| 13801 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
13801 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
| 13802 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
13802 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
| 13803 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13803 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13804 |
// MIs[9] Operand 1 |
13804 |
// MIs[9] Operand 1 |
| 13805 |
// No operand predicates |
13805 |
// No operand predicates |
| 13806 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
13806 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
| 13807 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
13807 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
| 13808 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13808 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13809 |
// MIs[10] Operand 1 |
13809 |
// MIs[10] Operand 1 |
| 13810 |
// No operand predicates |
13810 |
// No operand predicates |
| 13811 |
GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11] |
13811 |
GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11] |
| 13812 |
GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT, |
13812 |
GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT, |
| 13813 |
GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13813 |
GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13814 |
// MIs[11] Operand 1 |
13814 |
// MIs[11] Operand 1 |
| 13815 |
// No operand predicates |
13815 |
// No operand predicates |
| 13816 |
GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12] |
13816 |
GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12] |
| 13817 |
GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT, |
13817 |
GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT, |
| 13818 |
GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13818 |
GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13819 |
// MIs[12] Operand 1 |
13819 |
// MIs[12] Operand 1 |
| 13820 |
// No operand predicates |
13820 |
// No operand predicates |
| 13821 |
GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13] |
13821 |
GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13] |
| 13822 |
GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT, |
13822 |
GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT, |
| 13823 |
GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13823 |
GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13824 |
// MIs[13] Operand 1 |
13824 |
// MIs[13] Operand 1 |
| 13825 |
// No operand predicates |
13825 |
// No operand predicates |
| 13826 |
GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14] |
13826 |
GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14] |
| 13827 |
GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT, |
13827 |
GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT, |
| 13828 |
GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13828 |
GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13829 |
// MIs[14] Operand 1 |
13829 |
// MIs[14] Operand 1 |
| 13830 |
// No operand predicates |
13830 |
// No operand predicates |
| 13831 |
GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15] |
13831 |
GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15] |
| 13832 |
GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT, |
13832 |
GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT, |
| 13833 |
GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13833 |
GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13834 |
// MIs[15] Operand 1 |
13834 |
// MIs[15] Operand 1 |
| 13835 |
// No operand predicates |
13835 |
// No operand predicates |
| 13836 |
GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16] |
13836 |
GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16] |
| 13837 |
GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT, |
13837 |
GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT, |
| 13838 |
GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13838 |
GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13839 |
// MIs[16] Operand 1 |
13839 |
// MIs[16] Operand 1 |
| 13840 |
// No operand predicates |
13840 |
// No operand predicates |
| 13841 |
GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17] |
13841 |
GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17] |
| 13842 |
GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT, |
13842 |
GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT, |
| 13843 |
GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13843 |
GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13844 |
// MIs[17] Operand 1 |
13844 |
// MIs[17] Operand 1 |
| 13845 |
// No operand predicates |
13845 |
// No operand predicates |
| 13846 |
GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18] |
13846 |
GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18] |
| 13847 |
GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT, |
13847 |
GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT, |
| 13848 |
GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
13848 |
GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 13849 |
// MIs[18] Operand 1 |
13849 |
// MIs[18] Operand 1 |
| 13850 |
// No operand predicates |
13850 |
// No operand predicates |
| 13851 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13851 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13852 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
13852 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 13853 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
13853 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 13854 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
13854 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 13855 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
13855 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 13856 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
13856 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 13857 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
13857 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
| 13858 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
13858 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
| 13859 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
13859 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
| 13860 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
13860 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
| 13861 |
GIM_CheckIsSafeToFold, /*InsnID*/11, |
13861 |
GIM_CheckIsSafeToFold, /*InsnID*/11, |
| 13862 |
GIM_CheckIsSafeToFold, /*InsnID*/12, |
13862 |
GIM_CheckIsSafeToFold, /*InsnID*/12, |
| 13863 |
GIM_CheckIsSafeToFold, /*InsnID*/13, |
13863 |
GIM_CheckIsSafeToFold, /*InsnID*/13, |
| 13864 |
GIM_CheckIsSafeToFold, /*InsnID*/14, |
13864 |
GIM_CheckIsSafeToFold, /*InsnID*/14, |
| 13865 |
GIM_CheckIsSafeToFold, /*InsnID*/15, |
13865 |
GIM_CheckIsSafeToFold, /*InsnID*/15, |
| 13866 |
GIM_CheckIsSafeToFold, /*InsnID*/16, |
13866 |
GIM_CheckIsSafeToFold, /*InsnID*/16, |
| 13867 |
GIM_CheckIsSafeToFold, /*InsnID*/17, |
13867 |
GIM_CheckIsSafeToFold, /*InsnID*/17, |
| 13868 |
GIM_CheckIsSafeToFold, /*InsnID*/18, |
13868 |
GIM_CheckIsSafeToFold, /*InsnID*/18, |
| 13869 |
// (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt) |
13869 |
// (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt) |
| 13870 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_B, |
13870 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_B, |
| 13871 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
13871 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 13872 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
13872 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 13873 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
13873 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
| 13874 |
GIR_EraseFromParent, /*InsnID*/0, |
13874 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13875 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13875 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13876 |
// GIR_Coverage, 2029, |
13876 |
// GIR_Coverage, 2029, |
| 13877 |
GIR_Done, |
13877 |
GIR_Done, |
| 13878 |
// Label 872: @33850 |
13878 |
// Label 872: @33850 |
| 13879 |
GIM_Try, /*On fail goto*//*Label 873*/ 33869, // Rule ID 945 // |
13879 |
GIM_Try, /*On fail goto*//*Label 873*/ 33869, // Rule ID 945 // |
| 13880 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
13880 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 13881 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
13881 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 13882 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
13882 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 13883 |
// (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
13883 |
// (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 13884 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_B, |
13884 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_B, |
| 13885 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13885 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13886 |
// GIR_Coverage, 945, |
13886 |
// GIR_Coverage, 945, |
| 13887 |
GIR_Done, |
13887 |
GIR_Done, |
| 13888 |
// Label 873: @33869 |
13888 |
// Label 873: @33869 |
| 13889 |
GIM_Reject, |
13889 |
GIM_Reject, |
| 13890 |
// Label 870: @33870 |
13890 |
// Label 870: @33870 |
| 13891 |
GIM_Reject, |
13891 |
GIM_Reject, |
| 13892 |
// Label 848: @33871 |
13892 |
// Label 848: @33871 |
| 13893 |
GIM_Reject, |
13893 |
GIM_Reject, |
| 13894 |
// Label 24: @33872 |
13894 |
// Label 24: @33872 |
| 13895 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 880*/ 35624, |
13895 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 880*/ 35624, |
| 13896 |
/*GILLT_s32*//*Label 874*/ 33886, |
13896 |
/*GILLT_s32*//*Label 874*/ 33886, |
| 13897 |
/*GILLT_s64*//*Label 875*/ 34139, 0, |
13897 |
/*GILLT_s64*//*Label 875*/ 34139, 0, |
| 13898 |
/*GILLT_v2s64*//*Label 876*/ 34273, 0, |
13898 |
/*GILLT_v2s64*//*Label 876*/ 34273, 0, |
| 13899 |
/*GILLT_v4s32*//*Label 877*/ 34305, |
13899 |
/*GILLT_v4s32*//*Label 877*/ 34305, |
| 13900 |
/*GILLT_v8s16*//*Label 878*/ 34574, |
13900 |
/*GILLT_v8s16*//*Label 878*/ 34574, |
| 13901 |
/*GILLT_v16s8*//*Label 879*/ 34971, |
13901 |
/*GILLT_v16s8*//*Label 879*/ 34971, |
| 13902 |
// Label 874: @33886 |
13902 |
// Label 874: @33886 |
| 13903 |
GIM_Try, /*On fail goto*//*Label 881*/ 34138, |
13903 |
GIM_Try, /*On fail goto*//*Label 881*/ 34138, |
| 13904 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
13904 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 13905 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
13905 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 13906 |
GIM_Try, /*On fail goto*//*Label 882*/ 33939, // Rule ID 56 // |
13906 |
GIM_Try, /*On fail goto*//*Label 882*/ 33939, // Rule ID 56 // |
| 13907 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
13907 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 13908 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
13908 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 13909 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
13909 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 13910 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13910 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13911 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
13911 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 13912 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
13912 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 13913 |
// MIs[1] Operand 1 |
13913 |
// MIs[1] Operand 1 |
| 13914 |
// No operand predicates |
13914 |
// No operand predicates |
| 13915 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13915 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13916 |
// (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt) |
13916 |
// (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt) |
| 13917 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL, |
13917 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL, |
| 13918 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
13918 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 13919 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
13919 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 13920 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
13920 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 13921 |
GIR_EraseFromParent, /*InsnID*/0, |
13921 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13922 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13922 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13923 |
// GIR_Coverage, 56, |
13923 |
// GIR_Coverage, 56, |
| 13924 |
GIR_Done, |
13924 |
GIR_Done, |
| 13925 |
// Label 882: @33939 |
13925 |
// Label 882: @33939 |
| 13926 |
GIM_Try, /*On fail goto*//*Label 883*/ 33982, // Rule ID 1792 // |
13926 |
GIM_Try, /*On fail goto*//*Label 883*/ 33982, // Rule ID 1792 // |
| 13927 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
13927 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 13928 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
13928 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 13929 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
13929 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 13930 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13930 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13931 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
13931 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 13932 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
13932 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 13933 |
// MIs[1] Operand 1 |
13933 |
// MIs[1] Operand 1 |
| 13934 |
// No operand predicates |
13934 |
// No operand predicates |
| 13935 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13935 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13936 |
// (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<>:$imm) => (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<>:$imm) |
13936 |
// (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<>:$imm) => (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<>:$imm) |
| 13937 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SrlX16, |
13937 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SrlX16, |
| 13938 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx |
13938 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx |
| 13939 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
13939 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
| 13940 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
13940 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 13941 |
GIR_EraseFromParent, /*InsnID*/0, |
13941 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13942 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13942 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13943 |
// GIR_Coverage, 1792, |
13943 |
// GIR_Coverage, 1792, |
| 13944 |
GIR_Done, |
13944 |
GIR_Done, |
| 13945 |
// Label 883: @33982 |
13945 |
// Label 883: @33982 |
| 13946 |
GIM_Try, /*On fail goto*//*Label 884*/ 34025, // Rule ID 2131 // |
13946 |
GIM_Try, /*On fail goto*//*Label 884*/ 34025, // Rule ID 2131 // |
| 13947 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
13947 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 13948 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
13948 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID, |
| 13949 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
13949 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID, |
| 13950 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13950 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13951 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
13951 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 13952 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt2Shift, |
13952 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt2Shift, |
| 13953 |
// MIs[1] Operand 1 |
13953 |
// MIs[1] Operand 1 |
| 13954 |
// No operand predicates |
13954 |
// No operand predicates |
| 13955 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13955 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13956 |
// (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
13956 |
// (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
| 13957 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL16_MM, |
13957 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL16_MM, |
| 13958 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
13958 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 13959 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
13959 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 13960 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
13960 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 13961 |
GIR_EraseFromParent, /*InsnID*/0, |
13961 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13962 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13962 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13963 |
// GIR_Coverage, 2131, |
13963 |
// GIR_Coverage, 2131, |
| 13964 |
GIR_Done, |
13964 |
GIR_Done, |
| 13965 |
// Label 884: @34025 |
13965 |
// Label 884: @34025 |
| 13966 |
GIM_Try, /*On fail goto*//*Label 885*/ 34068, // Rule ID 2132 // |
13966 |
GIM_Try, /*On fail goto*//*Label 885*/ 34068, // Rule ID 2132 // |
| 13967 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
13967 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 13968 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
13968 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 13969 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
13969 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 13970 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
13970 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 13971 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
13971 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 13972 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
13972 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 13973 |
// MIs[1] Operand 1 |
13973 |
// MIs[1] Operand 1 |
| 13974 |
// No operand predicates |
13974 |
// No operand predicates |
| 13975 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
13975 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 13976 |
// (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
13976 |
// (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
| 13977 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_MM, |
13977 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_MM, |
| 13978 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
13978 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 13979 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
13979 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 13980 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
13980 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 13981 |
GIR_EraseFromParent, /*InsnID*/0, |
13981 |
GIR_EraseFromParent, /*InsnID*/0, |
| 13982 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13982 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13983 |
// GIR_Coverage, 2132, |
13983 |
// GIR_Coverage, 2132, |
| 13984 |
GIR_Done, |
13984 |
GIR_Done, |
| 13985 |
// Label 885: @34068 |
13985 |
// Label 885: @34068 |
| 13986 |
GIM_Try, /*On fail goto*//*Label 886*/ 34091, // Rule ID 59 // |
13986 |
GIM_Try, /*On fail goto*//*Label 886*/ 34091, // Rule ID 59 // |
| 13987 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
13987 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 13988 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
13988 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 13989 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
13989 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 13990 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
13990 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 13991 |
// (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
13991 |
// (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 13992 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV, |
13992 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV, |
| 13993 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
13993 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 13994 |
// GIR_Coverage, 59, |
13994 |
// GIR_Coverage, 59, |
| 13995 |
GIR_Done, |
13995 |
GIR_Done, |
| 13996 |
// Label 886: @34091 |
13996 |
// Label 886: @34091 |
| 13997 |
GIM_Try, /*On fail goto*//*Label 887*/ 34114, // Rule ID 1796 // |
13997 |
GIM_Try, /*On fail goto*//*Label 887*/ 34114, // Rule ID 1796 // |
| 13998 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
13998 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 13999 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
13999 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 14000 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
14000 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 14001 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
14001 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 14002 |
// (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) |
14002 |
// (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) |
| 14003 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SrlvRxRy16, |
14003 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SrlvRxRy16, |
| 14004 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14004 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14005 |
// GIR_Coverage, 1796, |
14005 |
// GIR_Coverage, 1796, |
| 14006 |
GIR_Done, |
14006 |
GIR_Done, |
| 14007 |
// Label 887: @34114 |
14007 |
// Label 887: @34114 |
| 14008 |
GIM_Try, /*On fail goto*//*Label 888*/ 34137, // Rule ID 2133 // |
14008 |
GIM_Try, /*On fail goto*//*Label 888*/ 34137, // Rule ID 2133 // |
| 14009 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
14009 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 14010 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
14010 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 14011 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
14011 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 14012 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
14012 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 14013 |
// (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) |
14013 |
// (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) |
| 14014 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV_MM, |
14014 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV_MM, |
| 14015 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14015 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14016 |
// GIR_Coverage, 2133, |
14016 |
// GIR_Coverage, 2133, |
| 14017 |
GIR_Done, |
14017 |
GIR_Done, |
| 14018 |
// Label 888: @34137 |
14018 |
// Label 888: @34137 |
| 14019 |
GIM_Reject, |
14019 |
GIM_Reject, |
| 14020 |
// Label 881: @34138 |
14020 |
// Label 881: @34138 |
| 14021 |
GIM_Reject, |
14021 |
GIM_Reject, |
| 14022 |
// Label 875: @34139 |
14022 |
// Label 875: @34139 |
| 14023 |
GIM_Try, /*On fail goto*//*Label 889*/ 34272, |
14023 |
GIM_Try, /*On fail goto*//*Label 889*/ 34272, |
| 14024 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
14024 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 14025 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
14025 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 14026 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
14026 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 14027 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
14027 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 14028 |
GIM_Try, /*On fail goto*//*Label 890*/ 34192, // Rule ID 205 // |
14028 |
GIM_Try, /*On fail goto*//*Label 890*/ 34192, // Rule ID 205 // |
| 14029 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
14029 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
| 14030 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14030 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14031 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
14031 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 14032 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt6, |
14032 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt6, |
| 14033 |
// MIs[1] Operand 1 |
14033 |
// MIs[1] Operand 1 |
| 14034 |
// No operand predicates |
14034 |
// No operand predicates |
| 14035 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14035 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14036 |
// (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt) |
14036 |
// (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt) |
| 14037 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL, |
14037 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL, |
| 14038 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
14038 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 14039 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
14039 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 14040 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
14040 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 14041 |
GIR_EraseFromParent, /*InsnID*/0, |
14041 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14042 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14042 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14043 |
// GIR_Coverage, 205, |
14043 |
// GIR_Coverage, 205, |
| 14044 |
GIR_Done, |
14044 |
GIR_Done, |
| 14045 |
// Label 890: @34192 |
14045 |
// Label 890: @34192 |
| 14046 |
GIM_Try, /*On fail goto*//*Label 891*/ 34256, // Rule ID 1563 // |
14046 |
GIM_Try, /*On fail goto*//*Label 891*/ 34256, // Rule ID 1563 // |
| 14047 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
14047 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
| 14048 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14048 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14049 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
14049 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 14050 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
14050 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 14051 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
14051 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 14052 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14052 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14053 |
// (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] })) |
14053 |
// (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] })) |
| 14054 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
14054 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 14055 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
14055 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 14056 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
14056 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 14057 |
GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs |
14057 |
GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs |
| 14058 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::GPR32RegClassID, |
14058 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::GPR32RegClassID, |
| 14059 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID, |
14059 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID, |
| 14060 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRLV, |
14060 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRLV, |
| 14061 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
14061 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 14062 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
14062 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 14063 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
14063 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 14064 |
GIR_EraseFromParent, /*InsnID*/0, |
14064 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14065 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14065 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14066 |
// GIR_Coverage, 1563, |
14066 |
// GIR_Coverage, 1563, |
| 14067 |
GIR_Done, |
14067 |
GIR_Done, |
| 14068 |
// Label 891: @34256 |
14068 |
// Label 891: @34256 |
| 14069 |
GIM_Try, /*On fail goto*//*Label 892*/ 34271, // Rule ID 209 // |
14069 |
GIM_Try, /*On fail goto*//*Label 892*/ 34271, // Rule ID 209 // |
| 14070 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
14070 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
| 14071 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
14071 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 14072 |
// (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
14072 |
// (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 14073 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRLV, |
14073 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRLV, |
| 14074 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14074 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14075 |
// GIR_Coverage, 209, |
14075 |
// GIR_Coverage, 209, |
| 14076 |
GIR_Done, |
14076 |
GIR_Done, |
| 14077 |
// Label 892: @34271 |
14077 |
// Label 892: @34271 |
| 14078 |
GIM_Reject, |
14078 |
GIM_Reject, |
| 14079 |
// Label 889: @34272 |
14079 |
// Label 889: @34272 |
| 14080 |
GIM_Reject, |
14080 |
GIM_Reject, |
| 14081 |
// Label 876: @34273 |
14081 |
// Label 876: @34273 |
| 14082 |
GIM_Try, /*On fail goto*//*Label 893*/ 34304, // Rule ID 980 // |
14082 |
GIM_Try, /*On fail goto*//*Label 893*/ 34304, // Rule ID 980 // |
| 14083 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
14083 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 14084 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
14084 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14085 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
14085 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 14086 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
14086 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 14087 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
14087 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 14088 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
14088 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 14089 |
// (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
14089 |
// (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 14090 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_D, |
14090 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_D, |
| 14091 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14091 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14092 |
// GIR_Coverage, 980, |
14092 |
// GIR_Coverage, 980, |
| 14093 |
GIR_Done, |
14093 |
GIR_Done, |
| 14094 |
// Label 893: @34304 |
14094 |
// Label 893: @34304 |
| 14095 |
GIM_Reject, |
14095 |
GIM_Reject, |
| 14096 |
// Label 877: @34305 |
14096 |
// Label 877: @34305 |
| 14097 |
GIM_Try, /*On fail goto*//*Label 894*/ 34573, |
14097 |
GIM_Try, /*On fail goto*//*Label 894*/ 34573, |
| 14098 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
14098 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14099 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
14099 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14100 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
14100 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 14101 |
GIM_Try, /*On fail goto*//*Label 895*/ 34436, // Rule ID 2430 // |
14101 |
GIM_Try, /*On fail goto*//*Label 895*/ 34436, // Rule ID 2430 // |
| 14102 |
GIM_CheckFeatures, GIFBS_HasMSA, |
14102 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 14103 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14103 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14104 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
14104 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14105 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
14105 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14106 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
14106 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14107 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
14107 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14108 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
14108 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 14109 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/5, |
14109 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/5, |
| 14110 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
14110 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14111 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
14111 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 14112 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
14112 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 14113 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
14113 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 14114 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
14114 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14115 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
14115 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 14116 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14116 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14117 |
// MIs[3] Operand 1 |
14117 |
// MIs[3] Operand 1 |
| 14118 |
// No operand predicates |
14118 |
// No operand predicates |
| 14119 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
14119 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 14120 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
14120 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 14121 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14121 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14122 |
// MIs[4] Operand 1 |
14122 |
// MIs[4] Operand 1 |
| 14123 |
// No operand predicates |
14123 |
// No operand predicates |
| 14124 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
14124 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 14125 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
14125 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 14126 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14126 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14127 |
// MIs[5] Operand 1 |
14127 |
// MIs[5] Operand 1 |
| 14128 |
// No operand predicates |
14128 |
// No operand predicates |
| 14129 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
14129 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 14130 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
14130 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 14131 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14131 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14132 |
// MIs[6] Operand 1 |
14132 |
// MIs[6] Operand 1 |
| 14133 |
// No operand predicates |
14133 |
// No operand predicates |
| 14134 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14134 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14135 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
14135 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14136 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
14136 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14137 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
14137 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14138 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
14138 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 14139 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
14139 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 14140 |
// (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v4i32:{ *:[v4i32] }:$wt)) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt) |
14140 |
// (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v4i32:{ *:[v4i32] }:$wt)) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt) |
| 14141 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_W, |
14141 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_W, |
| 14142 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
14142 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 14143 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
14143 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 14144 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
14144 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 14145 |
GIR_EraseFromParent, /*InsnID*/0, |
14145 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14146 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14146 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14147 |
// GIR_Coverage, 2430, |
14147 |
// GIR_Coverage, 2430, |
| 14148 |
GIR_Done, |
14148 |
GIR_Done, |
| 14149 |
// Label 895: @34436 |
14149 |
// Label 895: @34436 |
| 14150 |
GIM_Try, /*On fail goto*//*Label 896*/ 34553, // Rule ID 2039 // |
14150 |
GIM_Try, /*On fail goto*//*Label 896*/ 34553, // Rule ID 2039 // |
| 14151 |
GIM_CheckFeatures, GIFBS_HasMSA, |
14151 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 14152 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14152 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14153 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
14153 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14154 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
14154 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14155 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
14155 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14156 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
14156 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14157 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
14157 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 14158 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/5, |
14158 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/5, |
| 14159 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
14159 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14160 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
14160 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 14161 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
14161 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 14162 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
14162 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 14163 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
14163 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14164 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
14164 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 14165 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14165 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14166 |
// MIs[3] Operand 1 |
14166 |
// MIs[3] Operand 1 |
| 14167 |
// No operand predicates |
14167 |
// No operand predicates |
| 14168 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
14168 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 14169 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
14169 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 14170 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14170 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14171 |
// MIs[4] Operand 1 |
14171 |
// MIs[4] Operand 1 |
| 14172 |
// No operand predicates |
14172 |
// No operand predicates |
| 14173 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
14173 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 14174 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
14174 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 14175 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14175 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14176 |
// MIs[5] Operand 1 |
14176 |
// MIs[5] Operand 1 |
| 14177 |
// No operand predicates |
14177 |
// No operand predicates |
| 14178 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
14178 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 14179 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
14179 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 14180 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14180 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14181 |
// MIs[6] Operand 1 |
14181 |
// MIs[6] Operand 1 |
| 14182 |
// No operand predicates |
14182 |
// No operand predicates |
| 14183 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14183 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14184 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
14184 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14185 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
14185 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14186 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
14186 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14187 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
14187 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 14188 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
14188 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 14189 |
// (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt) |
14189 |
// (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt) |
| 14190 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_W, |
14190 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_W, |
| 14191 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
14191 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 14192 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
14192 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 14193 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
14193 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
| 14194 |
GIR_EraseFromParent, /*InsnID*/0, |
14194 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14195 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14195 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14196 |
// GIR_Coverage, 2039, |
14196 |
// GIR_Coverage, 2039, |
| 14197 |
GIR_Done, |
14197 |
GIR_Done, |
| 14198 |
// Label 896: @34553 |
14198 |
// Label 896: @34553 |
| 14199 |
GIM_Try, /*On fail goto*//*Label 897*/ 34572, // Rule ID 979 // |
14199 |
GIM_Try, /*On fail goto*//*Label 897*/ 34572, // Rule ID 979 // |
| 14200 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
14200 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 14201 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
14201 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 14202 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
14202 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 14203 |
// (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
14203 |
// (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 14204 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_W, |
14204 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_W, |
| 14205 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14205 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14206 |
// GIR_Coverage, 979, |
14206 |
// GIR_Coverage, 979, |
| 14207 |
GIR_Done, |
14207 |
GIR_Done, |
| 14208 |
// Label 897: @34572 |
14208 |
// Label 897: @34572 |
| 14209 |
GIM_Reject, |
14209 |
GIM_Reject, |
| 14210 |
// Label 894: @34573 |
14210 |
// Label 894: @34573 |
| 14211 |
GIM_Reject, |
14211 |
GIM_Reject, |
| 14212 |
// Label 878: @34574 |
14212 |
// Label 878: @34574 |
| 14213 |
GIM_Try, /*On fail goto*//*Label 898*/ 34970, |
14213 |
GIM_Try, /*On fail goto*//*Label 898*/ 34970, |
| 14214 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
14214 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14215 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
14215 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14216 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
14216 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 14217 |
GIM_Try, /*On fail goto*//*Label 899*/ 34769, // Rule ID 2429 // |
14217 |
GIM_Try, /*On fail goto*//*Label 899*/ 34769, // Rule ID 2429 // |
| 14218 |
GIM_CheckFeatures, GIFBS_HasMSA, |
14218 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 14219 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14219 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14220 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
14220 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14221 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
14221 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14222 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
14222 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14223 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
14223 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14224 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
14224 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 14225 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/9, |
14225 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/9, |
| 14226 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
14226 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14227 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
14227 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 14228 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
14228 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 14229 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
14229 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 14230 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
14230 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
| 14231 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
14231 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
| 14232 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
14232 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
| 14233 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
14233 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
| 14234 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
14234 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14235 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
14235 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 14236 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14236 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14237 |
// MIs[3] Operand 1 |
14237 |
// MIs[3] Operand 1 |
| 14238 |
// No operand predicates |
14238 |
// No operand predicates |
| 14239 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
14239 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 14240 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
14240 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 14241 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14241 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14242 |
// MIs[4] Operand 1 |
14242 |
// MIs[4] Operand 1 |
| 14243 |
// No operand predicates |
14243 |
// No operand predicates |
| 14244 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
14244 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 14245 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
14245 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 14246 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14246 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14247 |
// MIs[5] Operand 1 |
14247 |
// MIs[5] Operand 1 |
| 14248 |
// No operand predicates |
14248 |
// No operand predicates |
| 14249 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
14249 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 14250 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
14250 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 14251 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14251 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14252 |
// MIs[6] Operand 1 |
14252 |
// MIs[6] Operand 1 |
| 14253 |
// No operand predicates |
14253 |
// No operand predicates |
| 14254 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
14254 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
| 14255 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
14255 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
| 14256 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14256 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14257 |
// MIs[7] Operand 1 |
14257 |
// MIs[7] Operand 1 |
| 14258 |
// No operand predicates |
14258 |
// No operand predicates |
| 14259 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
14259 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
| 14260 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
14260 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
| 14261 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14261 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14262 |
// MIs[8] Operand 1 |
14262 |
// MIs[8] Operand 1 |
| 14263 |
// No operand predicates |
14263 |
// No operand predicates |
| 14264 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
14264 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
| 14265 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
14265 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
| 14266 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14266 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14267 |
// MIs[9] Operand 1 |
14267 |
// MIs[9] Operand 1 |
| 14268 |
// No operand predicates |
14268 |
// No operand predicates |
| 14269 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
14269 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
| 14270 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
14270 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
| 14271 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14271 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14272 |
// MIs[10] Operand 1 |
14272 |
// MIs[10] Operand 1 |
| 14273 |
// No operand predicates |
14273 |
// No operand predicates |
| 14274 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14274 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14275 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
14275 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14276 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
14276 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14277 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
14277 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14278 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
14278 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 14279 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
14279 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 14280 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
14280 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
| 14281 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
14281 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
| 14282 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
14282 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
| 14283 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
14283 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
| 14284 |
// (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v8i16:{ *:[v8i16] }:$wt)) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt) |
14284 |
// (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v8i16:{ *:[v8i16] }:$wt)) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt) |
| 14285 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_H, |
14285 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_H, |
| 14286 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
14286 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 14287 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
14287 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 14288 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
14288 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 14289 |
GIR_EraseFromParent, /*InsnID*/0, |
14289 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14290 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14290 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14291 |
// GIR_Coverage, 2429, |
14291 |
// GIR_Coverage, 2429, |
| 14292 |
GIR_Done, |
14292 |
GIR_Done, |
| 14293 |
// Label 899: @34769 |
14293 |
// Label 899: @34769 |
| 14294 |
GIM_Try, /*On fail goto*//*Label 900*/ 34950, // Rule ID 2038 // |
14294 |
GIM_Try, /*On fail goto*//*Label 900*/ 34950, // Rule ID 2038 // |
| 14295 |
GIM_CheckFeatures, GIFBS_HasMSA, |
14295 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 14296 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14296 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14297 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
14297 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14298 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
14298 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14299 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
14299 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14300 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
14300 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14301 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
14301 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 14302 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/9, |
14302 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/9, |
| 14303 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
14303 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14304 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
14304 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 14305 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
14305 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 14306 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
14306 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 14307 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
14307 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
| 14308 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
14308 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
| 14309 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
14309 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
| 14310 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
14310 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
| 14311 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
14311 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14312 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
14312 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 14313 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14313 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14314 |
// MIs[3] Operand 1 |
14314 |
// MIs[3] Operand 1 |
| 14315 |
// No operand predicates |
14315 |
// No operand predicates |
| 14316 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
14316 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 14317 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
14317 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 14318 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14318 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14319 |
// MIs[4] Operand 1 |
14319 |
// MIs[4] Operand 1 |
| 14320 |
// No operand predicates |
14320 |
// No operand predicates |
| 14321 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
14321 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 14322 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
14322 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 14323 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14323 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14324 |
// MIs[5] Operand 1 |
14324 |
// MIs[5] Operand 1 |
| 14325 |
// No operand predicates |
14325 |
// No operand predicates |
| 14326 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
14326 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 14327 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
14327 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 14328 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14328 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14329 |
// MIs[6] Operand 1 |
14329 |
// MIs[6] Operand 1 |
| 14330 |
// No operand predicates |
14330 |
// No operand predicates |
| 14331 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
14331 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
| 14332 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
14332 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
| 14333 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14333 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14334 |
// MIs[7] Operand 1 |
14334 |
// MIs[7] Operand 1 |
| 14335 |
// No operand predicates |
14335 |
// No operand predicates |
| 14336 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
14336 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
| 14337 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
14337 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
| 14338 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14338 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14339 |
// MIs[8] Operand 1 |
14339 |
// MIs[8] Operand 1 |
| 14340 |
// No operand predicates |
14340 |
// No operand predicates |
| 14341 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
14341 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
| 14342 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
14342 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
| 14343 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14343 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14344 |
// MIs[9] Operand 1 |
14344 |
// MIs[9] Operand 1 |
| 14345 |
// No operand predicates |
14345 |
// No operand predicates |
| 14346 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
14346 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
| 14347 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
14347 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
| 14348 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14348 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14349 |
// MIs[10] Operand 1 |
14349 |
// MIs[10] Operand 1 |
| 14350 |
// No operand predicates |
14350 |
// No operand predicates |
| 14351 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14351 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14352 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
14352 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14353 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
14353 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14354 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
14354 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14355 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
14355 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 14356 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
14356 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 14357 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
14357 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
| 14358 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
14358 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
| 14359 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
14359 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
| 14360 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
14360 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
| 14361 |
// (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt) |
14361 |
// (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt) |
| 14362 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_H, |
14362 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_H, |
| 14363 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
14363 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 14364 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
14364 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 14365 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
14365 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
| 14366 |
GIR_EraseFromParent, /*InsnID*/0, |
14366 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14367 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14367 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14368 |
// GIR_Coverage, 2038, |
14368 |
// GIR_Coverage, 2038, |
| 14369 |
GIR_Done, |
14369 |
GIR_Done, |
| 14370 |
// Label 900: @34950 |
14370 |
// Label 900: @34950 |
| 14371 |
GIM_Try, /*On fail goto*//*Label 901*/ 34969, // Rule ID 978 // |
14371 |
GIM_Try, /*On fail goto*//*Label 901*/ 34969, // Rule ID 978 // |
| 14372 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
14372 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 14373 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
14373 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 14374 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
14374 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 14375 |
// (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
14375 |
// (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 14376 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_H, |
14376 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_H, |
| 14377 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14377 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14378 |
// GIR_Coverage, 978, |
14378 |
// GIR_Coverage, 978, |
| 14379 |
GIR_Done, |
14379 |
GIR_Done, |
| 14380 |
// Label 901: @34969 |
14380 |
// Label 901: @34969 |
| 14381 |
GIM_Reject, |
14381 |
GIM_Reject, |
| 14382 |
// Label 898: @34970 |
14382 |
// Label 898: @34970 |
| 14383 |
GIM_Reject, |
14383 |
GIM_Reject, |
| 14384 |
// Label 879: @34971 |
14384 |
// Label 879: @34971 |
| 14385 |
GIM_Try, /*On fail goto*//*Label 902*/ 35623, |
14385 |
GIM_Try, /*On fail goto*//*Label 902*/ 35623, |
| 14386 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
14386 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14387 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
14387 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14388 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
14388 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 14389 |
GIM_Try, /*On fail goto*//*Label 903*/ 35294, // Rule ID 2428 // |
14389 |
GIM_Try, /*On fail goto*//*Label 903*/ 35294, // Rule ID 2428 // |
| 14390 |
GIM_CheckFeatures, GIFBS_HasMSA, |
14390 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 14391 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14391 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14392 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
14392 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14393 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
14393 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14394 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
14394 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14395 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
14395 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14396 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
14396 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 14397 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/17, |
14397 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/17, |
| 14398 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
14398 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14399 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
14399 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 14400 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
14400 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 14401 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
14401 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 14402 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
14402 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
| 14403 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
14403 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
| 14404 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
14404 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
| 14405 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
14405 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
| 14406 |
GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32, |
14406 |
GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32, |
| 14407 |
GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32, |
14407 |
GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32, |
| 14408 |
GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32, |
14408 |
GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32, |
| 14409 |
GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32, |
14409 |
GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32, |
| 14410 |
GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32, |
14410 |
GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32, |
| 14411 |
GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32, |
14411 |
GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32, |
| 14412 |
GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32, |
14412 |
GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32, |
| 14413 |
GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32, |
14413 |
GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32, |
| 14414 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
14414 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14415 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
14415 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 14416 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14416 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14417 |
// MIs[3] Operand 1 |
14417 |
// MIs[3] Operand 1 |
| 14418 |
// No operand predicates |
14418 |
// No operand predicates |
| 14419 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
14419 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 14420 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
14420 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 14421 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14421 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14422 |
// MIs[4] Operand 1 |
14422 |
// MIs[4] Operand 1 |
| 14423 |
// No operand predicates |
14423 |
// No operand predicates |
| 14424 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
14424 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 14425 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
14425 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 14426 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14426 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14427 |
// MIs[5] Operand 1 |
14427 |
// MIs[5] Operand 1 |
| 14428 |
// No operand predicates |
14428 |
// No operand predicates |
| 14429 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
14429 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 14430 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
14430 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 14431 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14431 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14432 |
// MIs[6] Operand 1 |
14432 |
// MIs[6] Operand 1 |
| 14433 |
// No operand predicates |
14433 |
// No operand predicates |
| 14434 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
14434 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
| 14435 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
14435 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
| 14436 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14436 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14437 |
// MIs[7] Operand 1 |
14437 |
// MIs[7] Operand 1 |
| 14438 |
// No operand predicates |
14438 |
// No operand predicates |
| 14439 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
14439 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
| 14440 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
14440 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
| 14441 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14441 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14442 |
// MIs[8] Operand 1 |
14442 |
// MIs[8] Operand 1 |
| 14443 |
// No operand predicates |
14443 |
// No operand predicates |
| 14444 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
14444 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
| 14445 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
14445 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
| 14446 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14446 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14447 |
// MIs[9] Operand 1 |
14447 |
// MIs[9] Operand 1 |
| 14448 |
// No operand predicates |
14448 |
// No operand predicates |
| 14449 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
14449 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
| 14450 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
14450 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
| 14451 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14451 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14452 |
// MIs[10] Operand 1 |
14452 |
// MIs[10] Operand 1 |
| 14453 |
// No operand predicates |
14453 |
// No operand predicates |
| 14454 |
GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11] |
14454 |
GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11] |
| 14455 |
GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT, |
14455 |
GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT, |
| 14456 |
GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14456 |
GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14457 |
// MIs[11] Operand 1 |
14457 |
// MIs[11] Operand 1 |
| 14458 |
// No operand predicates |
14458 |
// No operand predicates |
| 14459 |
GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12] |
14459 |
GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12] |
| 14460 |
GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT, |
14460 |
GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT, |
| 14461 |
GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14461 |
GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14462 |
// MIs[12] Operand 1 |
14462 |
// MIs[12] Operand 1 |
| 14463 |
// No operand predicates |
14463 |
// No operand predicates |
| 14464 |
GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13] |
14464 |
GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13] |
| 14465 |
GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT, |
14465 |
GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT, |
| 14466 |
GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14466 |
GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14467 |
// MIs[13] Operand 1 |
14467 |
// MIs[13] Operand 1 |
| 14468 |
// No operand predicates |
14468 |
// No operand predicates |
| 14469 |
GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14] |
14469 |
GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14] |
| 14470 |
GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT, |
14470 |
GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT, |
| 14471 |
GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14471 |
GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14472 |
// MIs[14] Operand 1 |
14472 |
// MIs[14] Operand 1 |
| 14473 |
// No operand predicates |
14473 |
// No operand predicates |
| 14474 |
GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15] |
14474 |
GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15] |
| 14475 |
GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT, |
14475 |
GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT, |
| 14476 |
GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14476 |
GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14477 |
// MIs[15] Operand 1 |
14477 |
// MIs[15] Operand 1 |
| 14478 |
// No operand predicates |
14478 |
// No operand predicates |
| 14479 |
GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16] |
14479 |
GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16] |
| 14480 |
GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT, |
14480 |
GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT, |
| 14481 |
GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14481 |
GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14482 |
// MIs[16] Operand 1 |
14482 |
// MIs[16] Operand 1 |
| 14483 |
// No operand predicates |
14483 |
// No operand predicates |
| 14484 |
GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17] |
14484 |
GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17] |
| 14485 |
GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT, |
14485 |
GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT, |
| 14486 |
GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14486 |
GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14487 |
// MIs[17] Operand 1 |
14487 |
// MIs[17] Operand 1 |
| 14488 |
// No operand predicates |
14488 |
// No operand predicates |
| 14489 |
GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18] |
14489 |
GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18] |
| 14490 |
GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT, |
14490 |
GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT, |
| 14491 |
GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14491 |
GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14492 |
// MIs[18] Operand 1 |
14492 |
// MIs[18] Operand 1 |
| 14493 |
// No operand predicates |
14493 |
// No operand predicates |
| 14494 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14494 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14495 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
14495 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14496 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
14496 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14497 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
14497 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14498 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
14498 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 14499 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
14499 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 14500 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
14500 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
| 14501 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
14501 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
| 14502 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
14502 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
| 14503 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
14503 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
| 14504 |
GIM_CheckIsSafeToFold, /*InsnID*/11, |
14504 |
GIM_CheckIsSafeToFold, /*InsnID*/11, |
| 14505 |
GIM_CheckIsSafeToFold, /*InsnID*/12, |
14505 |
GIM_CheckIsSafeToFold, /*InsnID*/12, |
| 14506 |
GIM_CheckIsSafeToFold, /*InsnID*/13, |
14506 |
GIM_CheckIsSafeToFold, /*InsnID*/13, |
| 14507 |
GIM_CheckIsSafeToFold, /*InsnID*/14, |
14507 |
GIM_CheckIsSafeToFold, /*InsnID*/14, |
| 14508 |
GIM_CheckIsSafeToFold, /*InsnID*/15, |
14508 |
GIM_CheckIsSafeToFold, /*InsnID*/15, |
| 14509 |
GIM_CheckIsSafeToFold, /*InsnID*/16, |
14509 |
GIM_CheckIsSafeToFold, /*InsnID*/16, |
| 14510 |
GIM_CheckIsSafeToFold, /*InsnID*/17, |
14510 |
GIM_CheckIsSafeToFold, /*InsnID*/17, |
| 14511 |
GIM_CheckIsSafeToFold, /*InsnID*/18, |
14511 |
GIM_CheckIsSafeToFold, /*InsnID*/18, |
| 14512 |
// (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v16i8:{ *:[v16i8] }:$wt)) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt) |
14512 |
// (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v16i8:{ *:[v16i8] }:$wt)) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt) |
| 14513 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_B, |
14513 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_B, |
| 14514 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
14514 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 14515 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
14515 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 14516 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
14516 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 14517 |
GIR_EraseFromParent, /*InsnID*/0, |
14517 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14518 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14518 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14519 |
// GIR_Coverage, 2428, |
14519 |
// GIR_Coverage, 2428, |
| 14520 |
GIR_Done, |
14520 |
GIR_Done, |
| 14521 |
// Label 903: @35294 |
14521 |
// Label 903: @35294 |
| 14522 |
GIM_Try, /*On fail goto*//*Label 904*/ 35603, // Rule ID 2037 // |
14522 |
GIM_Try, /*On fail goto*//*Label 904*/ 35603, // Rule ID 2037 // |
| 14523 |
GIM_CheckFeatures, GIFBS_HasMSA, |
14523 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 14524 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14524 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14525 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
14525 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14526 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
14526 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 14527 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
14527 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14528 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
14528 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14529 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
14529 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 14530 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/17, |
14530 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/17, |
| 14531 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
14531 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14532 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
14532 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 14533 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
14533 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 14534 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
14534 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 14535 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
14535 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
| 14536 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
14536 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
| 14537 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
14537 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
| 14538 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
14538 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
| 14539 |
GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32, |
14539 |
GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32, |
| 14540 |
GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32, |
14540 |
GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32, |
| 14541 |
GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32, |
14541 |
GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32, |
| 14542 |
GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32, |
14542 |
GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32, |
| 14543 |
GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32, |
14543 |
GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32, |
| 14544 |
GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32, |
14544 |
GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32, |
| 14545 |
GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32, |
14545 |
GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32, |
| 14546 |
GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32, |
14546 |
GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32, |
| 14547 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
14547 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14548 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
14548 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 14549 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14549 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14550 |
// MIs[3] Operand 1 |
14550 |
// MIs[3] Operand 1 |
| 14551 |
// No operand predicates |
14551 |
// No operand predicates |
| 14552 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
14552 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 14553 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
14553 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 14554 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14554 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14555 |
// MIs[4] Operand 1 |
14555 |
// MIs[4] Operand 1 |
| 14556 |
// No operand predicates |
14556 |
// No operand predicates |
| 14557 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
14557 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 14558 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
14558 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 14559 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14559 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14560 |
// MIs[5] Operand 1 |
14560 |
// MIs[5] Operand 1 |
| 14561 |
// No operand predicates |
14561 |
// No operand predicates |
| 14562 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
14562 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 14563 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
14563 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 14564 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14564 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14565 |
// MIs[6] Operand 1 |
14565 |
// MIs[6] Operand 1 |
| 14566 |
// No operand predicates |
14566 |
// No operand predicates |
| 14567 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
14567 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
| 14568 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
14568 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
| 14569 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14569 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14570 |
// MIs[7] Operand 1 |
14570 |
// MIs[7] Operand 1 |
| 14571 |
// No operand predicates |
14571 |
// No operand predicates |
| 14572 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
14572 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
| 14573 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
14573 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
| 14574 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14574 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14575 |
// MIs[8] Operand 1 |
14575 |
// MIs[8] Operand 1 |
| 14576 |
// No operand predicates |
14576 |
// No operand predicates |
| 14577 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
14577 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
| 14578 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
14578 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
| 14579 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14579 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14580 |
// MIs[9] Operand 1 |
14580 |
// MIs[9] Operand 1 |
| 14581 |
// No operand predicates |
14581 |
// No operand predicates |
| 14582 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
14582 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
| 14583 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
14583 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
| 14584 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14584 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14585 |
// MIs[10] Operand 1 |
14585 |
// MIs[10] Operand 1 |
| 14586 |
// No operand predicates |
14586 |
// No operand predicates |
| 14587 |
GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11] |
14587 |
GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11] |
| 14588 |
GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT, |
14588 |
GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT, |
| 14589 |
GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14589 |
GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14590 |
// MIs[11] Operand 1 |
14590 |
// MIs[11] Operand 1 |
| 14591 |
// No operand predicates |
14591 |
// No operand predicates |
| 14592 |
GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12] |
14592 |
GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12] |
| 14593 |
GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT, |
14593 |
GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT, |
| 14594 |
GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14594 |
GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14595 |
// MIs[12] Operand 1 |
14595 |
// MIs[12] Operand 1 |
| 14596 |
// No operand predicates |
14596 |
// No operand predicates |
| 14597 |
GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13] |
14597 |
GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13] |
| 14598 |
GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT, |
14598 |
GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT, |
| 14599 |
GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14599 |
GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14600 |
// MIs[13] Operand 1 |
14600 |
// MIs[13] Operand 1 |
| 14601 |
// No operand predicates |
14601 |
// No operand predicates |
| 14602 |
GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14] |
14602 |
GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14] |
| 14603 |
GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT, |
14603 |
GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT, |
| 14604 |
GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14604 |
GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14605 |
// MIs[14] Operand 1 |
14605 |
// MIs[14] Operand 1 |
| 14606 |
// No operand predicates |
14606 |
// No operand predicates |
| 14607 |
GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15] |
14607 |
GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15] |
| 14608 |
GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT, |
14608 |
GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT, |
| 14609 |
GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14609 |
GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14610 |
// MIs[15] Operand 1 |
14610 |
// MIs[15] Operand 1 |
| 14611 |
// No operand predicates |
14611 |
// No operand predicates |
| 14612 |
GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16] |
14612 |
GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16] |
| 14613 |
GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT, |
14613 |
GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT, |
| 14614 |
GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14614 |
GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14615 |
// MIs[16] Operand 1 |
14615 |
// MIs[16] Operand 1 |
| 14616 |
// No operand predicates |
14616 |
// No operand predicates |
| 14617 |
GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17] |
14617 |
GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17] |
| 14618 |
GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT, |
14618 |
GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT, |
| 14619 |
GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14619 |
GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14620 |
// MIs[17] Operand 1 |
14620 |
// MIs[17] Operand 1 |
| 14621 |
// No operand predicates |
14621 |
// No operand predicates |
| 14622 |
GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18] |
14622 |
GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18] |
| 14623 |
GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT, |
14623 |
GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT, |
| 14624 |
GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
14624 |
GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 14625 |
// MIs[18] Operand 1 |
14625 |
// MIs[18] Operand 1 |
| 14626 |
// No operand predicates |
14626 |
// No operand predicates |
| 14627 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14627 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14628 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
14628 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14629 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
14629 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14630 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
14630 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14631 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
14631 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 14632 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
14632 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 14633 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
14633 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
| 14634 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
14634 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
| 14635 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
14635 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
| 14636 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
14636 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
| 14637 |
GIM_CheckIsSafeToFold, /*InsnID*/11, |
14637 |
GIM_CheckIsSafeToFold, /*InsnID*/11, |
| 14638 |
GIM_CheckIsSafeToFold, /*InsnID*/12, |
14638 |
GIM_CheckIsSafeToFold, /*InsnID*/12, |
| 14639 |
GIM_CheckIsSafeToFold, /*InsnID*/13, |
14639 |
GIM_CheckIsSafeToFold, /*InsnID*/13, |
| 14640 |
GIM_CheckIsSafeToFold, /*InsnID*/14, |
14640 |
GIM_CheckIsSafeToFold, /*InsnID*/14, |
| 14641 |
GIM_CheckIsSafeToFold, /*InsnID*/15, |
14641 |
GIM_CheckIsSafeToFold, /*InsnID*/15, |
| 14642 |
GIM_CheckIsSafeToFold, /*InsnID*/16, |
14642 |
GIM_CheckIsSafeToFold, /*InsnID*/16, |
| 14643 |
GIM_CheckIsSafeToFold, /*InsnID*/17, |
14643 |
GIM_CheckIsSafeToFold, /*InsnID*/17, |
| 14644 |
GIM_CheckIsSafeToFold, /*InsnID*/18, |
14644 |
GIM_CheckIsSafeToFold, /*InsnID*/18, |
| 14645 |
// (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt) |
14645 |
// (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt) |
| 14646 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_B, |
14646 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_B, |
| 14647 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
14647 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 14648 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
14648 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 14649 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
14649 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
| 14650 |
GIR_EraseFromParent, /*InsnID*/0, |
14650 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14651 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14651 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14652 |
// GIR_Coverage, 2037, |
14652 |
// GIR_Coverage, 2037, |
| 14653 |
GIR_Done, |
14653 |
GIR_Done, |
| 14654 |
// Label 904: @35603 |
14654 |
// Label 904: @35603 |
| 14655 |
GIM_Try, /*On fail goto*//*Label 905*/ 35622, // Rule ID 977 // |
14655 |
GIM_Try, /*On fail goto*//*Label 905*/ 35622, // Rule ID 977 // |
| 14656 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
14656 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 14657 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
14657 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 14658 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
14658 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 14659 |
// (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
14659 |
// (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 14660 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_B, |
14660 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_B, |
| 14661 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14661 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14662 |
// GIR_Coverage, 977, |
14662 |
// GIR_Coverage, 977, |
| 14663 |
GIR_Done, |
14663 |
GIR_Done, |
| 14664 |
// Label 905: @35622 |
14664 |
// Label 905: @35622 |
| 14665 |
GIM_Reject, |
14665 |
GIM_Reject, |
| 14666 |
// Label 902: @35623 |
14666 |
// Label 902: @35623 |
| 14667 |
GIM_Reject, |
14667 |
GIM_Reject, |
| 14668 |
// Label 880: @35624 |
14668 |
// Label 880: @35624 |
| 14669 |
GIM_Reject, |
14669 |
GIM_Reject, |
| 14670 |
// Label 25: @35625 |
14670 |
// Label 25: @35625 |
| 14671 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 912*/ 37334, |
14671 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 912*/ 37334, |
| 14672 |
/*GILLT_s32*//*Label 906*/ 35639, |
14672 |
/*GILLT_s32*//*Label 906*/ 35639, |
| 14673 |
/*GILLT_s64*//*Label 907*/ 35849, 0, |
14673 |
/*GILLT_s64*//*Label 907*/ 35849, 0, |
| 14674 |
/*GILLT_v2s64*//*Label 908*/ 35983, 0, |
14674 |
/*GILLT_v2s64*//*Label 908*/ 35983, 0, |
| 14675 |
/*GILLT_v4s32*//*Label 909*/ 36015, |
14675 |
/*GILLT_v4s32*//*Label 909*/ 36015, |
| 14676 |
/*GILLT_v8s16*//*Label 910*/ 36284, |
14676 |
/*GILLT_v8s16*//*Label 910*/ 36284, |
| 14677 |
/*GILLT_v16s8*//*Label 911*/ 36681, |
14677 |
/*GILLT_v16s8*//*Label 911*/ 36681, |
| 14678 |
// Label 906: @35639 |
14678 |
// Label 906: @35639 |
| 14679 |
GIM_Try, /*On fail goto*//*Label 913*/ 35848, |
14679 |
GIM_Try, /*On fail goto*//*Label 913*/ 35848, |
| 14680 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
14680 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 14681 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
14681 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 14682 |
GIM_Try, /*On fail goto*//*Label 914*/ 35692, // Rule ID 57 // |
14682 |
GIM_Try, /*On fail goto*//*Label 914*/ 35692, // Rule ID 57 // |
| 14683 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
14683 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 14684 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
14684 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 14685 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
14685 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 14686 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14686 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14687 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
14687 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 14688 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
14688 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 14689 |
// MIs[1] Operand 1 |
14689 |
// MIs[1] Operand 1 |
| 14690 |
// No operand predicates |
14690 |
// No operand predicates |
| 14691 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14691 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14692 |
// (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt) |
14692 |
// (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt) |
| 14693 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA, |
14693 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA, |
| 14694 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
14694 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 14695 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
14695 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 14696 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
14696 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 14697 |
GIR_EraseFromParent, /*InsnID*/0, |
14697 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14698 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14698 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14699 |
// GIR_Coverage, 57, |
14699 |
// GIR_Coverage, 57, |
| 14700 |
GIR_Done, |
14700 |
GIR_Done, |
| 14701 |
// Label 914: @35692 |
14701 |
// Label 914: @35692 |
| 14702 |
GIM_Try, /*On fail goto*//*Label 915*/ 35735, // Rule ID 1793 // |
14702 |
GIM_Try, /*On fail goto*//*Label 915*/ 35735, // Rule ID 1793 // |
| 14703 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
14703 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 14704 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
14704 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 14705 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
14705 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 14706 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14706 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14707 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
14707 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 14708 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
14708 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 14709 |
// MIs[1] Operand 1 |
14709 |
// MIs[1] Operand 1 |
| 14710 |
// No operand predicates |
14710 |
// No operand predicates |
| 14711 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14711 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14712 |
// (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<>:$imm) => (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<>:$imm) |
14712 |
// (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<>:$imm) => (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<>:$imm) |
| 14713 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SraX16, |
14713 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SraX16, |
| 14714 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx |
14714 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx |
| 14715 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
14715 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in |
| 14716 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
14716 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 14717 |
GIR_EraseFromParent, /*InsnID*/0, |
14717 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14718 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14718 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14719 |
// GIR_Coverage, 1793, |
14719 |
// GIR_Coverage, 1793, |
| 14720 |
GIR_Done, |
14720 |
GIR_Done, |
| 14721 |
// Label 915: @35735 |
14721 |
// Label 915: @35735 |
| 14722 |
GIM_Try, /*On fail goto*//*Label 916*/ 35778, // Rule ID 2134 // |
14722 |
GIM_Try, /*On fail goto*//*Label 916*/ 35778, // Rule ID 2134 // |
| 14723 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
14723 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 14724 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
14724 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 14725 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
14725 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 14726 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14726 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14727 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
14727 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 14728 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
14728 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 14729 |
// MIs[1] Operand 1 |
14729 |
// MIs[1] Operand 1 |
| 14730 |
// No operand predicates |
14730 |
// No operand predicates |
| 14731 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14731 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14732 |
// (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
14732 |
// (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) => (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<>:$imm) |
| 14733 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_MM, |
14733 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_MM, |
| 14734 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
14734 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 14735 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
14735 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 14736 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
14736 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 14737 |
GIR_EraseFromParent, /*InsnID*/0, |
14737 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14738 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14738 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14739 |
// GIR_Coverage, 2134, |
14739 |
// GIR_Coverage, 2134, |
| 14740 |
GIR_Done, |
14740 |
GIR_Done, |
| 14741 |
// Label 916: @35778 |
14741 |
// Label 916: @35778 |
| 14742 |
GIM_Try, /*On fail goto*//*Label 917*/ 35801, // Rule ID 60 // |
14742 |
GIM_Try, /*On fail goto*//*Label 917*/ 35801, // Rule ID 60 // |
| 14743 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
14743 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 14744 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
14744 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 14745 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
14745 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 14746 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
14746 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 14747 |
// (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
14747 |
// (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 14748 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV, |
14748 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV, |
| 14749 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14749 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14750 |
// GIR_Coverage, 60, |
14750 |
// GIR_Coverage, 60, |
| 14751 |
GIR_Done, |
14751 |
GIR_Done, |
| 14752 |
// Label 917: @35801 |
14752 |
// Label 917: @35801 |
| 14753 |
GIM_Try, /*On fail goto*//*Label 918*/ 35824, // Rule ID 1795 // |
14753 |
GIM_Try, /*On fail goto*//*Label 918*/ 35824, // Rule ID 1795 // |
| 14754 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
14754 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 14755 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
14755 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 14756 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
14756 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 14757 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
14757 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 14758 |
// (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) |
14758 |
// (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) |
| 14759 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SravRxRy16, |
14759 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SravRxRy16, |
| 14760 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14760 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14761 |
// GIR_Coverage, 1795, |
14761 |
// GIR_Coverage, 1795, |
| 14762 |
GIR_Done, |
14762 |
GIR_Done, |
| 14763 |
// Label 918: @35824 |
14763 |
// Label 918: @35824 |
| 14764 |
GIM_Try, /*On fail goto*//*Label 919*/ 35847, // Rule ID 2135 // |
14764 |
GIM_Try, /*On fail goto*//*Label 919*/ 35847, // Rule ID 2135 // |
| 14765 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
14765 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 14766 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
14766 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 14767 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
14767 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 14768 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
14768 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 14769 |
// (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) |
14769 |
// (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) |
| 14770 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV_MM, |
14770 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV_MM, |
| 14771 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14771 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14772 |
// GIR_Coverage, 2135, |
14772 |
// GIR_Coverage, 2135, |
| 14773 |
GIR_Done, |
14773 |
GIR_Done, |
| 14774 |
// Label 919: @35847 |
14774 |
// Label 919: @35847 |
| 14775 |
GIM_Reject, |
14775 |
GIM_Reject, |
| 14776 |
// Label 913: @35848 |
14776 |
// Label 913: @35848 |
| 14777 |
GIM_Reject, |
14777 |
GIM_Reject, |
| 14778 |
// Label 907: @35849 |
14778 |
// Label 907: @35849 |
| 14779 |
GIM_Try, /*On fail goto*//*Label 920*/ 35982, |
14779 |
GIM_Try, /*On fail goto*//*Label 920*/ 35982, |
| 14780 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
14780 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 14781 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
14781 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 14782 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
14782 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 14783 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
14783 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 14784 |
GIM_Try, /*On fail goto*//*Label 921*/ 35902, // Rule ID 206 // |
14784 |
GIM_Try, /*On fail goto*//*Label 921*/ 35902, // Rule ID 206 // |
| 14785 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
14785 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
| 14786 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14786 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14787 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
14787 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 14788 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt6, |
14788 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt6, |
| 14789 |
// MIs[1] Operand 1 |
14789 |
// MIs[1] Operand 1 |
| 14790 |
// No operand predicates |
14790 |
// No operand predicates |
| 14791 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14791 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14792 |
// (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt) |
14792 |
// (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt) |
| 14793 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRA, |
14793 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRA, |
| 14794 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
14794 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 14795 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
14795 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 14796 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
14796 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 14797 |
GIR_EraseFromParent, /*InsnID*/0, |
14797 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14798 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14798 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14799 |
// GIR_Coverage, 206, |
14799 |
// GIR_Coverage, 206, |
| 14800 |
GIR_Done, |
14800 |
GIR_Done, |
| 14801 |
// Label 921: @35902 |
14801 |
// Label 921: @35902 |
| 14802 |
GIM_Try, /*On fail goto*//*Label 922*/ 35966, // Rule ID 1564 // |
14802 |
GIM_Try, /*On fail goto*//*Label 922*/ 35966, // Rule ID 1564 // |
| 14803 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
14803 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
| 14804 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14804 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14805 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
14805 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 14806 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
14806 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 14807 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
14807 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 14808 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14808 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14809 |
// (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] })) |
14809 |
// (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] })) |
| 14810 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
14810 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 14811 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
14811 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 14812 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
14812 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 14813 |
GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs |
14813 |
GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs |
| 14814 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::GPR32RegClassID, |
14814 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::GPR32RegClassID, |
| 14815 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID, |
14815 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID, |
| 14816 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRAV, |
14816 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRAV, |
| 14817 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
14817 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 14818 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
14818 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 14819 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
14819 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 14820 |
GIR_EraseFromParent, /*InsnID*/0, |
14820 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14821 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14821 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14822 |
// GIR_Coverage, 1564, |
14822 |
// GIR_Coverage, 1564, |
| 14823 |
GIR_Done, |
14823 |
GIR_Done, |
| 14824 |
// Label 922: @35966 |
14824 |
// Label 922: @35966 |
| 14825 |
GIM_Try, /*On fail goto*//*Label 923*/ 35981, // Rule ID 208 // |
14825 |
GIM_Try, /*On fail goto*//*Label 923*/ 35981, // Rule ID 208 // |
| 14826 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
14826 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips, |
| 14827 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
14827 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 14828 |
// (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
14828 |
// (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 14829 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRAV, |
14829 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRAV, |
| 14830 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14830 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14831 |
// GIR_Coverage, 208, |
14831 |
// GIR_Coverage, 208, |
| 14832 |
GIR_Done, |
14832 |
GIR_Done, |
| 14833 |
// Label 923: @35981 |
14833 |
// Label 923: @35981 |
| 14834 |
GIM_Reject, |
14834 |
GIM_Reject, |
| 14835 |
// Label 920: @35982 |
14835 |
// Label 920: @35982 |
| 14836 |
GIM_Reject, |
14836 |
GIM_Reject, |
| 14837 |
// Label 908: @35983 |
14837 |
// Label 908: @35983 |
| 14838 |
GIM_Try, /*On fail goto*//*Label 924*/ 36014, // Rule ID 964 // |
14838 |
GIM_Try, /*On fail goto*//*Label 924*/ 36014, // Rule ID 964 // |
| 14839 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
14839 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 14840 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
14840 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 14841 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
14841 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 14842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
14842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 14843 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
14843 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 14844 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
14844 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 14845 |
// (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
14845 |
// (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 14846 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_D, |
14846 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_D, |
| 14847 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14847 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14848 |
// GIR_Coverage, 964, |
14848 |
// GIR_Coverage, 964, |
| 14849 |
GIR_Done, |
14849 |
GIR_Done, |
| 14850 |
// Label 924: @36014 |
14850 |
// Label 924: @36014 |
| 14851 |
GIM_Reject, |
14851 |
GIM_Reject, |
| 14852 |
// Label 909: @36015 |
14852 |
// Label 909: @36015 |
| 14853 |
GIM_Try, /*On fail goto*//*Label 925*/ 36283, |
14853 |
GIM_Try, /*On fail goto*//*Label 925*/ 36283, |
| 14854 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
14854 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14855 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
14855 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14856 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
14856 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 14857 |
GIM_Try, /*On fail goto*//*Label 926*/ 36146, // Rule ID 2434 // |
14857 |
GIM_Try, /*On fail goto*//*Label 926*/ 36146, // Rule ID 2434 // |
| 14858 |
GIM_CheckFeatures, GIFBS_HasMSA, |
14858 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 14859 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14859 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14860 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
14860 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14861 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
14861 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14862 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
14862 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14863 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
14863 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14864 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
14864 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 14865 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/5, |
14865 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/5, |
| 14866 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
14866 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14867 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
14867 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 14868 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
14868 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 14869 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
14869 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 14870 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
14870 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14871 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
14871 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 14872 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14872 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14873 |
// MIs[3] Operand 1 |
14873 |
// MIs[3] Operand 1 |
| 14874 |
// No operand predicates |
14874 |
// No operand predicates |
| 14875 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
14875 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 14876 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
14876 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 14877 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14877 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14878 |
// MIs[4] Operand 1 |
14878 |
// MIs[4] Operand 1 |
| 14879 |
// No operand predicates |
14879 |
// No operand predicates |
| 14880 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
14880 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 14881 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
14881 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 14882 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14882 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14883 |
// MIs[5] Operand 1 |
14883 |
// MIs[5] Operand 1 |
| 14884 |
// No operand predicates |
14884 |
// No operand predicates |
| 14885 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
14885 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 14886 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
14886 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 14887 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14887 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14888 |
// MIs[6] Operand 1 |
14888 |
// MIs[6] Operand 1 |
| 14889 |
// No operand predicates |
14889 |
// No operand predicates |
| 14890 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14890 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14891 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
14891 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14892 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
14892 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14893 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
14893 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14894 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
14894 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 14895 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
14895 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 14896 |
// (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v4i32:{ *:[v4i32] }:$wt)) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt) |
14896 |
// (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v4i32:{ *:[v4i32] }:$wt)) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt) |
| 14897 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_W, |
14897 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_W, |
| 14898 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
14898 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 14899 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
14899 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 14900 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
14900 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 14901 |
GIR_EraseFromParent, /*InsnID*/0, |
14901 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14902 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14902 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14903 |
// GIR_Coverage, 2434, |
14903 |
// GIR_Coverage, 2434, |
| 14904 |
GIR_Done, |
14904 |
GIR_Done, |
| 14905 |
// Label 926: @36146 |
14905 |
// Label 926: @36146 |
| 14906 |
GIM_Try, /*On fail goto*//*Label 927*/ 36263, // Rule ID 2043 // |
14906 |
GIM_Try, /*On fail goto*//*Label 927*/ 36263, // Rule ID 2043 // |
| 14907 |
GIM_CheckFeatures, GIFBS_HasMSA, |
14907 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 14908 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14908 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14909 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
14909 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14910 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
14910 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14911 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
14911 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14912 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
14912 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 14913 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
14913 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 14914 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/5, |
14914 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/5, |
| 14915 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
14915 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14916 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
14916 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 14917 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
14917 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 14918 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
14918 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 14919 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
14919 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14920 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
14920 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 14921 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14921 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14922 |
// MIs[3] Operand 1 |
14922 |
// MIs[3] Operand 1 |
| 14923 |
// No operand predicates |
14923 |
// No operand predicates |
| 14924 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
14924 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 14925 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
14925 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 14926 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14926 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14927 |
// MIs[4] Operand 1 |
14927 |
// MIs[4] Operand 1 |
| 14928 |
// No operand predicates |
14928 |
// No operand predicates |
| 14929 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
14929 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 14930 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
14930 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 14931 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14931 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14932 |
// MIs[5] Operand 1 |
14932 |
// MIs[5] Operand 1 |
| 14933 |
// No operand predicates |
14933 |
// No operand predicates |
| 14934 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
14934 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 14935 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
14935 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 14936 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
14936 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst31, |
| 14937 |
// MIs[6] Operand 1 |
14937 |
// MIs[6] Operand 1 |
| 14938 |
// No operand predicates |
14938 |
// No operand predicates |
| 14939 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
14939 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 14940 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
14940 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 14941 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
14941 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 14942 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
14942 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 14943 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
14943 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 14944 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
14944 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 14945 |
// (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt) |
14945 |
// (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt) |
| 14946 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_W, |
14946 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_W, |
| 14947 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
14947 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 14948 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
14948 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 14949 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
14949 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
| 14950 |
GIR_EraseFromParent, /*InsnID*/0, |
14950 |
GIR_EraseFromParent, /*InsnID*/0, |
| 14951 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14951 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14952 |
// GIR_Coverage, 2043, |
14952 |
// GIR_Coverage, 2043, |
| 14953 |
GIR_Done, |
14953 |
GIR_Done, |
| 14954 |
// Label 927: @36263 |
14954 |
// Label 927: @36263 |
| 14955 |
GIM_Try, /*On fail goto*//*Label 928*/ 36282, // Rule ID 963 // |
14955 |
GIM_Try, /*On fail goto*//*Label 928*/ 36282, // Rule ID 963 // |
| 14956 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
14956 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 14957 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
14957 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 14958 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
14958 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 14959 |
// (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
14959 |
// (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 14960 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_W, |
14960 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_W, |
| 14961 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
14961 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 14962 |
// GIR_Coverage, 963, |
14962 |
// GIR_Coverage, 963, |
| 14963 |
GIR_Done, |
14963 |
GIR_Done, |
| 14964 |
// Label 928: @36282 |
14964 |
// Label 928: @36282 |
| 14965 |
GIM_Reject, |
14965 |
GIM_Reject, |
| 14966 |
// Label 925: @36283 |
14966 |
// Label 925: @36283 |
| 14967 |
GIM_Reject, |
14967 |
GIM_Reject, |
| 14968 |
// Label 910: @36284 |
14968 |
// Label 910: @36284 |
| 14969 |
GIM_Try, /*On fail goto*//*Label 929*/ 36680, |
14969 |
GIM_Try, /*On fail goto*//*Label 929*/ 36680, |
| 14970 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
14970 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14971 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
14971 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14972 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
14972 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 14973 |
GIM_Try, /*On fail goto*//*Label 930*/ 36479, // Rule ID 2433 // |
14973 |
GIM_Try, /*On fail goto*//*Label 930*/ 36479, // Rule ID 2433 // |
| 14974 |
GIM_CheckFeatures, GIFBS_HasMSA, |
14974 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 14975 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
14975 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 14976 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
14976 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 14977 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
14977 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 14978 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
14978 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14979 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
14979 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 14980 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
14980 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 14981 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/9, |
14981 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/9, |
| 14982 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
14982 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 14983 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
14983 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 14984 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
14984 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 14985 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
14985 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 14986 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
14986 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
| 14987 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
14987 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
| 14988 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
14988 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
| 14989 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
14989 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
| 14990 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
14990 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 14991 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
14991 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 14992 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14992 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14993 |
// MIs[3] Operand 1 |
14993 |
// MIs[3] Operand 1 |
| 14994 |
// No operand predicates |
14994 |
// No operand predicates |
| 14995 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
14995 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 14996 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
14996 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 14997 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
14997 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 14998 |
// MIs[4] Operand 1 |
14998 |
// MIs[4] Operand 1 |
| 14999 |
// No operand predicates |
14999 |
// No operand predicates |
| 15000 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
15000 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 15001 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
15001 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 15002 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15002 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15003 |
// MIs[5] Operand 1 |
15003 |
// MIs[5] Operand 1 |
| 15004 |
// No operand predicates |
15004 |
// No operand predicates |
| 15005 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
15005 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 15006 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
15006 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 15007 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15007 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15008 |
// MIs[6] Operand 1 |
15008 |
// MIs[6] Operand 1 |
| 15009 |
// No operand predicates |
15009 |
// No operand predicates |
| 15010 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
15010 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
| 15011 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
15011 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
| 15012 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15012 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15013 |
// MIs[7] Operand 1 |
15013 |
// MIs[7] Operand 1 |
| 15014 |
// No operand predicates |
15014 |
// No operand predicates |
| 15015 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
15015 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
| 15016 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
15016 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
| 15017 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15017 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15018 |
// MIs[8] Operand 1 |
15018 |
// MIs[8] Operand 1 |
| 15019 |
// No operand predicates |
15019 |
// No operand predicates |
| 15020 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
15020 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
| 15021 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
15021 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
| 15022 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15022 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15023 |
// MIs[9] Operand 1 |
15023 |
// MIs[9] Operand 1 |
| 15024 |
// No operand predicates |
15024 |
// No operand predicates |
| 15025 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
15025 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
| 15026 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
15026 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
| 15027 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15027 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15028 |
// MIs[10] Operand 1 |
15028 |
// MIs[10] Operand 1 |
| 15029 |
// No operand predicates |
15029 |
// No operand predicates |
| 15030 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
15030 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15031 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
15031 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 15032 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
15032 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 15033 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
15033 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 15034 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
15034 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 15035 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
15035 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 15036 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
15036 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
| 15037 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
15037 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
| 15038 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
15038 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
| 15039 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
15039 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
| 15040 |
// (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v8i16:{ *:[v8i16] }:$wt)) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt) |
15040 |
// (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v8i16:{ *:[v8i16] }:$wt)) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt) |
| 15041 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_H, |
15041 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_H, |
| 15042 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
15042 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 15043 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
15043 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 15044 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
15044 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 15045 |
GIR_EraseFromParent, /*InsnID*/0, |
15045 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15046 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15046 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15047 |
// GIR_Coverage, 2433, |
15047 |
// GIR_Coverage, 2433, |
| 15048 |
GIR_Done, |
15048 |
GIR_Done, |
| 15049 |
// Label 930: @36479 |
15049 |
// Label 930: @36479 |
| 15050 |
GIM_Try, /*On fail goto*//*Label 931*/ 36660, // Rule ID 2042 // |
15050 |
GIM_Try, /*On fail goto*//*Label 931*/ 36660, // Rule ID 2042 // |
| 15051 |
GIM_CheckFeatures, GIFBS_HasMSA, |
15051 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 15052 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
15052 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15053 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
15053 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 15054 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
15054 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 15055 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
15055 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15056 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
15056 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 15057 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
15057 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 15058 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/9, |
15058 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/9, |
| 15059 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
15059 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 15060 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
15060 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 15061 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
15061 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 15062 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
15062 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 15063 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
15063 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
| 15064 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
15064 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
| 15065 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
15065 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
| 15066 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
15066 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
| 15067 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
15067 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 15068 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
15068 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 15069 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15069 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15070 |
// MIs[3] Operand 1 |
15070 |
// MIs[3] Operand 1 |
| 15071 |
// No operand predicates |
15071 |
// No operand predicates |
| 15072 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
15072 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 15073 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
15073 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 15074 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15074 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15075 |
// MIs[4] Operand 1 |
15075 |
// MIs[4] Operand 1 |
| 15076 |
// No operand predicates |
15076 |
// No operand predicates |
| 15077 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
15077 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 15078 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
15078 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 15079 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15079 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15080 |
// MIs[5] Operand 1 |
15080 |
// MIs[5] Operand 1 |
| 15081 |
// No operand predicates |
15081 |
// No operand predicates |
| 15082 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
15082 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 15083 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
15083 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 15084 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15084 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15085 |
// MIs[6] Operand 1 |
15085 |
// MIs[6] Operand 1 |
| 15086 |
// No operand predicates |
15086 |
// No operand predicates |
| 15087 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
15087 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
| 15088 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
15088 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
| 15089 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15089 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15090 |
// MIs[7] Operand 1 |
15090 |
// MIs[7] Operand 1 |
| 15091 |
// No operand predicates |
15091 |
// No operand predicates |
| 15092 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
15092 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
| 15093 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
15093 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
| 15094 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15094 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15095 |
// MIs[8] Operand 1 |
15095 |
// MIs[8] Operand 1 |
| 15096 |
// No operand predicates |
15096 |
// No operand predicates |
| 15097 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
15097 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
| 15098 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
15098 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
| 15099 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15099 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15100 |
// MIs[9] Operand 1 |
15100 |
// MIs[9] Operand 1 |
| 15101 |
// No operand predicates |
15101 |
// No operand predicates |
| 15102 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
15102 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
| 15103 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
15103 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
| 15104 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
15104 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst15, |
| 15105 |
// MIs[10] Operand 1 |
15105 |
// MIs[10] Operand 1 |
| 15106 |
// No operand predicates |
15106 |
// No operand predicates |
| 15107 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
15107 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15108 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
15108 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 15109 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
15109 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 15110 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
15110 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 15111 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
15111 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 15112 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
15112 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 15113 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
15113 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
| 15114 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
15114 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
| 15115 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
15115 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
| 15116 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
15116 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
| 15117 |
// (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt) |
15117 |
// (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt) |
| 15118 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_H, |
15118 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_H, |
| 15119 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
15119 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 15120 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
15120 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 15121 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
15121 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
| 15122 |
GIR_EraseFromParent, /*InsnID*/0, |
15122 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15123 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15123 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15124 |
// GIR_Coverage, 2042, |
15124 |
// GIR_Coverage, 2042, |
| 15125 |
GIR_Done, |
15125 |
GIR_Done, |
| 15126 |
// Label 931: @36660 |
15126 |
// Label 931: @36660 |
| 15127 |
GIM_Try, /*On fail goto*//*Label 932*/ 36679, // Rule ID 962 // |
15127 |
GIM_Try, /*On fail goto*//*Label 932*/ 36679, // Rule ID 962 // |
| 15128 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
15128 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 15129 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
15129 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 15130 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
15130 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 15131 |
// (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
15131 |
// (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 15132 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_H, |
15132 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_H, |
| 15133 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15133 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15134 |
// GIR_Coverage, 962, |
15134 |
// GIR_Coverage, 962, |
| 15135 |
GIR_Done, |
15135 |
GIR_Done, |
| 15136 |
// Label 932: @36679 |
15136 |
// Label 932: @36679 |
| 15137 |
GIM_Reject, |
15137 |
GIM_Reject, |
| 15138 |
// Label 929: @36680 |
15138 |
// Label 929: @36680 |
| 15139 |
GIM_Reject, |
15139 |
GIM_Reject, |
| 15140 |
// Label 911: @36681 |
15140 |
// Label 911: @36681 |
| 15141 |
GIM_Try, /*On fail goto*//*Label 933*/ 37333, |
15141 |
GIM_Try, /*On fail goto*//*Label 933*/ 37333, |
| 15142 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
15142 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 15143 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
15143 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15144 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
15144 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 15145 |
GIM_Try, /*On fail goto*//*Label 934*/ 37004, // Rule ID 2432 // |
15145 |
GIM_Try, /*On fail goto*//*Label 934*/ 37004, // Rule ID 2432 // |
| 15146 |
GIM_CheckFeatures, GIFBS_HasMSA, |
15146 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 15147 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
15147 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15148 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
15148 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 15149 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
15149 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 15150 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
15150 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15151 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
15151 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 15152 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
15152 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 15153 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/17, |
15153 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/17, |
| 15154 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
15154 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 15155 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
15155 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 15156 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
15156 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 15157 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
15157 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 15158 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
15158 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
| 15159 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
15159 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
| 15160 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
15160 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
| 15161 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
15161 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
| 15162 |
GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32, |
15162 |
GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32, |
| 15163 |
GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32, |
15163 |
GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32, |
| 15164 |
GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32, |
15164 |
GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32, |
| 15165 |
GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32, |
15165 |
GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32, |
| 15166 |
GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32, |
15166 |
GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32, |
| 15167 |
GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32, |
15167 |
GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32, |
| 15168 |
GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32, |
15168 |
GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32, |
| 15169 |
GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32, |
15169 |
GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32, |
| 15170 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
15170 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 15171 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
15171 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 15172 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15172 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15173 |
// MIs[3] Operand 1 |
15173 |
// MIs[3] Operand 1 |
| 15174 |
// No operand predicates |
15174 |
// No operand predicates |
| 15175 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
15175 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 15176 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
15176 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 15177 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15177 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15178 |
// MIs[4] Operand 1 |
15178 |
// MIs[4] Operand 1 |
| 15179 |
// No operand predicates |
15179 |
// No operand predicates |
| 15180 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
15180 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 15181 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
15181 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 15182 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15182 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15183 |
// MIs[5] Operand 1 |
15183 |
// MIs[5] Operand 1 |
| 15184 |
// No operand predicates |
15184 |
// No operand predicates |
| 15185 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
15185 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 15186 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
15186 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 15187 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15187 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15188 |
// MIs[6] Operand 1 |
15188 |
// MIs[6] Operand 1 |
| 15189 |
// No operand predicates |
15189 |
// No operand predicates |
| 15190 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
15190 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
| 15191 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
15191 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
| 15192 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15192 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15193 |
// MIs[7] Operand 1 |
15193 |
// MIs[7] Operand 1 |
| 15194 |
// No operand predicates |
15194 |
// No operand predicates |
| 15195 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
15195 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
| 15196 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
15196 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
| 15197 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15197 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15198 |
// MIs[8] Operand 1 |
15198 |
// MIs[8] Operand 1 |
| 15199 |
// No operand predicates |
15199 |
// No operand predicates |
| 15200 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
15200 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
| 15201 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
15201 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
| 15202 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15202 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15203 |
// MIs[9] Operand 1 |
15203 |
// MIs[9] Operand 1 |
| 15204 |
// No operand predicates |
15204 |
// No operand predicates |
| 15205 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
15205 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
| 15206 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
15206 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
| 15207 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15207 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15208 |
// MIs[10] Operand 1 |
15208 |
// MIs[10] Operand 1 |
| 15209 |
// No operand predicates |
15209 |
// No operand predicates |
| 15210 |
GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11] |
15210 |
GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11] |
| 15211 |
GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT, |
15211 |
GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT, |
| 15212 |
GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15212 |
GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15213 |
// MIs[11] Operand 1 |
15213 |
// MIs[11] Operand 1 |
| 15214 |
// No operand predicates |
15214 |
// No operand predicates |
| 15215 |
GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12] |
15215 |
GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12] |
| 15216 |
GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT, |
15216 |
GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT, |
| 15217 |
GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15217 |
GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15218 |
// MIs[12] Operand 1 |
15218 |
// MIs[12] Operand 1 |
| 15219 |
// No operand predicates |
15219 |
// No operand predicates |
| 15220 |
GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13] |
15220 |
GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13] |
| 15221 |
GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT, |
15221 |
GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT, |
| 15222 |
GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15222 |
GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15223 |
// MIs[13] Operand 1 |
15223 |
// MIs[13] Operand 1 |
| 15224 |
// No operand predicates |
15224 |
// No operand predicates |
| 15225 |
GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14] |
15225 |
GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14] |
| 15226 |
GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT, |
15226 |
GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT, |
| 15227 |
GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15227 |
GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15228 |
// MIs[14] Operand 1 |
15228 |
// MIs[14] Operand 1 |
| 15229 |
// No operand predicates |
15229 |
// No operand predicates |
| 15230 |
GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15] |
15230 |
GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15] |
| 15231 |
GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT, |
15231 |
GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT, |
| 15232 |
GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15232 |
GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15233 |
// MIs[15] Operand 1 |
15233 |
// MIs[15] Operand 1 |
| 15234 |
// No operand predicates |
15234 |
// No operand predicates |
| 15235 |
GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16] |
15235 |
GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16] |
| 15236 |
GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT, |
15236 |
GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT, |
| 15237 |
GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15237 |
GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15238 |
// MIs[16] Operand 1 |
15238 |
// MIs[16] Operand 1 |
| 15239 |
// No operand predicates |
15239 |
// No operand predicates |
| 15240 |
GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17] |
15240 |
GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17] |
| 15241 |
GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT, |
15241 |
GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT, |
| 15242 |
GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15242 |
GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15243 |
// MIs[17] Operand 1 |
15243 |
// MIs[17] Operand 1 |
| 15244 |
// No operand predicates |
15244 |
// No operand predicates |
| 15245 |
GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18] |
15245 |
GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18] |
| 15246 |
GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT, |
15246 |
GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT, |
| 15247 |
GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15247 |
GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15248 |
// MIs[18] Operand 1 |
15248 |
// MIs[18] Operand 1 |
| 15249 |
// No operand predicates |
15249 |
// No operand predicates |
| 15250 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
15250 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15251 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
15251 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 15252 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
15252 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 15253 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
15253 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 15254 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
15254 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 15255 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
15255 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 15256 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
15256 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
| 15257 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
15257 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
| 15258 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
15258 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
| 15259 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
15259 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
| 15260 |
GIM_CheckIsSafeToFold, /*InsnID*/11, |
15260 |
GIM_CheckIsSafeToFold, /*InsnID*/11, |
| 15261 |
GIM_CheckIsSafeToFold, /*InsnID*/12, |
15261 |
GIM_CheckIsSafeToFold, /*InsnID*/12, |
| 15262 |
GIM_CheckIsSafeToFold, /*InsnID*/13, |
15262 |
GIM_CheckIsSafeToFold, /*InsnID*/13, |
| 15263 |
GIM_CheckIsSafeToFold, /*InsnID*/14, |
15263 |
GIM_CheckIsSafeToFold, /*InsnID*/14, |
| 15264 |
GIM_CheckIsSafeToFold, /*InsnID*/15, |
15264 |
GIM_CheckIsSafeToFold, /*InsnID*/15, |
| 15265 |
GIM_CheckIsSafeToFold, /*InsnID*/16, |
15265 |
GIM_CheckIsSafeToFold, /*InsnID*/16, |
| 15266 |
GIM_CheckIsSafeToFold, /*InsnID*/17, |
15266 |
GIM_CheckIsSafeToFold, /*InsnID*/17, |
| 15267 |
GIM_CheckIsSafeToFold, /*InsnID*/18, |
15267 |
GIM_CheckIsSafeToFold, /*InsnID*/18, |
| 15268 |
// (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v16i8:{ *:[v16i8] }:$wt)) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt) |
15268 |
// (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>), v16i8:{ *:[v16i8] }:$wt)) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt) |
| 15269 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_B, |
15269 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_B, |
| 15270 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
15270 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 15271 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
15271 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 15272 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
15272 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 15273 |
GIR_EraseFromParent, /*InsnID*/0, |
15273 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15274 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15274 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15275 |
// GIR_Coverage, 2432, |
15275 |
// GIR_Coverage, 2432, |
| 15276 |
GIR_Done, |
15276 |
GIR_Done, |
| 15277 |
// Label 934: @37004 |
15277 |
// Label 934: @37004 |
| 15278 |
GIM_Try, /*On fail goto*//*Label 935*/ 37313, // Rule ID 2041 // |
15278 |
GIM_Try, /*On fail goto*//*Label 935*/ 37313, // Rule ID 2041 // |
| 15279 |
GIM_CheckFeatures, GIFBS_HasMSA, |
15279 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 15280 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
15280 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15281 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
15281 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, |
| 15282 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
15282 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 15283 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
15283 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15284 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
15284 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 15285 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
15285 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_BUILD_VECTOR, |
| 15286 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/17, |
15286 |
GIM_CheckNumOperands, /*MI*/2, /*Expected*/17, |
| 15287 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
15287 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 15288 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
15288 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 15289 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
15289 |
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 15290 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
15290 |
GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32, |
| 15291 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
15291 |
GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32, |
| 15292 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
15292 |
GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32, |
| 15293 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
15293 |
GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32, |
| 15294 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
15294 |
GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32, |
| 15295 |
GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32, |
15295 |
GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32, |
| 15296 |
GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32, |
15296 |
GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32, |
| 15297 |
GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32, |
15297 |
GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32, |
| 15298 |
GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32, |
15298 |
GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32, |
| 15299 |
GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32, |
15299 |
GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32, |
| 15300 |
GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32, |
15300 |
GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32, |
| 15301 |
GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32, |
15301 |
GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32, |
| 15302 |
GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32, |
15302 |
GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32, |
| 15303 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
15303 |
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 15304 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
15304 |
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_CONSTANT, |
| 15305 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15305 |
GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15306 |
// MIs[3] Operand 1 |
15306 |
// MIs[3] Operand 1 |
| 15307 |
// No operand predicates |
15307 |
// No operand predicates |
| 15308 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
15308 |
GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 15309 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
15309 |
GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_CONSTANT, |
| 15310 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15310 |
GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15311 |
// MIs[4] Operand 1 |
15311 |
// MIs[4] Operand 1 |
| 15312 |
// No operand predicates |
15312 |
// No operand predicates |
| 15313 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
15313 |
GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5] |
| 15314 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
15314 |
GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_CONSTANT, |
| 15315 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15315 |
GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15316 |
// MIs[5] Operand 1 |
15316 |
// MIs[5] Operand 1 |
| 15317 |
// No operand predicates |
15317 |
// No operand predicates |
| 15318 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
15318 |
GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6] |
| 15319 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
15319 |
GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_CONSTANT, |
| 15320 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15320 |
GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15321 |
// MIs[6] Operand 1 |
15321 |
// MIs[6] Operand 1 |
| 15322 |
// No operand predicates |
15322 |
// No operand predicates |
| 15323 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
15323 |
GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7] |
| 15324 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
15324 |
GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_CONSTANT, |
| 15325 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15325 |
GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15326 |
// MIs[7] Operand 1 |
15326 |
// MIs[7] Operand 1 |
| 15327 |
// No operand predicates |
15327 |
// No operand predicates |
| 15328 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
15328 |
GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8] |
| 15329 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
15329 |
GIM_CheckOpcode, /*MI*/8, TargetOpcode::G_CONSTANT, |
| 15330 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15330 |
GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15331 |
// MIs[8] Operand 1 |
15331 |
// MIs[8] Operand 1 |
| 15332 |
// No operand predicates |
15332 |
// No operand predicates |
| 15333 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
15333 |
GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9] |
| 15334 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
15334 |
GIM_CheckOpcode, /*MI*/9, TargetOpcode::G_CONSTANT, |
| 15335 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15335 |
GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15336 |
// MIs[9] Operand 1 |
15336 |
// MIs[9] Operand 1 |
| 15337 |
// No operand predicates |
15337 |
// No operand predicates |
| 15338 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
15338 |
GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10] |
| 15339 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
15339 |
GIM_CheckOpcode, /*MI*/10, TargetOpcode::G_CONSTANT, |
| 15340 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15340 |
GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15341 |
// MIs[10] Operand 1 |
15341 |
// MIs[10] Operand 1 |
| 15342 |
// No operand predicates |
15342 |
// No operand predicates |
| 15343 |
GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11] |
15343 |
GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11] |
| 15344 |
GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT, |
15344 |
GIM_CheckOpcode, /*MI*/11, TargetOpcode::G_CONSTANT, |
| 15345 |
GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15345 |
GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15346 |
// MIs[11] Operand 1 |
15346 |
// MIs[11] Operand 1 |
| 15347 |
// No operand predicates |
15347 |
// No operand predicates |
| 15348 |
GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12] |
15348 |
GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12] |
| 15349 |
GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT, |
15349 |
GIM_CheckOpcode, /*MI*/12, TargetOpcode::G_CONSTANT, |
| 15350 |
GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15350 |
GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15351 |
// MIs[12] Operand 1 |
15351 |
// MIs[12] Operand 1 |
| 15352 |
// No operand predicates |
15352 |
// No operand predicates |
| 15353 |
GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13] |
15353 |
GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13] |
| 15354 |
GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT, |
15354 |
GIM_CheckOpcode, /*MI*/13, TargetOpcode::G_CONSTANT, |
| 15355 |
GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15355 |
GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15356 |
// MIs[13] Operand 1 |
15356 |
// MIs[13] Operand 1 |
| 15357 |
// No operand predicates |
15357 |
// No operand predicates |
| 15358 |
GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14] |
15358 |
GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14] |
| 15359 |
GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT, |
15359 |
GIM_CheckOpcode, /*MI*/14, TargetOpcode::G_CONSTANT, |
| 15360 |
GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15360 |
GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15361 |
// MIs[14] Operand 1 |
15361 |
// MIs[14] Operand 1 |
| 15362 |
// No operand predicates |
15362 |
// No operand predicates |
| 15363 |
GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15] |
15363 |
GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15] |
| 15364 |
GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT, |
15364 |
GIM_CheckOpcode, /*MI*/15, TargetOpcode::G_CONSTANT, |
| 15365 |
GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15365 |
GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15366 |
// MIs[15] Operand 1 |
15366 |
// MIs[15] Operand 1 |
| 15367 |
// No operand predicates |
15367 |
// No operand predicates |
| 15368 |
GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16] |
15368 |
GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16] |
| 15369 |
GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT, |
15369 |
GIM_CheckOpcode, /*MI*/16, TargetOpcode::G_CONSTANT, |
| 15370 |
GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15370 |
GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15371 |
// MIs[16] Operand 1 |
15371 |
// MIs[16] Operand 1 |
| 15372 |
// No operand predicates |
15372 |
// No operand predicates |
| 15373 |
GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17] |
15373 |
GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17] |
| 15374 |
GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT, |
15374 |
GIM_CheckOpcode, /*MI*/17, TargetOpcode::G_CONSTANT, |
| 15375 |
GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15375 |
GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15376 |
// MIs[17] Operand 1 |
15376 |
// MIs[17] Operand 1 |
| 15377 |
// No operand predicates |
15377 |
// No operand predicates |
| 15378 |
GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18] |
15378 |
GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18] |
| 15379 |
GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT, |
15379 |
GIM_CheckOpcode, /*MI*/18, TargetOpcode::G_CONSTANT, |
| 15380 |
GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
15380 |
GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GICXXPred_I64_Predicate_immi32Cst7, |
| 15381 |
// MIs[18] Operand 1 |
15381 |
// MIs[18] Operand 1 |
| 15382 |
// No operand predicates |
15382 |
// No operand predicates |
| 15383 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
15383 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15384 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
15384 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 15385 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
15385 |
GIM_CheckIsSafeToFold, /*InsnID*/3, |
| 15386 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
15386 |
GIM_CheckIsSafeToFold, /*InsnID*/4, |
| 15387 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
15387 |
GIM_CheckIsSafeToFold, /*InsnID*/5, |
| 15388 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
15388 |
GIM_CheckIsSafeToFold, /*InsnID*/6, |
| 15389 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
15389 |
GIM_CheckIsSafeToFold, /*InsnID*/7, |
| 15390 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
15390 |
GIM_CheckIsSafeToFold, /*InsnID*/8, |
| 15391 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
15391 |
GIM_CheckIsSafeToFold, /*InsnID*/9, |
| 15392 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
15392 |
GIM_CheckIsSafeToFold, /*InsnID*/10, |
| 15393 |
GIM_CheckIsSafeToFold, /*InsnID*/11, |
15393 |
GIM_CheckIsSafeToFold, /*InsnID*/11, |
| 15394 |
GIM_CheckIsSafeToFold, /*InsnID*/12, |
15394 |
GIM_CheckIsSafeToFold, /*InsnID*/12, |
| 15395 |
GIM_CheckIsSafeToFold, /*InsnID*/13, |
15395 |
GIM_CheckIsSafeToFold, /*InsnID*/13, |
| 15396 |
GIM_CheckIsSafeToFold, /*InsnID*/14, |
15396 |
GIM_CheckIsSafeToFold, /*InsnID*/14, |
| 15397 |
GIM_CheckIsSafeToFold, /*InsnID*/15, |
15397 |
GIM_CheckIsSafeToFold, /*InsnID*/15, |
| 15398 |
GIM_CheckIsSafeToFold, /*InsnID*/16, |
15398 |
GIM_CheckIsSafeToFold, /*InsnID*/16, |
| 15399 |
GIM_CheckIsSafeToFold, /*InsnID*/17, |
15399 |
GIM_CheckIsSafeToFold, /*InsnID*/17, |
| 15400 |
GIM_CheckIsSafeToFold, /*InsnID*/18, |
15400 |
GIM_CheckIsSafeToFold, /*InsnID*/18, |
| 15401 |
// (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt) |
15401 |
// (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>, (imm:{ *:[i32] })<>))) => (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt) |
| 15402 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_B, |
15402 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_B, |
| 15403 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
15403 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 15404 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
15404 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 15405 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
15405 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
| 15406 |
GIR_EraseFromParent, /*InsnID*/0, |
15406 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15407 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15407 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15408 |
// GIR_Coverage, 2041, |
15408 |
// GIR_Coverage, 2041, |
| 15409 |
GIR_Done, |
15409 |
GIR_Done, |
| 15410 |
// Label 935: @37313 |
15410 |
// Label 935: @37313 |
| 15411 |
GIM_Try, /*On fail goto*//*Label 936*/ 37332, // Rule ID 961 // |
15411 |
GIM_Try, /*On fail goto*//*Label 936*/ 37332, // Rule ID 961 // |
| 15412 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
15412 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 15413 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
15413 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 15414 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
15414 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 15415 |
// (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
15415 |
// (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 15416 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_B, |
15416 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_B, |
| 15417 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15417 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15418 |
// GIR_Coverage, 961, |
15418 |
// GIR_Coverage, 961, |
| 15419 |
GIR_Done, |
15419 |
GIR_Done, |
| 15420 |
// Label 936: @37332 |
15420 |
// Label 936: @37332 |
| 15421 |
GIM_Reject, |
15421 |
GIM_Reject, |
| 15422 |
// Label 933: @37333 |
15422 |
// Label 933: @37333 |
| 15423 |
GIM_Reject, |
15423 |
GIM_Reject, |
| 15424 |
// Label 912: @37334 |
15424 |
// Label 912: @37334 |
| 15425 |
GIM_Reject, |
15425 |
GIM_Reject, |
| 15426 |
// Label 26: @37335 |
15426 |
// Label 26: @37335 |
| 15427 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 939*/ 37597, |
15427 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 939*/ 37597, |
| 15428 |
/*GILLT_s32*//*Label 937*/ 37343, |
15428 |
/*GILLT_s32*//*Label 937*/ 37343, |
| 15429 |
/*GILLT_s64*//*Label 938*/ 37463, |
15429 |
/*GILLT_s64*//*Label 938*/ 37463, |
| 15430 |
// Label 937: @37343 |
15430 |
// Label 937: @37343 |
| 15431 |
GIM_Try, /*On fail goto*//*Label 940*/ 37462, |
15431 |
GIM_Try, /*On fail goto*//*Label 940*/ 37462, |
| 15432 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
15432 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 15433 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
15433 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 15434 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
15434 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 15435 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
15435 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 15436 |
GIM_Try, /*On fail goto*//*Label 941*/ 37396, // Rule ID 61 // |
15436 |
GIM_Try, /*On fail goto*//*Label 941*/ 37396, // Rule ID 61 // |
| 15437 |
GIM_CheckFeatures, GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips, |
15437 |
GIM_CheckFeatures, GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips, |
| 15438 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
15438 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15439 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
15439 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 15440 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
15440 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 15441 |
// MIs[1] Operand 1 |
15441 |
// MIs[1] Operand 1 |
| 15442 |
// No operand predicates |
15442 |
// No operand predicates |
| 15443 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
15443 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15444 |
// (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (ROTR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt) |
15444 |
// (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (ROTR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt) |
| 15445 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR, |
15445 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR, |
| 15446 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15446 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15447 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
15447 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 15448 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
15448 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 15449 |
GIR_EraseFromParent, /*InsnID*/0, |
15449 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15450 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15450 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15451 |
// GIR_Coverage, 61, |
15451 |
// GIR_Coverage, 61, |
| 15452 |
GIR_Done, |
15452 |
GIR_Done, |
| 15453 |
// Label 941: @37396 |
15453 |
// Label 941: @37396 |
| 15454 |
GIM_Try, /*On fail goto*//*Label 942*/ 37431, // Rule ID 1069 // |
15454 |
GIM_Try, /*On fail goto*//*Label 942*/ 37431, // Rule ID 1069 // |
| 15455 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
15455 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 15456 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
15456 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15457 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
15457 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 15458 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
15458 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt5, |
| 15459 |
// MIs[1] Operand 1 |
15459 |
// MIs[1] Operand 1 |
| 15460 |
// No operand predicates |
15460 |
// No operand predicates |
| 15461 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
15461 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15462 |
// (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (ROTR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt) |
15462 |
// (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (ROTR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt) |
| 15463 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR_MM, |
15463 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR_MM, |
| 15464 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15464 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15465 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
15465 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 15466 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
15466 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 15467 |
GIR_EraseFromParent, /*InsnID*/0, |
15467 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15468 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15468 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15469 |
// GIR_Coverage, 1069, |
15469 |
// GIR_Coverage, 1069, |
| 15470 |
GIR_Done, |
15470 |
GIR_Done, |
| 15471 |
// Label 942: @37431 |
15471 |
// Label 942: @37431 |
| 15472 |
GIM_Try, /*On fail goto*//*Label 943*/ 37446, // Rule ID 62 // |
15472 |
GIM_Try, /*On fail goto*//*Label 943*/ 37446, // Rule ID 62 // |
| 15473 |
GIM_CheckFeatures, GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips, |
15473 |
GIM_CheckFeatures, GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips, |
| 15474 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15474 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15475 |
// (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
15475 |
// (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 15476 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ROTRV, |
15476 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ROTRV, |
| 15477 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15477 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15478 |
// GIR_Coverage, 62, |
15478 |
// GIR_Coverage, 62, |
| 15479 |
GIR_Done, |
15479 |
GIR_Done, |
| 15480 |
// Label 943: @37446 |
15480 |
// Label 943: @37446 |
| 15481 |
GIM_Try, /*On fail goto*//*Label 944*/ 37461, // Rule ID 1070 // |
15481 |
GIM_Try, /*On fail goto*//*Label 944*/ 37461, // Rule ID 1070 // |
| 15482 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
15482 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 15483 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15483 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15484 |
// (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
15484 |
// (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (ROTRV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 15485 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ROTRV_MM, |
15485 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ROTRV_MM, |
| 15486 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15486 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15487 |
// GIR_Coverage, 1070, |
15487 |
// GIR_Coverage, 1070, |
| 15488 |
GIR_Done, |
15488 |
GIR_Done, |
| 15489 |
// Label 944: @37461 |
15489 |
// Label 944: @37461 |
| 15490 |
GIM_Reject, |
15490 |
GIM_Reject, |
| 15491 |
// Label 940: @37462 |
15491 |
// Label 940: @37462 |
| 15492 |
GIM_Reject, |
15492 |
GIM_Reject, |
| 15493 |
// Label 938: @37463 |
15493 |
// Label 938: @37463 |
| 15494 |
GIM_Try, /*On fail goto*//*Label 945*/ 37596, |
15494 |
GIM_Try, /*On fail goto*//*Label 945*/ 37596, |
| 15495 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
15495 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 15496 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
15496 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 15497 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
15497 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 15498 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
15498 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 15499 |
GIM_Try, /*On fail goto*//*Label 946*/ 37516, // Rule ID 210 // |
15499 |
GIM_Try, /*On fail goto*//*Label 946*/ 37516, // Rule ID 210 // |
| 15500 |
GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips, |
15500 |
GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips, |
| 15501 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
15501 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15502 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
15502 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 15503 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt6, |
15503 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt6, |
| 15504 |
// MIs[1] Operand 1 |
15504 |
// MIs[1] Operand 1 |
| 15505 |
// No operand predicates |
15505 |
// No operand predicates |
| 15506 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
15506 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15507 |
// (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (DROTR:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt) |
15507 |
// (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<>:$shamt) => (DROTR:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt) |
| 15508 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DROTR, |
15508 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DROTR, |
| 15509 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15509 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15510 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
15510 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 15511 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
15511 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt |
| 15512 |
GIR_EraseFromParent, /*InsnID*/0, |
15512 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15513 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15513 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15514 |
// GIR_Coverage, 210, |
15514 |
// GIR_Coverage, 210, |
| 15515 |
GIR_Done, |
15515 |
GIR_Done, |
| 15516 |
// Label 946: @37516 |
15516 |
// Label 946: @37516 |
| 15517 |
GIM_Try, /*On fail goto*//*Label 947*/ 37580, // Rule ID 1565 // |
15517 |
GIM_Try, /*On fail goto*//*Label 947*/ 37580, // Rule ID 1565 // |
| 15518 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
15518 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit, |
| 15519 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
15519 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 15520 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
15520 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, |
| 15521 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
15521 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 15522 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
15522 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 15523 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
15523 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 15524 |
// (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DROTRV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] })) |
15524 |
// (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DROTRV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] })) |
| 15525 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
15525 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15526 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
15526 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, |
| 15527 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
15527 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 15528 |
GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs |
15528 |
GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs |
| 15529 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::GPR32RegClassID, |
15529 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Mips::GPR32RegClassID, |
| 15530 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID, |
15530 |
GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Mips::GPR64RegClassID, |
| 15531 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DROTRV, |
15531 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DROTRV, |
| 15532 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15532 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15533 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
15533 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 15534 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
15534 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 15535 |
GIR_EraseFromParent, /*InsnID*/0, |
15535 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15536 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15536 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15537 |
// GIR_Coverage, 1565, |
15537 |
// GIR_Coverage, 1565, |
| 15538 |
GIR_Done, |
15538 |
GIR_Done, |
| 15539 |
// Label 947: @37580 |
15539 |
// Label 947: @37580 |
| 15540 |
GIM_Try, /*On fail goto*//*Label 948*/ 37595, // Rule ID 211 // |
15540 |
GIM_Try, /*On fail goto*//*Label 948*/ 37595, // Rule ID 211 // |
| 15541 |
GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips, |
15541 |
GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips, |
| 15542 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15542 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15543 |
// (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DROTRV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
15543 |
// (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DROTRV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) |
| 15544 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DROTRV, |
15544 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DROTRV, |
| 15545 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15545 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15546 |
// GIR_Coverage, 211, |
15546 |
// GIR_Coverage, 211, |
| 15547 |
GIR_Done, |
15547 |
GIR_Done, |
| 15548 |
// Label 948: @37595 |
15548 |
// Label 948: @37595 |
| 15549 |
GIM_Reject, |
15549 |
GIM_Reject, |
| 15550 |
// Label 945: @37596 |
15550 |
// Label 945: @37596 |
| 15551 |
GIM_Reject, |
15551 |
GIM_Reject, |
| 15552 |
// Label 939: @37597 |
15552 |
// Label 939: @37597 |
| 15553 |
GIM_Reject, |
15553 |
GIM_Reject, |
| 15554 |
// Label 27: @37598 |
15554 |
// Label 27: @37598 |
| 15555 |
GIM_Try, /*On fail goto*//*Label 949*/ 40101, |
15555 |
GIM_Try, /*On fail goto*//*Label 949*/ 40101, |
| 15556 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
15556 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 15557 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 952*/ 37778, |
15557 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 952*/ 37778, |
| 15558 |
/*GILLT_s32*//*Label 950*/ 37612, |
15558 |
/*GILLT_s32*//*Label 950*/ 37612, |
| 15559 |
/*GILLT_s64*//*Label 951*/ 37695, |
15559 |
/*GILLT_s64*//*Label 951*/ 37695, |
| 15560 |
// Label 950: @37612 |
15560 |
// Label 950: @37612 |
| 15561 |
GIM_Try, /*On fail goto*//*Label 953*/ 37694, |
15561 |
GIM_Try, /*On fail goto*//*Label 953*/ 37694, |
| 15562 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
15562 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 15563 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
15563 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 15564 |
GIM_Try, /*On fail goto*//*Label 954*/ 37657, // Rule ID 1403 // |
15564 |
GIM_Try, /*On fail goto*//*Label 954*/ 37657, // Rule ID 1403 // |
| 15565 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
15565 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 15566 |
// MIs[0] Operand 1 |
15566 |
// MIs[0] Operand 1 |
| 15567 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
15567 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 15568 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15568 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15569 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
15569 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
| 15570 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] }) |
15570 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] }) |
| 15571 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu, |
15571 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu, |
| 15572 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
15572 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 15573 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15573 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15574 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
15574 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 15575 |
GIR_EraseFromParent, /*InsnID*/0, |
15575 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15576 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15576 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15577 |
// GIR_Coverage, 1403, |
15577 |
// GIR_Coverage, 1403, |
| 15578 |
GIR_Done, |
15578 |
GIR_Done, |
| 15579 |
// Label 954: @37657 |
15579 |
// Label 954: @37657 |
| 15580 |
GIM_Try, /*On fail goto*//*Label 955*/ 37693, // Rule ID 1404 // |
15580 |
GIM_Try, /*On fail goto*//*Label 955*/ 37693, // Rule ID 1404 // |
| 15581 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
15581 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 15582 |
// MIs[0] Operand 1 |
15582 |
// MIs[0] Operand 1 |
| 15583 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
15583 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 15584 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15584 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15585 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
15585 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
| 15586 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs) |
15586 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs) |
| 15587 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu, |
15587 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu, |
| 15588 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15588 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15589 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
15589 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 15590 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15590 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15591 |
GIR_EraseFromParent, /*InsnID*/0, |
15591 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15592 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15592 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15593 |
// GIR_Coverage, 1404, |
15593 |
// GIR_Coverage, 1404, |
| 15594 |
GIR_Done, |
15594 |
GIR_Done, |
| 15595 |
// Label 955: @37693 |
15595 |
// Label 955: @37693 |
| 15596 |
GIM_Reject, |
15596 |
GIM_Reject, |
| 15597 |
// Label 953: @37694 |
15597 |
// Label 953: @37694 |
| 15598 |
GIM_Reject, |
15598 |
GIM_Reject, |
| 15599 |
// Label 951: @37695 |
15599 |
// Label 951: @37695 |
| 15600 |
GIM_Try, /*On fail goto*//*Label 956*/ 37777, |
15600 |
GIM_Try, /*On fail goto*//*Label 956*/ 37777, |
| 15601 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
15601 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 15602 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
15602 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 15603 |
GIM_Try, /*On fail goto*//*Label 957*/ 37740, // Rule ID 1547 // |
15603 |
GIM_Try, /*On fail goto*//*Label 957*/ 37740, // Rule ID 1547 // |
| 15604 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
15604 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
| 15605 |
// MIs[0] Operand 1 |
15605 |
// MIs[0] Operand 1 |
| 15606 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
15606 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 15607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
15607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 15608 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
15608 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
| 15609 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 1:{ *:[i64] }) |
15609 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 1:{ *:[i64] }) |
| 15610 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu64, |
15610 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu64, |
| 15611 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
15611 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 15612 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15612 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15613 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
15613 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 15614 |
GIR_EraseFromParent, /*InsnID*/0, |
15614 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15615 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15615 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15616 |
// GIR_Coverage, 1547, |
15616 |
// GIR_Coverage, 1547, |
| 15617 |
GIR_Done, |
15617 |
GIR_Done, |
| 15618 |
// Label 957: @37740 |
15618 |
// Label 957: @37740 |
| 15619 |
GIM_Try, /*On fail goto*//*Label 958*/ 37776, // Rule ID 1548 // |
15619 |
GIM_Try, /*On fail goto*//*Label 958*/ 37776, // Rule ID 1548 // |
| 15620 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
15620 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
| 15621 |
// MIs[0] Operand 1 |
15621 |
// MIs[0] Operand 1 |
| 15622 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
15622 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 15623 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
15623 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 15624 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
15624 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
| 15625 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, GPR64:{ *:[i64] }:$lhs) |
15625 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, GPR64:{ *:[i64] }:$lhs) |
| 15626 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64, |
15626 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64, |
| 15627 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15627 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15628 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO_64, /*AddRegisterRegFlags*/0, |
15628 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO_64, /*AddRegisterRegFlags*/0, |
| 15629 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15629 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15630 |
GIR_EraseFromParent, /*InsnID*/0, |
15630 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15631 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15631 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15632 |
// GIR_Coverage, 1548, |
15632 |
// GIR_Coverage, 1548, |
| 15633 |
GIR_Done, |
15633 |
GIR_Done, |
| 15634 |
// Label 958: @37776 |
15634 |
// Label 958: @37776 |
| 15635 |
GIM_Reject, |
15635 |
GIM_Reject, |
| 15636 |
// Label 956: @37777 |
15636 |
// Label 956: @37777 |
| 15637 |
GIM_Reject, |
15637 |
GIM_Reject, |
| 15638 |
// Label 952: @37778 |
15638 |
// Label 952: @37778 |
| 15639 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 961*/ 38150, |
15639 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 961*/ 38150, |
| 15640 |
/*GILLT_s32*//*Label 959*/ 37786, |
15640 |
/*GILLT_s32*//*Label 959*/ 37786, |
| 15641 |
/*GILLT_s64*//*Label 960*/ 38066, |
15641 |
/*GILLT_s64*//*Label 960*/ 38066, |
| 15642 |
// Label 959: @37786 |
15642 |
// Label 959: @37786 |
| 15643 |
GIM_Try, /*On fail goto*//*Label 962*/ 38065, |
15643 |
GIM_Try, /*On fail goto*//*Label 962*/ 38065, |
| 15644 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
15644 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 15645 |
GIM_Try, /*On fail goto*//*Label 963*/ 37831, // Rule ID 1843 // |
15645 |
GIM_Try, /*On fail goto*//*Label 963*/ 37831, // Rule ID 1843 // |
| 15646 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
15646 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 15647 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
15647 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 15648 |
// MIs[0] Operand 1 |
15648 |
// MIs[0] Operand 1 |
| 15649 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
15649 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 15650 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
15650 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 15651 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
15651 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
| 15652 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 1:{ *:[i32] }) |
15652 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 1:{ *:[i32] }) |
| 15653 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltiuCCRxImmX16, |
15653 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltiuCCRxImmX16, |
| 15654 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
15654 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
| 15655 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15655 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15656 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
15656 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 15657 |
GIR_EraseFromParent, /*InsnID*/0, |
15657 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15658 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15658 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15659 |
// GIR_Coverage, 1843, |
15659 |
// GIR_Coverage, 1843, |
| 15660 |
GIR_Done, |
15660 |
GIR_Done, |
| 15661 |
// Label 963: @37831 |
15661 |
// Label 963: @37831 |
| 15662 |
GIM_Try, /*On fail goto*//*Label 964*/ 37905, // Rule ID 1845 // |
15662 |
GIM_Try, /*On fail goto*//*Label 964*/ 37905, // Rule ID 1845 // |
| 15663 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
15663 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 15664 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
15664 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 15665 |
// MIs[0] Operand 1 |
15665 |
// MIs[0] Operand 1 |
| 15666 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, |
15666 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, |
| 15667 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
15667 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 15668 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, -32769, |
15668 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, -32769, |
| 15669 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32769:{ *:[i32] }, SETGT:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltiCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32768:{ *:[i32] }), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] })) |
15669 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32769:{ *:[i32] }, SETGT:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltiCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32768:{ *:[i32] }), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] })) |
| 15670 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
15670 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15671 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
15671 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 15672 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16, |
15672 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16, |
| 15673 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
15673 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 15674 |
GIR_AddImm, /*InsnID*/2, /*Imm*/1, |
15674 |
GIR_AddImm, /*InsnID*/2, /*Imm*/1, |
| 15675 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
15675 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 15676 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltiCCRxImmX16, |
15676 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltiCCRxImmX16, |
| 15677 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
15677 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 15678 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15678 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15679 |
GIR_AddImm, /*InsnID*/1, /*Imm*/-32768, |
15679 |
GIR_AddImm, /*InsnID*/1, /*Imm*/-32768, |
| 15680 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
15680 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15681 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16, |
15681 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16, |
| 15682 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz |
15682 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz |
| 15683 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
15683 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 15684 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
15684 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 15685 |
GIR_EraseFromParent, /*InsnID*/0, |
15685 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15686 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15686 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15687 |
// GIR_Coverage, 1845, |
15687 |
// GIR_Coverage, 1845, |
| 15688 |
GIR_Done, |
15688 |
GIR_Done, |
| 15689 |
// Label 964: @37905 |
15689 |
// Label 964: @37905 |
| 15690 |
GIM_Try, /*On fail goto*//*Label 965*/ 37944, // Rule ID 2162 // |
15690 |
GIM_Try, /*On fail goto*//*Label 965*/ 37944, // Rule ID 2162 // |
| 15691 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
15691 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 15692 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
15692 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 15693 |
// MIs[0] Operand 1 |
15693 |
// MIs[0] Operand 1 |
| 15694 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
15694 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 15695 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15695 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15696 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
15696 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
| 15697 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] }) |
15697 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] }) |
| 15698 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu_MM, |
15698 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu_MM, |
| 15699 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
15699 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 15700 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15700 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15701 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
15701 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 15702 |
GIR_EraseFromParent, /*InsnID*/0, |
15702 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15703 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15703 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15704 |
// GIR_Coverage, 2162, |
15704 |
// GIR_Coverage, 2162, |
| 15705 |
GIR_Done, |
15705 |
GIR_Done, |
| 15706 |
// Label 965: @37944 |
15706 |
// Label 965: @37944 |
| 15707 |
GIM_Try, /*On fail goto*//*Label 966*/ 37984, // Rule ID 2163 // |
15707 |
GIM_Try, /*On fail goto*//*Label 966*/ 37984, // Rule ID 2163 // |
| 15708 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
15708 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 15709 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
15709 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 15710 |
// MIs[0] Operand 1 |
15710 |
// MIs[0] Operand 1 |
| 15711 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
15711 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 15712 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15712 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15713 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
15713 |
GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, |
| 15714 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs) |
15714 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs) |
| 15715 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM, |
15715 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM, |
| 15716 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15716 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15717 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
15717 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 15718 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15718 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15719 |
GIR_EraseFromParent, /*InsnID*/0, |
15719 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15720 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15720 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15721 |
// GIR_Coverage, 2163, |
15721 |
// GIR_Coverage, 2163, |
| 15722 |
GIR_Done, |
15722 |
GIR_Done, |
| 15723 |
// Label 966: @37984 |
15723 |
// Label 966: @37984 |
| 15724 |
GIM_Try, /*On fail goto*//*Label 967*/ 38024, // Rule ID 49 // |
15724 |
GIM_Try, /*On fail goto*//*Label 967*/ 38024, // Rule ID 49 // |
| 15725 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
15725 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 15726 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
15726 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 15727 |
// MIs[0] Operand 1 |
15727 |
// MIs[0] Operand 1 |
| 15728 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, |
15728 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, |
| 15729 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15729 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15730 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
15730 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 15731 |
// (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
15731 |
// (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 15732 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT, |
15732 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT, |
| 15733 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15733 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15734 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
15734 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 15735 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
15735 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 15736 |
GIR_EraseFromParent, /*InsnID*/0, |
15736 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15737 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15737 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15738 |
// GIR_Coverage, 49, |
15738 |
// GIR_Coverage, 49, |
| 15739 |
GIR_Done, |
15739 |
GIR_Done, |
| 15740 |
// Label 967: @38024 |
15740 |
// Label 967: @38024 |
| 15741 |
GIM_Try, /*On fail goto*//*Label 968*/ 38064, // Rule ID 50 // |
15741 |
GIM_Try, /*On fail goto*//*Label 968*/ 38064, // Rule ID 50 // |
| 15742 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
15742 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 15743 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
15743 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 15744 |
// MIs[0] Operand 1 |
15744 |
// MIs[0] Operand 1 |
| 15745 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, |
15745 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, |
| 15746 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15746 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15747 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
15747 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 15748 |
// (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
15748 |
// (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 15749 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu, |
15749 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu, |
| 15750 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15750 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15751 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
15751 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 15752 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
15752 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 15753 |
GIR_EraseFromParent, /*InsnID*/0, |
15753 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15754 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15754 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15755 |
// GIR_Coverage, 50, |
15755 |
// GIR_Coverage, 50, |
| 15756 |
GIR_Done, |
15756 |
GIR_Done, |
| 15757 |
// Label 968: @38064 |
15757 |
// Label 968: @38064 |
| 15758 |
GIM_Reject, |
15758 |
GIM_Reject, |
| 15759 |
// Label 962: @38065 |
15759 |
// Label 962: @38065 |
| 15760 |
GIM_Reject, |
15760 |
GIM_Reject, |
| 15761 |
// Label 960: @38066 |
15761 |
// Label 960: @38066 |
| 15762 |
GIM_Try, /*On fail goto*//*Label 969*/ 38149, |
15762 |
GIM_Try, /*On fail goto*//*Label 969*/ 38149, |
| 15763 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
15763 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 15764 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
15764 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 15765 |
GIM_Try, /*On fail goto*//*Label 970*/ 38112, // Rule ID 198 // |
15765 |
GIM_Try, /*On fail goto*//*Label 970*/ 38112, // Rule ID 198 // |
| 15766 |
GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, |
15766 |
GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, |
| 15767 |
// MIs[0] Operand 1 |
15767 |
// MIs[0] Operand 1 |
| 15768 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, |
15768 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, |
| 15769 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
15769 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 15770 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
15770 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 15771 |
// (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETLT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
15771 |
// (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETLT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 15772 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT64, |
15772 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT64, |
| 15773 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15773 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15774 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
15774 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 15775 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
15775 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 15776 |
GIR_EraseFromParent, /*InsnID*/0, |
15776 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15777 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15777 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15778 |
// GIR_Coverage, 198, |
15778 |
// GIR_Coverage, 198, |
| 15779 |
GIR_Done, |
15779 |
GIR_Done, |
| 15780 |
// Label 970: @38112 |
15780 |
// Label 970: @38112 |
| 15781 |
GIM_Try, /*On fail goto*//*Label 971*/ 38148, // Rule ID 199 // |
15781 |
GIM_Try, /*On fail goto*//*Label 971*/ 38148, // Rule ID 199 // |
| 15782 |
GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, |
15782 |
GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode, |
| 15783 |
// MIs[0] Operand 1 |
15783 |
// MIs[0] Operand 1 |
| 15784 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, |
15784 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, |
| 15785 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
15785 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 15786 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
15786 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 15787 |
// (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETULT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
15787 |
// (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETULT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 15788 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64, |
15788 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64, |
| 15789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15790 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
15790 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 15791 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
15791 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 15792 |
GIR_EraseFromParent, /*InsnID*/0, |
15792 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15793 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15793 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15794 |
// GIR_Coverage, 199, |
15794 |
// GIR_Coverage, 199, |
| 15795 |
GIR_Done, |
15795 |
GIR_Done, |
| 15796 |
// Label 971: @38148 |
15796 |
// Label 971: @38148 |
| 15797 |
GIM_Reject, |
15797 |
GIM_Reject, |
| 15798 |
// Label 969: @38149 |
15798 |
// Label 969: @38149 |
| 15799 |
GIM_Reject, |
15799 |
GIM_Reject, |
| 15800 |
// Label 961: @38150 |
15800 |
// Label 961: @38150 |
| 15801 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 974*/ 39060, |
15801 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 974*/ 39060, |
| 15802 |
/*GILLT_s32*//*Label 972*/ 38158, |
15802 |
/*GILLT_s32*//*Label 972*/ 38158, |
| 15803 |
/*GILLT_s64*//*Label 973*/ 38645, |
15803 |
/*GILLT_s64*//*Label 973*/ 38645, |
| 15804 |
// Label 972: @38158 |
15804 |
// Label 972: @38158 |
| 15805 |
GIM_Try, /*On fail goto*//*Label 975*/ 38644, |
15805 |
GIM_Try, /*On fail goto*//*Label 975*/ 38644, |
| 15806 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
15806 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 15807 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
15807 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 15808 |
GIM_Try, /*On fail goto*//*Label 976*/ 38204, // Rule ID 1063 // |
15808 |
GIM_Try, /*On fail goto*//*Label 976*/ 38204, // Rule ID 1063 // |
| 15809 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
15809 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 15810 |
// MIs[0] Operand 1 |
15810 |
// MIs[0] Operand 1 |
| 15811 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, |
15811 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, |
| 15812 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15812 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15813 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
15813 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 15814 |
// (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
15814 |
// (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 15815 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT_MM, |
15815 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT_MM, |
| 15816 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15816 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15817 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
15817 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 15818 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
15818 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 15819 |
GIR_EraseFromParent, /*InsnID*/0, |
15819 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15820 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15820 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15821 |
// GIR_Coverage, 1063, |
15821 |
// GIR_Coverage, 1063, |
| 15822 |
GIR_Done, |
15822 |
GIR_Done, |
| 15823 |
// Label 976: @38204 |
15823 |
// Label 976: @38204 |
| 15824 |
GIM_Try, /*On fail goto*//*Label 977*/ 38240, // Rule ID 1064 // |
15824 |
GIM_Try, /*On fail goto*//*Label 977*/ 38240, // Rule ID 1064 // |
| 15825 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
15825 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 15826 |
// MIs[0] Operand 1 |
15826 |
// MIs[0] Operand 1 |
| 15827 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, |
15827 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, |
| 15828 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15828 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15829 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
15829 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 15830 |
// (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
15830 |
// (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 15831 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM, |
15831 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM, |
| 15832 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15832 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15833 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
15833 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs |
| 15834 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
15834 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt |
| 15835 |
GIR_EraseFromParent, /*InsnID*/0, |
15835 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15836 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15836 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15837 |
// GIR_Coverage, 1064, |
15837 |
// GIR_Coverage, 1064, |
| 15838 |
GIR_Done, |
15838 |
GIR_Done, |
| 15839 |
// Label 977: @38240 |
15839 |
// Label 977: @38240 |
| 15840 |
GIM_Try, /*On fail goto*//*Label 978*/ 38295, // Rule ID 1405 // |
15840 |
GIM_Try, /*On fail goto*//*Label 978*/ 38295, // Rule ID 1405 // |
| 15841 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
15841 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 15842 |
// MIs[0] Operand 1 |
15842 |
// MIs[0] Operand 1 |
| 15843 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
15843 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 15844 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15844 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15845 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
15845 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 15846 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
15846 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu:{ *:[i32] } (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
| 15847 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
15847 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15848 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
15848 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
| 15849 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
15849 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 15850 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15850 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15851 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
15851 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 15852 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
15852 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15853 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu, |
15853 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu, |
| 15854 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
15854 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 15855 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
15855 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 15856 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
15856 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 15857 |
GIR_EraseFromParent, /*InsnID*/0, |
15857 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15858 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15858 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15859 |
// GIR_Coverage, 1405, |
15859 |
// GIR_Coverage, 1405, |
| 15860 |
GIR_Done, |
15860 |
GIR_Done, |
| 15861 |
// Label 978: @38295 |
15861 |
// Label 978: @38295 |
| 15862 |
GIM_Try, /*On fail goto*//*Label 979*/ 38351, // Rule ID 1406 // |
15862 |
GIM_Try, /*On fail goto*//*Label 979*/ 38351, // Rule ID 1406 // |
| 15863 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
15863 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 15864 |
// MIs[0] Operand 1 |
15864 |
// MIs[0] Operand 1 |
| 15865 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
15865 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 15866 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15866 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15867 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
15867 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 15868 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)) |
15868 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)) |
| 15869 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
15869 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15870 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
15870 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
| 15871 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
15871 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 15872 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15872 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15873 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
15873 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 15874 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
15874 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15875 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu, |
15875 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu, |
| 15876 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15876 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15877 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
15877 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 15878 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
15878 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 15879 |
GIR_EraseFromParent, /*InsnID*/0, |
15879 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15880 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15880 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15881 |
// GIR_Coverage, 1406, |
15881 |
// GIR_Coverage, 1406, |
| 15882 |
GIR_Done, |
15882 |
GIR_Done, |
| 15883 |
// Label 979: @38351 |
15883 |
// Label 979: @38351 |
| 15884 |
GIM_Try, /*On fail goto*//*Label 980*/ 38406, // Rule ID 1407 // |
15884 |
GIM_Try, /*On fail goto*//*Label 980*/ 38406, // Rule ID 1407 // |
| 15885 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
15885 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 15886 |
// MIs[0] Operand 1 |
15886 |
// MIs[0] Operand 1 |
| 15887 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
15887 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 15888 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15888 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15889 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
15889 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 15890 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] }) |
15890 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] }) |
| 15891 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
15891 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15892 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
15892 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
| 15893 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
15893 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 15894 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
15894 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 15895 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15895 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15896 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
15896 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15897 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
15897 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
| 15898 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
15898 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 15899 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
15899 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 15900 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
15900 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 15901 |
GIR_EraseFromParent, /*InsnID*/0, |
15901 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15902 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15902 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15903 |
// GIR_Coverage, 1407, |
15903 |
// GIR_Coverage, 1407, |
| 15904 |
GIR_Done, |
15904 |
GIR_Done, |
| 15905 |
// Label 980: @38406 |
15905 |
// Label 980: @38406 |
| 15906 |
GIM_Try, /*On fail goto*//*Label 981*/ 38461, // Rule ID 1408 // |
15906 |
GIM_Try, /*On fail goto*//*Label 981*/ 38461, // Rule ID 1408 // |
| 15907 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
15907 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 15908 |
// MIs[0] Operand 1 |
15908 |
// MIs[0] Operand 1 |
| 15909 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
15909 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 15910 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15910 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15911 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
15911 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 15912 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] }) |
15912 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] }) |
| 15913 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
15913 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15914 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
15914 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
| 15915 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
15915 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 15916 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
15916 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 15917 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15917 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15918 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
15918 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15919 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
15919 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
| 15920 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
15920 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 15921 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
15921 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 15922 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
15922 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 15923 |
GIR_EraseFromParent, /*InsnID*/0, |
15923 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15924 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15924 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15925 |
// GIR_Coverage, 1408, |
15925 |
// GIR_Coverage, 1408, |
| 15926 |
GIR_Done, |
15926 |
GIR_Done, |
| 15927 |
// Label 981: @38461 |
15927 |
// Label 981: @38461 |
| 15928 |
GIM_Try, /*On fail goto*//*Label 982*/ 38497, // Rule ID 1409 // |
15928 |
GIM_Try, /*On fail goto*//*Label 982*/ 38497, // Rule ID 1409 // |
| 15929 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
15929 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 15930 |
// MIs[0] Operand 1 |
15930 |
// MIs[0] Operand 1 |
| 15931 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, |
15931 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, |
| 15932 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15932 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15933 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
15933 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 15934 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs) |
15934 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs) |
| 15935 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT, |
15935 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT, |
| 15936 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15936 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15937 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
15937 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 15938 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15938 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15939 |
GIR_EraseFromParent, /*InsnID*/0, |
15939 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15940 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15940 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15941 |
// GIR_Coverage, 1409, |
15941 |
// GIR_Coverage, 1409, |
| 15942 |
GIR_Done, |
15942 |
GIR_Done, |
| 15943 |
// Label 982: @38497 |
15943 |
// Label 982: @38497 |
| 15944 |
GIM_Try, /*On fail goto*//*Label 983*/ 38533, // Rule ID 1410 // |
15944 |
GIM_Try, /*On fail goto*//*Label 983*/ 38533, // Rule ID 1410 // |
| 15945 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
15945 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 15946 |
// MIs[0] Operand 1 |
15946 |
// MIs[0] Operand 1 |
| 15947 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT, |
15947 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT, |
| 15948 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15948 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15949 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
15949 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 15950 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs) |
15950 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs) |
| 15951 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu, |
15951 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu, |
| 15952 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
15952 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 15953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
15953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 15954 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15954 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15955 |
GIR_EraseFromParent, /*InsnID*/0, |
15955 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15956 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15956 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15957 |
// GIR_Coverage, 1410, |
15957 |
// GIR_Coverage, 1410, |
| 15958 |
GIR_Done, |
15958 |
GIR_Done, |
| 15959 |
// Label 983: @38533 |
15959 |
// Label 983: @38533 |
| 15960 |
GIM_Try, /*On fail goto*//*Label 984*/ 38588, // Rule ID 1411 // |
15960 |
GIM_Try, /*On fail goto*//*Label 984*/ 38588, // Rule ID 1411 // |
| 15961 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
15961 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 15962 |
// MIs[0] Operand 1 |
15962 |
// MIs[0] Operand 1 |
| 15963 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
15963 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 15964 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15964 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15965 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
15965 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 15966 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
15966 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
| 15967 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
15967 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15968 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
15968 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
| 15969 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
15969 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 15970 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15970 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15971 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
15971 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 15972 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
15972 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15973 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
15973 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
| 15974 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
15974 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 15975 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
15975 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 15976 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
15976 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 15977 |
GIR_EraseFromParent, /*InsnID*/0, |
15977 |
GIR_EraseFromParent, /*InsnID*/0, |
| 15978 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
15978 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 15979 |
// GIR_Coverage, 1411, |
15979 |
// GIR_Coverage, 1411, |
| 15980 |
GIR_Done, |
15980 |
GIR_Done, |
| 15981 |
// Label 984: @38588 |
15981 |
// Label 984: @38588 |
| 15982 |
GIM_Try, /*On fail goto*//*Label 985*/ 38643, // Rule ID 1412 // |
15982 |
GIM_Try, /*On fail goto*//*Label 985*/ 38643, // Rule ID 1412 // |
| 15983 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
15983 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 15984 |
// MIs[0] Operand 1 |
15984 |
// MIs[0] Operand 1 |
| 15985 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
15985 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 15986 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
15986 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 15987 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
15987 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 15988 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
15988 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
| 15989 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
15989 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 15990 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
15990 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
| 15991 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
15991 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 15992 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
15992 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 15993 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
15993 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 15994 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
15994 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 15995 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
15995 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
| 15996 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
15996 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 15997 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
15997 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 15998 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
15998 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 15999 |
GIR_EraseFromParent, /*InsnID*/0, |
15999 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16000 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16000 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16001 |
// GIR_Coverage, 1412, |
16001 |
// GIR_Coverage, 1412, |
| 16002 |
GIR_Done, |
16002 |
GIR_Done, |
| 16003 |
// Label 985: @38643 |
16003 |
// Label 985: @38643 |
| 16004 |
GIM_Reject, |
16004 |
GIM_Reject, |
| 16005 |
// Label 975: @38644 |
16005 |
// Label 975: @38644 |
| 16006 |
GIM_Reject, |
16006 |
GIM_Reject, |
| 16007 |
// Label 973: @38645 |
16007 |
// Label 973: @38645 |
| 16008 |
GIM_Try, /*On fail goto*//*Label 986*/ 39059, |
16008 |
GIM_Try, /*On fail goto*//*Label 986*/ 39059, |
| 16009 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
16009 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 16010 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
16010 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 16011 |
GIM_Try, /*On fail goto*//*Label 987*/ 38710, // Rule ID 1549 // |
16011 |
GIM_Try, /*On fail goto*//*Label 987*/ 38710, // Rule ID 1549 // |
| 16012 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
16012 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
| 16013 |
// MIs[0] Operand 1 |
16013 |
// MIs[0] Operand 1 |
| 16014 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
16014 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 16015 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
16015 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 16016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
16016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 16017 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i64] }) |
16017 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu64:{ *:[i32] } (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i64] }) |
| 16018 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
16018 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 16019 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
16019 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
| 16020 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16020 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16021 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16021 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16022 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16022 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16023 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16023 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16024 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu64, |
16024 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu64, |
| 16025 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
16025 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 16026 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16026 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16027 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
16027 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 16028 |
GIR_EraseFromParent, /*InsnID*/0, |
16028 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16029 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16029 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16030 |
// GIR_Coverage, 1549, |
16030 |
// GIR_Coverage, 1549, |
| 16031 |
GIR_Done, |
16031 |
GIR_Done, |
| 16032 |
// Label 987: @38710 |
16032 |
// Label 987: @38710 |
| 16033 |
GIM_Try, /*On fail goto*//*Label 988*/ 38766, // Rule ID 1550 // |
16033 |
GIM_Try, /*On fail goto*//*Label 988*/ 38766, // Rule ID 1550 // |
| 16034 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
16034 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
| 16035 |
// MIs[0] Operand 1 |
16035 |
// MIs[0] Operand 1 |
| 16036 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
16036 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 16037 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
16037 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 16038 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
16038 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 16039 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs)) |
16039 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }) => (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs)) |
| 16040 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
16040 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 16041 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
16041 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
| 16042 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16042 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16043 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16043 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16044 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16044 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16045 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16045 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16046 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64, |
16046 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64, |
| 16047 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
16047 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 16048 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO_64, /*AddRegisterRegFlags*/0, |
16048 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO_64, /*AddRegisterRegFlags*/0, |
| 16049 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16049 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16050 |
GIR_EraseFromParent, /*InsnID*/0, |
16050 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16051 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16051 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16052 |
// GIR_Coverage, 1550, |
16052 |
// GIR_Coverage, 1550, |
| 16053 |
GIR_Done, |
16053 |
GIR_Done, |
| 16054 |
// Label 988: @38766 |
16054 |
// Label 988: @38766 |
| 16055 |
GIM_Try, /*On fail goto*//*Label 989*/ 38821, // Rule ID 1551 // |
16055 |
GIM_Try, /*On fail goto*//*Label 989*/ 38821, // Rule ID 1551 // |
| 16056 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
16056 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
| 16057 |
// MIs[0] Operand 1 |
16057 |
// MIs[0] Operand 1 |
| 16058 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
16058 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 16059 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
16059 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 16060 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
16060 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 16061 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] }) |
16061 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] }) |
| 16062 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16062 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16063 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
16063 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
| 16064 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16064 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16065 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16065 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16066 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16066 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16067 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16067 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16068 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
16068 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
| 16069 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
16069 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 16070 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16070 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16071 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
16071 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 16072 |
GIR_EraseFromParent, /*InsnID*/0, |
16072 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16073 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16073 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16074 |
// GIR_Coverage, 1551, |
16074 |
// GIR_Coverage, 1551, |
| 16075 |
GIR_Done, |
16075 |
GIR_Done, |
| 16076 |
// Label 989: @38821 |
16076 |
// Label 989: @38821 |
| 16077 |
GIM_Try, /*On fail goto*//*Label 990*/ 38876, // Rule ID 1552 // |
16077 |
GIM_Try, /*On fail goto*//*Label 990*/ 38876, // Rule ID 1552 // |
| 16078 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
16078 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
| 16079 |
// MIs[0] Operand 1 |
16079 |
// MIs[0] Operand 1 |
| 16080 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
16080 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 16081 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
16081 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 16082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
16082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 16083 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] }) |
16083 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] }) |
| 16084 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16084 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16085 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
16085 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
| 16086 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16086 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16087 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16087 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16088 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16088 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16089 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16089 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16090 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
16090 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
| 16091 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
16091 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 16092 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16092 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16093 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
16093 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 16094 |
GIR_EraseFromParent, /*InsnID*/0, |
16094 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16095 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16095 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16096 |
// GIR_Coverage, 1552, |
16096 |
// GIR_Coverage, 1552, |
| 16097 |
GIR_Done, |
16097 |
GIR_Done, |
| 16098 |
// Label 990: @38876 |
16098 |
// Label 990: @38876 |
| 16099 |
GIM_Try, /*On fail goto*//*Label 991*/ 38912, // Rule ID 1553 // |
16099 |
GIM_Try, /*On fail goto*//*Label 991*/ 38912, // Rule ID 1553 // |
| 16100 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
16100 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
| 16101 |
// MIs[0] Operand 1 |
16101 |
// MIs[0] Operand 1 |
| 16102 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, |
16102 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, |
| 16103 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
16103 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 16104 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
16104 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 16105 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs) |
16105 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGT:{ *:[Other] }) => (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs) |
| 16106 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT64, |
16106 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT64, |
| 16107 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
16107 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 16108 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16108 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16109 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16109 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16110 |
GIR_EraseFromParent, /*InsnID*/0, |
16110 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16111 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16111 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16112 |
// GIR_Coverage, 1553, |
16112 |
// GIR_Coverage, 1553, |
| 16113 |
GIR_Done, |
16113 |
GIR_Done, |
| 16114 |
// Label 991: @38912 |
16114 |
// Label 991: @38912 |
| 16115 |
GIM_Try, /*On fail goto*//*Label 992*/ 38948, // Rule ID 1554 // |
16115 |
GIM_Try, /*On fail goto*//*Label 992*/ 38948, // Rule ID 1554 // |
| 16116 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
16116 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
| 16117 |
// MIs[0] Operand 1 |
16117 |
// MIs[0] Operand 1 |
| 16118 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT, |
16118 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT, |
| 16119 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
16119 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 16120 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
16120 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 16121 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs) |
16121 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs) |
| 16122 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64, |
16122 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu64, |
| 16123 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
16123 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 16124 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16124 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16125 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16125 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16126 |
GIR_EraseFromParent, /*InsnID*/0, |
16126 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16127 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16127 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16128 |
// GIR_Coverage, 1554, |
16128 |
// GIR_Coverage, 1554, |
| 16129 |
GIR_Done, |
16129 |
GIR_Done, |
| 16130 |
// Label 992: @38948 |
16130 |
// Label 992: @38948 |
| 16131 |
GIM_Try, /*On fail goto*//*Label 993*/ 39003, // Rule ID 1555 // |
16131 |
GIM_Try, /*On fail goto*//*Label 993*/ 39003, // Rule ID 1555 // |
| 16132 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
16132 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
| 16133 |
// MIs[0] Operand 1 |
16133 |
// MIs[0] Operand 1 |
| 16134 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
16134 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 16135 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
16135 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 16136 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
16136 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 16137 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] }) |
16137 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] }) |
| 16138 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16138 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16139 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
16139 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
| 16140 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16140 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16141 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16141 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16142 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16142 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16143 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16143 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16144 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
16144 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
| 16145 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
16145 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 16146 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16146 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16147 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
16147 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 16148 |
GIR_EraseFromParent, /*InsnID*/0, |
16148 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16149 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16149 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16150 |
// GIR_Coverage, 1555, |
16150 |
// GIR_Coverage, 1555, |
| 16151 |
GIR_Done, |
16151 |
GIR_Done, |
| 16152 |
// Label 993: @39003 |
16152 |
// Label 993: @39003 |
| 16153 |
GIM_Try, /*On fail goto*//*Label 994*/ 39058, // Rule ID 1556 // |
16153 |
GIM_Try, /*On fail goto*//*Label 994*/ 39058, // Rule ID 1556 // |
| 16154 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
16154 |
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips, |
| 16155 |
// MIs[0] Operand 1 |
16155 |
// MIs[0] Operand 1 |
| 16156 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
16156 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 16157 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
16157 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 16158 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
16158 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 16159 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] }) |
16159 |
// (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }) => (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] }) |
| 16160 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16160 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16161 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
16161 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
| 16162 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16162 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16163 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16163 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16164 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16164 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16165 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16165 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16166 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
16166 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi, |
| 16167 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
16167 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 16168 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16168 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16169 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
16169 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 16170 |
GIR_EraseFromParent, /*InsnID*/0, |
16170 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16171 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16171 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16172 |
// GIR_Coverage, 1556, |
16172 |
// GIR_Coverage, 1556, |
| 16173 |
GIR_Done, |
16173 |
GIR_Done, |
| 16174 |
// Label 994: @39058 |
16174 |
// Label 994: @39058 |
| 16175 |
GIM_Reject, |
16175 |
GIM_Reject, |
| 16176 |
// Label 986: @39059 |
16176 |
// Label 986: @39059 |
| 16177 |
GIM_Reject, |
16177 |
GIM_Reject, |
| 16178 |
// Label 974: @39060 |
16178 |
// Label 974: @39060 |
| 16179 |
GIM_Try, /*On fail goto*//*Label 995*/ 40100, |
16179 |
GIM_Try, /*On fail goto*//*Label 995*/ 40100, |
| 16180 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
16180 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 16181 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
16181 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 16182 |
GIM_Try, /*On fail goto*//*Label 996*/ 39129, // Rule ID 1842 // |
16182 |
GIM_Try, /*On fail goto*//*Label 996*/ 39129, // Rule ID 1842 // |
| 16183 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
16183 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 16184 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
16184 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 16185 |
// MIs[0] Operand 1 |
16185 |
// MIs[0] Operand 1 |
| 16186 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
16186 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 16187 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
16187 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 16188 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
16188 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 16189 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
16189 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SltiuCCRxImmX16:{ *:[i32] } (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
| 16190 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16190 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16191 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XorRxRxRy16, |
16191 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XorRxRxRy16, |
| 16192 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16192 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16193 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16193 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16194 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16194 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16195 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16195 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16196 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltiuCCRxImmX16, |
16196 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltiuCCRxImmX16, |
| 16197 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
16197 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
| 16198 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16198 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16199 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
16199 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 16200 |
GIR_EraseFromParent, /*InsnID*/0, |
16200 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16201 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16201 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16202 |
// GIR_Coverage, 1842, |
16202 |
// GIR_Coverage, 1842, |
| 16203 |
GIR_Done, |
16203 |
GIR_Done, |
| 16204 |
// Label 996: @39129 |
16204 |
// Label 996: @39129 |
| 16205 |
GIM_Try, /*On fail goto*//*Label 997*/ 39204, // Rule ID 1844 // |
16205 |
GIM_Try, /*On fail goto*//*Label 997*/ 39204, // Rule ID 1844 // |
| 16206 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
16206 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 16207 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
16207 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 16208 |
// MIs[0] Operand 1 |
16208 |
// MIs[0] Operand 1 |
| 16209 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
16209 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 16210 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
16210 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 16211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
16211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 16212 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] })) |
16212 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] })) |
| 16213 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16213 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16214 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
16214 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16215 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16, |
16215 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16, |
| 16216 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
16216 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16217 |
GIR_AddImm, /*InsnID*/2, /*Imm*/1, |
16217 |
GIR_AddImm, /*InsnID*/2, /*Imm*/1, |
| 16218 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
16218 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16219 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltCCRxRy16, |
16219 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltCCRxRy16, |
| 16220 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16220 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16221 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16221 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16222 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16222 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16223 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16223 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16224 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16, |
16224 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16, |
| 16225 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz |
16225 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz |
| 16226 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16226 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16227 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
16227 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16228 |
GIR_EraseFromParent, /*InsnID*/0, |
16228 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16229 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16229 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16230 |
// GIR_Coverage, 1844, |
16230 |
// GIR_Coverage, 1844, |
| 16231 |
GIR_Done, |
16231 |
GIR_Done, |
| 16232 |
// Label 997: @39204 |
16232 |
// Label 997: @39204 |
| 16233 |
GIM_Try, /*On fail goto*//*Label 998*/ 39244, // Rule ID 1846 // |
16233 |
GIM_Try, /*On fail goto*//*Label 998*/ 39244, // Rule ID 1846 // |
| 16234 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
16234 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 16235 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
16235 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 16236 |
// MIs[0] Operand 1 |
16236 |
// MIs[0] Operand 1 |
| 16237 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, |
16237 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, |
| 16238 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
16238 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 16239 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
16239 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 16240 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs) |
16240 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs) |
| 16241 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltCCRxRy16, |
16241 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltCCRxRy16, |
| 16242 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
16242 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
| 16243 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16243 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16244 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16244 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16245 |
GIR_EraseFromParent, /*InsnID*/0, |
16245 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16246 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16246 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16247 |
// GIR_Coverage, 1846, |
16247 |
// GIR_Coverage, 1846, |
| 16248 |
GIR_Done, |
16248 |
GIR_Done, |
| 16249 |
// Label 998: @39244 |
16249 |
// Label 998: @39244 |
| 16250 |
GIM_Try, /*On fail goto*//*Label 999*/ 39319, // Rule ID 1847 // |
16250 |
GIM_Try, /*On fail goto*//*Label 999*/ 39319, // Rule ID 1847 // |
| 16251 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
16251 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 16252 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
16252 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 16253 |
// MIs[0] Operand 1 |
16253 |
// MIs[0] Operand 1 |
| 16254 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
16254 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 16255 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
16255 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 16256 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
16256 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 16257 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImm16:{ *:[i32] } 1:{ *:[i32] })) |
16257 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImm16:{ *:[i32] } 1:{ *:[i32] })) |
| 16258 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16258 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16259 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
16259 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16260 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImm16, |
16260 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImm16, |
| 16261 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
16261 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16262 |
GIR_AddImm, /*InsnID*/2, /*Imm*/1, |
16262 |
GIR_AddImm, /*InsnID*/2, /*Imm*/1, |
| 16263 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
16263 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16264 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltCCRxRy16, |
16264 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltCCRxRy16, |
| 16265 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16265 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16266 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16266 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16267 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16267 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16268 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16268 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16269 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16, |
16269 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16, |
| 16270 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz |
16270 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz |
| 16271 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16271 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16272 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
16272 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16273 |
GIR_EraseFromParent, /*InsnID*/0, |
16273 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16274 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16274 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16275 |
// GIR_Coverage, 1847, |
16275 |
// GIR_Coverage, 1847, |
| 16276 |
GIR_Done, |
16276 |
GIR_Done, |
| 16277 |
// Label 999: @39319 |
16277 |
// Label 999: @39319 |
| 16278 |
GIM_Try, /*On fail goto*//*Label 1000*/ 39359, // Rule ID 1848 // |
16278 |
GIM_Try, /*On fail goto*//*Label 1000*/ 39359, // Rule ID 1848 // |
| 16279 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
16279 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 16280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
16280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 16281 |
// MIs[0] Operand 1 |
16281 |
// MIs[0] Operand 1 |
| 16282 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, |
16282 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, |
| 16283 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
16283 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 16284 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
16284 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 16285 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry) |
16285 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }) => (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry) |
| 16286 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltCCRxRy16, |
16286 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltCCRxRy16, |
| 16287 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
16287 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
| 16288 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rx |
16288 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rx |
| 16289 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ry |
16289 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ry |
| 16290 |
GIR_EraseFromParent, /*InsnID*/0, |
16290 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16291 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16291 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16292 |
// GIR_Coverage, 1848, |
16292 |
// GIR_Coverage, 1848, |
| 16293 |
GIR_Done, |
16293 |
GIR_Done, |
| 16294 |
// Label 1000: @39359 |
16294 |
// Label 1000: @39359 |
| 16295 |
GIM_Try, /*On fail goto*//*Label 1001*/ 39434, // Rule ID 1850 // |
16295 |
GIM_Try, /*On fail goto*//*Label 1001*/ 39434, // Rule ID 1850 // |
| 16296 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
16296 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 16297 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
16297 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 16298 |
// MIs[0] Operand 1 |
16298 |
// MIs[0] Operand 1 |
| 16299 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
16299 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 16300 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
16300 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 16301 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
16301 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 16302 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } 0:{ *:[i32] }), (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs)) |
16302 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } 0:{ *:[i32] }), (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs)) |
| 16303 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16303 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16304 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
16304 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16305 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::XorRxRxRy16, |
16305 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::XorRxRxRy16, |
| 16306 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
16306 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16307 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16307 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16308 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16308 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16309 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
16309 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16310 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::LiRxImmX16, |
16310 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::LiRxImmX16, |
| 16311 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16311 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16312 |
GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
16312 |
GIR_AddImm, /*InsnID*/1, /*Imm*/0, |
| 16313 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16313 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16314 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16, |
16314 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16, |
| 16315 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
16315 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
| 16316 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16316 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16317 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
16317 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16318 |
GIR_EraseFromParent, /*InsnID*/0, |
16318 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16319 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16319 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16320 |
// GIR_Coverage, 1850, |
16320 |
// GIR_Coverage, 1850, |
| 16321 |
GIR_Done, |
16321 |
GIR_Done, |
| 16322 |
// Label 1001: @39434 |
16322 |
// Label 1001: @39434 |
| 16323 |
GIM_Try, /*On fail goto*//*Label 1002*/ 39509, // Rule ID 1851 // |
16323 |
GIM_Try, /*On fail goto*//*Label 1002*/ 39509, // Rule ID 1851 // |
| 16324 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
16324 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 16325 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
16325 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 16326 |
// MIs[0] Operand 1 |
16326 |
// MIs[0] Operand 1 |
| 16327 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
16327 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 16328 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
16328 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 16329 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
16329 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 16330 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] })) |
16330 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] })) |
| 16331 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16331 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16332 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
16332 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16333 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16, |
16333 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16, |
| 16334 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
16334 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16335 |
GIR_AddImm, /*InsnID*/2, /*Imm*/1, |
16335 |
GIR_AddImm, /*InsnID*/2, /*Imm*/1, |
| 16336 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
16336 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16337 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltuCCRxRy16, |
16337 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltuCCRxRy16, |
| 16338 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16338 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16339 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16339 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16340 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16340 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16341 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16341 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16342 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16, |
16342 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16, |
| 16343 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz |
16343 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz |
| 16344 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16344 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16345 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
16345 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16346 |
GIR_EraseFromParent, /*InsnID*/0, |
16346 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16347 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16347 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16348 |
// GIR_Coverage, 1851, |
16348 |
// GIR_Coverage, 1851, |
| 16349 |
GIR_Done, |
16349 |
GIR_Done, |
| 16350 |
// Label 1002: @39509 |
16350 |
// Label 1002: @39509 |
| 16351 |
GIM_Try, /*On fail goto*//*Label 1003*/ 39549, // Rule ID 1852 // |
16351 |
GIM_Try, /*On fail goto*//*Label 1003*/ 39549, // Rule ID 1852 // |
| 16352 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
16352 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 16353 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
16353 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 16354 |
// MIs[0] Operand 1 |
16354 |
// MIs[0] Operand 1 |
| 16355 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT, |
16355 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT, |
| 16356 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
16356 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 16357 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
16357 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 16358 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs) |
16358 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs) |
| 16359 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16, |
16359 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16, |
| 16360 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
16360 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
| 16361 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16361 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16362 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16362 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16363 |
GIR_EraseFromParent, /*InsnID*/0, |
16363 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16364 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16364 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16365 |
// GIR_Coverage, 1852, |
16365 |
// GIR_Coverage, 1852, |
| 16366 |
GIR_Done, |
16366 |
GIR_Done, |
| 16367 |
// Label 1003: @39549 |
16367 |
// Label 1003: @39549 |
| 16368 |
GIM_Try, /*On fail goto*//*Label 1004*/ 39624, // Rule ID 1853 // |
16368 |
GIM_Try, /*On fail goto*//*Label 1004*/ 39624, // Rule ID 1853 // |
| 16369 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
16369 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 16370 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
16370 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 16371 |
// MIs[0] Operand 1 |
16371 |
// MIs[0] Operand 1 |
| 16372 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
16372 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 16373 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
16373 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 16374 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
16374 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 16375 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] })) |
16375 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] })) |
| 16376 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16376 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16377 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
16377 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 16378 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16, |
16378 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::LiRxImmX16, |
| 16379 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
16379 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 16380 |
GIR_AddImm, /*InsnID*/2, /*Imm*/1, |
16380 |
GIR_AddImm, /*InsnID*/2, /*Imm*/1, |
| 16381 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
16381 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16382 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltuCCRxRy16, |
16382 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SltuCCRxRy16, |
| 16383 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16383 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16384 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16384 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16385 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16385 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16386 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16386 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16387 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16, |
16387 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XorRxRxRy16, |
| 16388 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz |
16388 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rz |
| 16389 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16389 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16390 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
16390 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 16391 |
GIR_EraseFromParent, /*InsnID*/0, |
16391 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16392 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16392 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16393 |
// GIR_Coverage, 1853, |
16393 |
// GIR_Coverage, 1853, |
| 16394 |
GIR_Done, |
16394 |
GIR_Done, |
| 16395 |
// Label 1004: @39624 |
16395 |
// Label 1004: @39624 |
| 16396 |
GIM_Try, /*On fail goto*//*Label 1005*/ 39664, // Rule ID 1854 // |
16396 |
GIM_Try, /*On fail goto*//*Label 1005*/ 39664, // Rule ID 1854 // |
| 16397 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
16397 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 16398 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
16398 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 16399 |
// MIs[0] Operand 1 |
16399 |
// MIs[0] Operand 1 |
| 16400 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, |
16400 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, |
| 16401 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
16401 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 16402 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
16402 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 16403 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETULT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry) |
16403 |
// (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETULT:{ *:[Other] }) => (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry) |
| 16404 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16, |
16404 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SltuCCRxRy16, |
| 16405 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
16405 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // cc |
| 16406 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rx |
16406 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rx |
| 16407 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ry |
16407 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ry |
| 16408 |
GIR_EraseFromParent, /*InsnID*/0, |
16408 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16409 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16409 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16410 |
// GIR_Coverage, 1854, |
16410 |
// GIR_Coverage, 1854, |
| 16411 |
GIR_Done, |
16411 |
GIR_Done, |
| 16412 |
// Label 1005: @39664 |
16412 |
// Label 1005: @39664 |
| 16413 |
GIM_Try, /*On fail goto*//*Label 1006*/ 39723, // Rule ID 2164 // |
16413 |
GIM_Try, /*On fail goto*//*Label 1006*/ 39723, // Rule ID 2164 // |
| 16414 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
16414 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 16415 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
16415 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 16416 |
// MIs[0] Operand 1 |
16416 |
// MIs[0] Operand 1 |
| 16417 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
16417 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 16418 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
16418 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 16419 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
16419 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 16420 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
16420 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) => (SLTiu_MM:{ *:[i32] } (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
| 16421 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16421 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16422 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
16422 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
| 16423 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16423 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16424 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16424 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16425 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16425 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16426 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16426 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16427 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu_MM, |
16427 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTiu_MM, |
| 16428 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
16428 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 16429 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16429 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16430 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
16430 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 16431 |
GIR_EraseFromParent, /*InsnID*/0, |
16431 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16432 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16432 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16433 |
// GIR_Coverage, 2164, |
16433 |
// GIR_Coverage, 2164, |
| 16434 |
GIR_Done, |
16434 |
GIR_Done, |
| 16435 |
// Label 1006: @39723 |
16435 |
// Label 1006: @39723 |
| 16436 |
GIM_Try, /*On fail goto*//*Label 1007*/ 39783, // Rule ID 2165 // |
16436 |
GIM_Try, /*On fail goto*//*Label 1007*/ 39783, // Rule ID 2165 // |
| 16437 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
16437 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 16438 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
16438 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 16439 |
// MIs[0] Operand 1 |
16439 |
// MIs[0] Operand 1 |
| 16440 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
16440 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 16441 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
16441 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 16442 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
16442 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 16443 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)) |
16443 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)) |
| 16444 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16444 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16445 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
16445 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
| 16446 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16446 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16447 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16447 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16448 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16448 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16449 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16449 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16450 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM, |
16450 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM, |
| 16451 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
16451 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 16452 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
16452 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 16453 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16453 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16454 |
GIR_EraseFromParent, /*InsnID*/0, |
16454 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16455 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16455 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16456 |
// GIR_Coverage, 2165, |
16456 |
// GIR_Coverage, 2165, |
| 16457 |
GIR_Done, |
16457 |
GIR_Done, |
| 16458 |
// Label 1007: @39783 |
16458 |
// Label 1007: @39783 |
| 16459 |
GIM_Try, /*On fail goto*//*Label 1008*/ 39842, // Rule ID 2166 // |
16459 |
GIM_Try, /*On fail goto*//*Label 1008*/ 39842, // Rule ID 2166 // |
| 16460 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
16460 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 16461 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
16461 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 16462 |
// MIs[0] Operand 1 |
16462 |
// MIs[0] Operand 1 |
| 16463 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
16463 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 16464 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
16464 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 16465 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
16465 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 16466 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] }) |
16466 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] }) |
| 16467 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16467 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16468 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
16468 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
| 16469 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16469 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16470 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16470 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16471 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16471 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16472 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16472 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16473 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM, |
16473 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM, |
| 16474 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
16474 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 16475 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16475 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16476 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
16476 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 16477 |
GIR_EraseFromParent, /*InsnID*/0, |
16477 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16478 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16478 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16479 |
// GIR_Coverage, 2166, |
16479 |
// GIR_Coverage, 2166, |
| 16480 |
GIR_Done, |
16480 |
GIR_Done, |
| 16481 |
// Label 1008: @39842 |
16481 |
// Label 1008: @39842 |
| 16482 |
GIM_Try, /*On fail goto*//*Label 1009*/ 39901, // Rule ID 2167 // |
16482 |
GIM_Try, /*On fail goto*//*Label 1009*/ 39901, // Rule ID 2167 // |
| 16483 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
16483 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 16484 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
16484 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 16485 |
// MIs[0] Operand 1 |
16485 |
// MIs[0] Operand 1 |
| 16486 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
16486 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 16487 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
16487 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 16488 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
16488 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 16489 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] }) |
16489 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] }) |
| 16490 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16490 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16491 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
16491 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
| 16492 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16492 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16493 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16493 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16494 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16494 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16495 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16495 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16496 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM, |
16496 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM, |
| 16497 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
16497 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 16498 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16498 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16499 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
16499 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 16500 |
GIR_EraseFromParent, /*InsnID*/0, |
16500 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16501 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16501 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16502 |
// GIR_Coverage, 2167, |
16502 |
// GIR_Coverage, 2167, |
| 16503 |
GIR_Done, |
16503 |
GIR_Done, |
| 16504 |
// Label 1009: @39901 |
16504 |
// Label 1009: @39901 |
| 16505 |
GIM_Try, /*On fail goto*//*Label 1010*/ 39941, // Rule ID 2168 // |
16505 |
GIM_Try, /*On fail goto*//*Label 1010*/ 39941, // Rule ID 2168 // |
| 16506 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
16506 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 16507 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
16507 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 16508 |
// MIs[0] Operand 1 |
16508 |
// MIs[0] Operand 1 |
| 16509 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, |
16509 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, |
| 16510 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
16510 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 16511 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
16511 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 16512 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs) |
16512 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) => (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs) |
| 16513 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT_MM, |
16513 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLT_MM, |
| 16514 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
16514 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 16515 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16515 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16516 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16516 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16517 |
GIR_EraseFromParent, /*InsnID*/0, |
16517 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16518 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16518 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16519 |
// GIR_Coverage, 2168, |
16519 |
// GIR_Coverage, 2168, |
| 16520 |
GIR_Done, |
16520 |
GIR_Done, |
| 16521 |
// Label 1010: @39941 |
16521 |
// Label 1010: @39941 |
| 16522 |
GIM_Try, /*On fail goto*//*Label 1011*/ 39981, // Rule ID 2169 // |
16522 |
GIM_Try, /*On fail goto*//*Label 1011*/ 39981, // Rule ID 2169 // |
| 16523 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
16523 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 16524 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
16524 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 16525 |
// MIs[0] Operand 1 |
16525 |
// MIs[0] Operand 1 |
| 16526 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT, |
16526 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT, |
| 16527 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
16527 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 16528 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
16528 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 16529 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs) |
16529 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) => (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs) |
| 16530 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM, |
16530 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLTu_MM, |
| 16531 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
16531 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 16532 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16532 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16533 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16533 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16534 |
GIR_EraseFromParent, /*InsnID*/0, |
16534 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16535 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16535 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16536 |
// GIR_Coverage, 2169, |
16536 |
// GIR_Coverage, 2169, |
| 16537 |
GIR_Done, |
16537 |
GIR_Done, |
| 16538 |
// Label 1011: @39981 |
16538 |
// Label 1011: @39981 |
| 16539 |
GIM_Try, /*On fail goto*//*Label 1012*/ 40040, // Rule ID 2170 // |
16539 |
GIM_Try, /*On fail goto*//*Label 1012*/ 40040, // Rule ID 2170 // |
| 16540 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
16540 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 16541 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
16541 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 16542 |
// MIs[0] Operand 1 |
16542 |
// MIs[0] Operand 1 |
| 16543 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
16543 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 16544 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
16544 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 16545 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
16545 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 16546 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
16546 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
| 16547 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16547 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16548 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
16548 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
| 16549 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16549 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16550 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16550 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16551 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16551 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16552 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16552 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16553 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM, |
16553 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM, |
| 16554 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
16554 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 16555 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16555 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16556 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
16556 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 16557 |
GIR_EraseFromParent, /*InsnID*/0, |
16557 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16558 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16558 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16559 |
// GIR_Coverage, 2170, |
16559 |
// GIR_Coverage, 2170, |
| 16560 |
GIR_Done, |
16560 |
GIR_Done, |
| 16561 |
// Label 1012: @40040 |
16561 |
// Label 1012: @40040 |
| 16562 |
GIM_Try, /*On fail goto*//*Label 1013*/ 40099, // Rule ID 2171 // |
16562 |
GIM_Try, /*On fail goto*//*Label 1013*/ 40099, // Rule ID 2171 // |
| 16563 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
16563 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 16564 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
16564 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 16565 |
// MIs[0] Operand 1 |
16565 |
// MIs[0] Operand 1 |
| 16566 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
16566 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 16567 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
16567 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 16568 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
16568 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 16569 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
16569 |
// (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) => (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] }) |
| 16570 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
16570 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16571 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
16571 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
| 16572 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
16572 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 16573 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
16573 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 16574 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
16574 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 16575 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
16575 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 16576 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM, |
16576 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::XORi_MM, |
| 16577 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
16577 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt |
| 16578 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
16578 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 16579 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
16579 |
GIR_AddImm, /*InsnID*/0, /*Imm*/1, |
| 16580 |
GIR_EraseFromParent, /*InsnID*/0, |
16580 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16581 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16581 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16582 |
// GIR_Coverage, 2171, |
16582 |
// GIR_Coverage, 2171, |
| 16583 |
GIR_Done, |
16583 |
GIR_Done, |
| 16584 |
// Label 1013: @40099 |
16584 |
// Label 1013: @40099 |
| 16585 |
GIM_Reject, |
16585 |
GIM_Reject, |
| 16586 |
// Label 995: @40100 |
16586 |
// Label 995: @40100 |
| 16587 |
GIM_Reject, |
16587 |
GIM_Reject, |
| 16588 |
// Label 949: @40101 |
16588 |
// Label 949: @40101 |
| 16589 |
GIM_Reject, |
16589 |
GIM_Reject, |
| 16590 |
// Label 28: @40102 |
16590 |
// Label 28: @40102 |
| 16591 |
GIM_Try, /*On fail goto*//*Label 1014*/ 41821, |
16591 |
GIM_Try, /*On fail goto*//*Label 1014*/ 41821, |
| 16592 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
16592 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 16593 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1017*/ 40644, |
16593 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1017*/ 40644, |
| 16594 |
/*GILLT_s32*//*Label 1015*/ 40116, |
16594 |
/*GILLT_s32*//*Label 1015*/ 40116, |
| 16595 |
/*GILLT_s64*//*Label 1016*/ 40380, |
16595 |
/*GILLT_s64*//*Label 1016*/ 40380, |
| 16596 |
// Label 1015: @40116 |
16596 |
// Label 1015: @40116 |
| 16597 |
GIM_Try, /*On fail goto*//*Label 1018*/ 40379, |
16597 |
GIM_Try, /*On fail goto*//*Label 1018*/ 40379, |
| 16598 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
16598 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 16599 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID, |
16599 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID, |
| 16600 |
GIM_Try, /*On fail goto*//*Label 1019*/ 40162, // Rule ID 300 // |
16600 |
GIM_Try, /*On fail goto*//*Label 1019*/ 40162, // Rule ID 300 // |
| 16601 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16601 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16602 |
// MIs[0] Operand 1 |
16602 |
// MIs[0] Operand 1 |
| 16603 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, |
16603 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, |
| 16604 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16604 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16605 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16605 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16606 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16606 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16607 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_S, |
16607 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_S, |
| 16608 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16608 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16609 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16609 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16610 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16610 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16611 |
GIR_EraseFromParent, /*InsnID*/0, |
16611 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16612 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16612 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16613 |
// GIR_Coverage, 300, |
16613 |
// GIR_Coverage, 300, |
| 16614 |
GIR_Done, |
16614 |
GIR_Done, |
| 16615 |
// Label 1019: @40162 |
16615 |
// Label 1019: @40162 |
| 16616 |
GIM_Try, /*On fail goto*//*Label 1020*/ 40198, // Rule ID 301 // |
16616 |
GIM_Try, /*On fail goto*//*Label 1020*/ 40198, // Rule ID 301 // |
| 16617 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16617 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16618 |
// MIs[0] Operand 1 |
16618 |
// MIs[0] Operand 1 |
| 16619 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ, |
16619 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ, |
| 16620 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16620 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16621 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16621 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16622 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16622 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16623 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_S, |
16623 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_S, |
| 16624 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16624 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16625 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16625 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16626 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16626 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16627 |
GIR_EraseFromParent, /*InsnID*/0, |
16627 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16628 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16628 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16629 |
// GIR_Coverage, 301, |
16629 |
// GIR_Coverage, 301, |
| 16630 |
GIR_Done, |
16630 |
GIR_Done, |
| 16631 |
// Label 1020: @40198 |
16631 |
// Label 1020: @40198 |
| 16632 |
GIM_Try, /*On fail goto*//*Label 1021*/ 40234, // Rule ID 302 // |
16632 |
GIM_Try, /*On fail goto*//*Label 1021*/ 40234, // Rule ID 302 // |
| 16633 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16633 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16634 |
// MIs[0] Operand 1 |
16634 |
// MIs[0] Operand 1 |
| 16635 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ, |
16635 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ, |
| 16636 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16636 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16637 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16637 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16638 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16638 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16639 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_S, |
16639 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_S, |
| 16640 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16640 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16641 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16641 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16642 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16642 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16643 |
GIR_EraseFromParent, /*InsnID*/0, |
16643 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16644 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16644 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16645 |
// GIR_Coverage, 302, |
16645 |
// GIR_Coverage, 302, |
| 16646 |
GIR_Done, |
16646 |
GIR_Done, |
| 16647 |
// Label 1021: @40234 |
16647 |
// Label 1021: @40234 |
| 16648 |
GIM_Try, /*On fail goto*//*Label 1022*/ 40270, // Rule ID 303 // |
16648 |
GIM_Try, /*On fail goto*//*Label 1022*/ 40270, // Rule ID 303 // |
| 16649 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16649 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16650 |
// MIs[0] Operand 1 |
16650 |
// MIs[0] Operand 1 |
| 16651 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT, |
16651 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT, |
| 16652 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16652 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16653 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16653 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16654 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16654 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16655 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_S, |
16655 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_S, |
| 16656 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16656 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16657 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16657 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16658 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16658 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16659 |
GIR_EraseFromParent, /*InsnID*/0, |
16659 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16660 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16660 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16661 |
// GIR_Coverage, 303, |
16661 |
// GIR_Coverage, 303, |
| 16662 |
GIR_Done, |
16662 |
GIR_Done, |
| 16663 |
// Label 1022: @40270 |
16663 |
// Label 1022: @40270 |
| 16664 |
GIM_Try, /*On fail goto*//*Label 1023*/ 40306, // Rule ID 304 // |
16664 |
GIM_Try, /*On fail goto*//*Label 1023*/ 40306, // Rule ID 304 // |
| 16665 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16665 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16666 |
// MIs[0] Operand 1 |
16666 |
// MIs[0] Operand 1 |
| 16667 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT, |
16667 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT, |
| 16668 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16668 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16669 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16669 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16670 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16670 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16671 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_S, |
16671 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_S, |
| 16672 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16672 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16673 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16673 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16674 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16674 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16675 |
GIR_EraseFromParent, /*InsnID*/0, |
16675 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16676 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16676 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16677 |
// GIR_Coverage, 304, |
16677 |
// GIR_Coverage, 304, |
| 16678 |
GIR_Done, |
16678 |
GIR_Done, |
| 16679 |
// Label 1023: @40306 |
16679 |
// Label 1023: @40306 |
| 16680 |
GIM_Try, /*On fail goto*//*Label 1024*/ 40342, // Rule ID 305 // |
16680 |
GIM_Try, /*On fail goto*//*Label 1024*/ 40342, // Rule ID 305 // |
| 16681 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16681 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16682 |
// MIs[0] Operand 1 |
16682 |
// MIs[0] Operand 1 |
| 16683 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE, |
16683 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE, |
| 16684 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16684 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16685 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16685 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16686 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16686 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16687 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_S, |
16687 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_S, |
| 16688 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16688 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16689 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16689 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16690 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16690 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16691 |
GIR_EraseFromParent, /*InsnID*/0, |
16691 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16692 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16692 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16693 |
// GIR_Coverage, 305, |
16693 |
// GIR_Coverage, 305, |
| 16694 |
GIR_Done, |
16694 |
GIR_Done, |
| 16695 |
// Label 1024: @40342 |
16695 |
// Label 1024: @40342 |
| 16696 |
GIM_Try, /*On fail goto*//*Label 1025*/ 40378, // Rule ID 306 // |
16696 |
GIM_Try, /*On fail goto*//*Label 1025*/ 40378, // Rule ID 306 // |
| 16697 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16697 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16698 |
// MIs[0] Operand 1 |
16698 |
// MIs[0] Operand 1 |
| 16699 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, |
16699 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, |
| 16700 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16700 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16701 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16701 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16702 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16702 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16703 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_S, |
16703 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_S, |
| 16704 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16704 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16705 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16705 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16706 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16706 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16707 |
GIR_EraseFromParent, /*InsnID*/0, |
16707 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16708 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16708 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16709 |
// GIR_Coverage, 306, |
16709 |
// GIR_Coverage, 306, |
| 16710 |
GIR_Done, |
16710 |
GIR_Done, |
| 16711 |
// Label 1025: @40378 |
16711 |
// Label 1025: @40378 |
| 16712 |
GIM_Reject, |
16712 |
GIM_Reject, |
| 16713 |
// Label 1018: @40379 |
16713 |
// Label 1018: @40379 |
| 16714 |
GIM_Reject, |
16714 |
GIM_Reject, |
| 16715 |
// Label 1016: @40380 |
16715 |
// Label 1016: @40380 |
| 16716 |
GIM_Try, /*On fail goto*//*Label 1026*/ 40643, |
16716 |
GIM_Try, /*On fail goto*//*Label 1026*/ 40643, |
| 16717 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
16717 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 16718 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID, |
16718 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID, |
| 16719 |
GIM_Try, /*On fail goto*//*Label 1027*/ 40426, // Rule ID 307 // |
16719 |
GIM_Try, /*On fail goto*//*Label 1027*/ 40426, // Rule ID 307 // |
| 16720 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16720 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16721 |
// MIs[0] Operand 1 |
16721 |
// MIs[0] Operand 1 |
| 16722 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, |
16722 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, |
| 16723 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
16723 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 16724 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
16724 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 16725 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
16725 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 16726 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_D, |
16726 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_D, |
| 16727 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16727 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16728 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16728 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16729 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16729 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16730 |
GIR_EraseFromParent, /*InsnID*/0, |
16730 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16731 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16731 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16732 |
// GIR_Coverage, 307, |
16732 |
// GIR_Coverage, 307, |
| 16733 |
GIR_Done, |
16733 |
GIR_Done, |
| 16734 |
// Label 1027: @40426 |
16734 |
// Label 1027: @40426 |
| 16735 |
GIM_Try, /*On fail goto*//*Label 1028*/ 40462, // Rule ID 308 // |
16735 |
GIM_Try, /*On fail goto*//*Label 1028*/ 40462, // Rule ID 308 // |
| 16736 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16736 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16737 |
// MIs[0] Operand 1 |
16737 |
// MIs[0] Operand 1 |
| 16738 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ, |
16738 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ, |
| 16739 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
16739 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 16740 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
16740 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 16741 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
16741 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 16742 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_D, |
16742 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_D, |
| 16743 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16743 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16744 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16744 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16745 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16745 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16746 |
GIR_EraseFromParent, /*InsnID*/0, |
16746 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16747 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16747 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16748 |
// GIR_Coverage, 308, |
16748 |
// GIR_Coverage, 308, |
| 16749 |
GIR_Done, |
16749 |
GIR_Done, |
| 16750 |
// Label 1028: @40462 |
16750 |
// Label 1028: @40462 |
| 16751 |
GIM_Try, /*On fail goto*//*Label 1029*/ 40498, // Rule ID 309 // |
16751 |
GIM_Try, /*On fail goto*//*Label 1029*/ 40498, // Rule ID 309 // |
| 16752 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16752 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16753 |
// MIs[0] Operand 1 |
16753 |
// MIs[0] Operand 1 |
| 16754 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ, |
16754 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ, |
| 16755 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
16755 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 16756 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
16756 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 16757 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
16757 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 16758 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_D, |
16758 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_D, |
| 16759 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16759 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16760 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16760 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16761 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16761 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16762 |
GIR_EraseFromParent, /*InsnID*/0, |
16762 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16763 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16763 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16764 |
// GIR_Coverage, 309, |
16764 |
// GIR_Coverage, 309, |
| 16765 |
GIR_Done, |
16765 |
GIR_Done, |
| 16766 |
// Label 1029: @40498 |
16766 |
// Label 1029: @40498 |
| 16767 |
GIM_Try, /*On fail goto*//*Label 1030*/ 40534, // Rule ID 310 // |
16767 |
GIM_Try, /*On fail goto*//*Label 1030*/ 40534, // Rule ID 310 // |
| 16768 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16768 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16769 |
// MIs[0] Operand 1 |
16769 |
// MIs[0] Operand 1 |
| 16770 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT, |
16770 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT, |
| 16771 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
16771 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 16772 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
16772 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 16773 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
16773 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 16774 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_D, |
16774 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_D, |
| 16775 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16775 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16776 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16776 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16777 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16777 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16778 |
GIR_EraseFromParent, /*InsnID*/0, |
16778 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16779 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16779 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16780 |
// GIR_Coverage, 310, |
16780 |
// GIR_Coverage, 310, |
| 16781 |
GIR_Done, |
16781 |
GIR_Done, |
| 16782 |
// Label 1030: @40534 |
16782 |
// Label 1030: @40534 |
| 16783 |
GIM_Try, /*On fail goto*//*Label 1031*/ 40570, // Rule ID 311 // |
16783 |
GIM_Try, /*On fail goto*//*Label 1031*/ 40570, // Rule ID 311 // |
| 16784 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16784 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16785 |
// MIs[0] Operand 1 |
16785 |
// MIs[0] Operand 1 |
| 16786 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT, |
16786 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT, |
| 16787 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
16787 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 16788 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
16788 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 16789 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
16789 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 16790 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_D, |
16790 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_D, |
| 16791 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16791 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16792 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16792 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16793 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16793 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16794 |
GIR_EraseFromParent, /*InsnID*/0, |
16794 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16795 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16795 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16796 |
// GIR_Coverage, 311, |
16796 |
// GIR_Coverage, 311, |
| 16797 |
GIR_Done, |
16797 |
GIR_Done, |
| 16798 |
// Label 1031: @40570 |
16798 |
// Label 1031: @40570 |
| 16799 |
GIM_Try, /*On fail goto*//*Label 1032*/ 40606, // Rule ID 312 // |
16799 |
GIM_Try, /*On fail goto*//*Label 1032*/ 40606, // Rule ID 312 // |
| 16800 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16800 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16801 |
// MIs[0] Operand 1 |
16801 |
// MIs[0] Operand 1 |
| 16802 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE, |
16802 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE, |
| 16803 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
16803 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 16804 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
16804 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 16805 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
16805 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 16806 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_D, |
16806 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_D, |
| 16807 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16807 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16808 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16808 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16809 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16809 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16810 |
GIR_EraseFromParent, /*InsnID*/0, |
16810 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16811 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16811 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16812 |
// GIR_Coverage, 312, |
16812 |
// GIR_Coverage, 312, |
| 16813 |
GIR_Done, |
16813 |
GIR_Done, |
| 16814 |
// Label 1032: @40606 |
16814 |
// Label 1032: @40606 |
| 16815 |
GIM_Try, /*On fail goto*//*Label 1033*/ 40642, // Rule ID 313 // |
16815 |
GIM_Try, /*On fail goto*//*Label 1033*/ 40642, // Rule ID 313 // |
| 16816 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
16816 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 16817 |
// MIs[0] Operand 1 |
16817 |
// MIs[0] Operand 1 |
| 16818 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, |
16818 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, |
| 16819 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
16819 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 16820 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
16820 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 16821 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
16821 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 16822 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_D, |
16822 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_D, |
| 16823 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16823 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16824 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16824 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16825 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16825 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16826 |
GIR_EraseFromParent, /*InsnID*/0, |
16826 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16827 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16827 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16828 |
// GIR_Coverage, 313, |
16828 |
// GIR_Coverage, 313, |
| 16829 |
GIR_Done, |
16829 |
GIR_Done, |
| 16830 |
// Label 1033: @40642 |
16830 |
// Label 1033: @40642 |
| 16831 |
GIM_Reject, |
16831 |
GIM_Reject, |
| 16832 |
// Label 1026: @40643 |
16832 |
// Label 1026: @40643 |
| 16833 |
GIM_Reject, |
16833 |
GIM_Reject, |
| 16834 |
// Label 1017: @40644 |
16834 |
// Label 1017: @40644 |
| 16835 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1036*/ 41180, |
16835 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1036*/ 41180, |
| 16836 |
/*GILLT_s32*//*Label 1034*/ 40652, |
16836 |
/*GILLT_s32*//*Label 1034*/ 40652, |
| 16837 |
/*GILLT_s64*//*Label 1035*/ 40916, |
16837 |
/*GILLT_s64*//*Label 1035*/ 40916, |
| 16838 |
// Label 1034: @40652 |
16838 |
// Label 1034: @40652 |
| 16839 |
GIM_Try, /*On fail goto*//*Label 1037*/ 40915, |
16839 |
GIM_Try, /*On fail goto*//*Label 1037*/ 40915, |
| 16840 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
16840 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 16841 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID, |
16841 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID, |
| 16842 |
GIM_Try, /*On fail goto*//*Label 1038*/ 40698, // Rule ID 1181 // |
16842 |
GIM_Try, /*On fail goto*//*Label 1038*/ 40698, // Rule ID 1181 // |
| 16843 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
16843 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 16844 |
// MIs[0] Operand 1 |
16844 |
// MIs[0] Operand 1 |
| 16845 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, |
16845 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, |
| 16846 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16846 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16847 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16847 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16848 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16848 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16849 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_S_MMR6, |
16849 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_S_MMR6, |
| 16850 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16850 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16851 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16851 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16852 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16852 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16853 |
GIR_EraseFromParent, /*InsnID*/0, |
16853 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16854 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16854 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16855 |
// GIR_Coverage, 1181, |
16855 |
// GIR_Coverage, 1181, |
| 16856 |
GIR_Done, |
16856 |
GIR_Done, |
| 16857 |
// Label 1038: @40698 |
16857 |
// Label 1038: @40698 |
| 16858 |
GIM_Try, /*On fail goto*//*Label 1039*/ 40734, // Rule ID 1182 // |
16858 |
GIM_Try, /*On fail goto*//*Label 1039*/ 40734, // Rule ID 1182 // |
| 16859 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
16859 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 16860 |
// MIs[0] Operand 1 |
16860 |
// MIs[0] Operand 1 |
| 16861 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ, |
16861 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ, |
| 16862 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16862 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16863 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16863 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16864 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16864 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16865 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_S_MMR6, |
16865 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_S_MMR6, |
| 16866 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16866 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16867 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16867 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16868 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16868 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16869 |
GIR_EraseFromParent, /*InsnID*/0, |
16869 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16870 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16870 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16871 |
// GIR_Coverage, 1182, |
16871 |
// GIR_Coverage, 1182, |
| 16872 |
GIR_Done, |
16872 |
GIR_Done, |
| 16873 |
// Label 1039: @40734 |
16873 |
// Label 1039: @40734 |
| 16874 |
GIM_Try, /*On fail goto*//*Label 1040*/ 40770, // Rule ID 1183 // |
16874 |
GIM_Try, /*On fail goto*//*Label 1040*/ 40770, // Rule ID 1183 // |
| 16875 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
16875 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 16876 |
// MIs[0] Operand 1 |
16876 |
// MIs[0] Operand 1 |
| 16877 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ, |
16877 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ, |
| 16878 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16878 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16879 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16879 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16880 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16880 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16881 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_S_MMR6, |
16881 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_S_MMR6, |
| 16882 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16882 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16883 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16883 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16884 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16884 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16885 |
GIR_EraseFromParent, /*InsnID*/0, |
16885 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16886 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16886 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16887 |
// GIR_Coverage, 1183, |
16887 |
// GIR_Coverage, 1183, |
| 16888 |
GIR_Done, |
16888 |
GIR_Done, |
| 16889 |
// Label 1040: @40770 |
16889 |
// Label 1040: @40770 |
| 16890 |
GIM_Try, /*On fail goto*//*Label 1041*/ 40806, // Rule ID 1184 // |
16890 |
GIM_Try, /*On fail goto*//*Label 1041*/ 40806, // Rule ID 1184 // |
| 16891 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
16891 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 16892 |
// MIs[0] Operand 1 |
16892 |
// MIs[0] Operand 1 |
| 16893 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT, |
16893 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT, |
| 16894 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16894 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16895 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16895 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16896 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16896 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16897 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_S_MMR6, |
16897 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_S_MMR6, |
| 16898 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16898 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16899 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16899 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16900 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16900 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16901 |
GIR_EraseFromParent, /*InsnID*/0, |
16901 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16902 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16902 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16903 |
// GIR_Coverage, 1184, |
16903 |
// GIR_Coverage, 1184, |
| 16904 |
GIR_Done, |
16904 |
GIR_Done, |
| 16905 |
// Label 1041: @40806 |
16905 |
// Label 1041: @40806 |
| 16906 |
GIM_Try, /*On fail goto*//*Label 1042*/ 40842, // Rule ID 1185 // |
16906 |
GIM_Try, /*On fail goto*//*Label 1042*/ 40842, // Rule ID 1185 // |
| 16907 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
16907 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 16908 |
// MIs[0] Operand 1 |
16908 |
// MIs[0] Operand 1 |
| 16909 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT, |
16909 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT, |
| 16910 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16910 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16911 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16911 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16912 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16912 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16913 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_S_MMR6, |
16913 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_S_MMR6, |
| 16914 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16914 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16915 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16915 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16916 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16916 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16917 |
GIR_EraseFromParent, /*InsnID*/0, |
16917 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16918 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16918 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16919 |
// GIR_Coverage, 1185, |
16919 |
// GIR_Coverage, 1185, |
| 16920 |
GIR_Done, |
16920 |
GIR_Done, |
| 16921 |
// Label 1042: @40842 |
16921 |
// Label 1042: @40842 |
| 16922 |
GIM_Try, /*On fail goto*//*Label 1043*/ 40878, // Rule ID 1186 // |
16922 |
GIM_Try, /*On fail goto*//*Label 1043*/ 40878, // Rule ID 1186 // |
| 16923 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
16923 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 16924 |
// MIs[0] Operand 1 |
16924 |
// MIs[0] Operand 1 |
| 16925 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE, |
16925 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE, |
| 16926 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16926 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16927 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16927 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16928 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16928 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16929 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_S_MMR6, |
16929 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_S_MMR6, |
| 16930 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16930 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16931 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16931 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16932 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16932 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16933 |
GIR_EraseFromParent, /*InsnID*/0, |
16933 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16934 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16934 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16935 |
// GIR_Coverage, 1186, |
16935 |
// GIR_Coverage, 1186, |
| 16936 |
GIR_Done, |
16936 |
GIR_Done, |
| 16937 |
// Label 1043: @40878 |
16937 |
// Label 1043: @40878 |
| 16938 |
GIM_Try, /*On fail goto*//*Label 1044*/ 40914, // Rule ID 1187 // |
16938 |
GIM_Try, /*On fail goto*//*Label 1044*/ 40914, // Rule ID 1187 // |
| 16939 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
16939 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 16940 |
// MIs[0] Operand 1 |
16940 |
// MIs[0] Operand 1 |
| 16941 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, |
16941 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, |
| 16942 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
16942 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 16943 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
16943 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 16944 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
16944 |
// (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 16945 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_S_MMR6, |
16945 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_S_MMR6, |
| 16946 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16946 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16947 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16947 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16948 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16948 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16949 |
GIR_EraseFromParent, /*InsnID*/0, |
16949 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16950 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16950 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16951 |
// GIR_Coverage, 1187, |
16951 |
// GIR_Coverage, 1187, |
| 16952 |
GIR_Done, |
16952 |
GIR_Done, |
| 16953 |
// Label 1044: @40914 |
16953 |
// Label 1044: @40914 |
| 16954 |
GIM_Reject, |
16954 |
GIM_Reject, |
| 16955 |
// Label 1037: @40915 |
16955 |
// Label 1037: @40915 |
| 16956 |
GIM_Reject, |
16956 |
GIM_Reject, |
| 16957 |
// Label 1035: @40916 |
16957 |
// Label 1035: @40916 |
| 16958 |
GIM_Try, /*On fail goto*//*Label 1045*/ 41179, |
16958 |
GIM_Try, /*On fail goto*//*Label 1045*/ 41179, |
| 16959 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
16959 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 16960 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID, |
16960 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGRCCRegClassID, |
| 16961 |
GIM_Try, /*On fail goto*//*Label 1046*/ 40962, // Rule ID 1188 // |
16961 |
GIM_Try, /*On fail goto*//*Label 1046*/ 40962, // Rule ID 1188 // |
| 16962 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
16962 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 16963 |
// MIs[0] Operand 1 |
16963 |
// MIs[0] Operand 1 |
| 16964 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, |
16964 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, |
| 16965 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
16965 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 16966 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
16966 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 16967 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
16967 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) => (CMP_UN_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 16968 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_D_MMR6, |
16968 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UN_D_MMR6, |
| 16969 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16969 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16970 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16970 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16971 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16971 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16972 |
GIR_EraseFromParent, /*InsnID*/0, |
16972 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16973 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16973 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16974 |
// GIR_Coverage, 1188, |
16974 |
// GIR_Coverage, 1188, |
| 16975 |
GIR_Done, |
16975 |
GIR_Done, |
| 16976 |
// Label 1046: @40962 |
16976 |
// Label 1046: @40962 |
| 16977 |
GIM_Try, /*On fail goto*//*Label 1047*/ 40998, // Rule ID 1189 // |
16977 |
GIM_Try, /*On fail goto*//*Label 1047*/ 40998, // Rule ID 1189 // |
| 16978 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
16978 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 16979 |
// MIs[0] Operand 1 |
16979 |
// MIs[0] Operand 1 |
| 16980 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ, |
16980 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ, |
| 16981 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
16981 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 16982 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
16982 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 16983 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
16983 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) => (CMP_EQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 16984 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_D_MMR6, |
16984 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_D_MMR6, |
| 16985 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
16985 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 16986 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
16986 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 16987 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
16987 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 16988 |
GIR_EraseFromParent, /*InsnID*/0, |
16988 |
GIR_EraseFromParent, /*InsnID*/0, |
| 16989 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
16989 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 16990 |
// GIR_Coverage, 1189, |
16990 |
// GIR_Coverage, 1189, |
| 16991 |
GIR_Done, |
16991 |
GIR_Done, |
| 16992 |
// Label 1047: @40998 |
16992 |
// Label 1047: @40998 |
| 16993 |
GIM_Try, /*On fail goto*//*Label 1048*/ 41034, // Rule ID 1190 // |
16993 |
GIM_Try, /*On fail goto*//*Label 1048*/ 41034, // Rule ID 1190 // |
| 16994 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
16994 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 16995 |
// MIs[0] Operand 1 |
16995 |
// MIs[0] Operand 1 |
| 16996 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ, |
16996 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UEQ, |
| 16997 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
16997 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 16998 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
16998 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 16999 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
16999 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) => (CMP_UEQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 17000 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_D_MMR6, |
17000 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_UEQ_D_MMR6, |
| 17001 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
17001 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 17002 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
17002 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 17003 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
17003 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 17004 |
GIR_EraseFromParent, /*InsnID*/0, |
17004 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17005 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17005 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17006 |
// GIR_Coverage, 1190, |
17006 |
// GIR_Coverage, 1190, |
| 17007 |
GIR_Done, |
17007 |
GIR_Done, |
| 17008 |
// Label 1048: @41034 |
17008 |
// Label 1048: @41034 |
| 17009 |
GIM_Try, /*On fail goto*//*Label 1049*/ 41070, // Rule ID 1191 // |
17009 |
GIM_Try, /*On fail goto*//*Label 1049*/ 41070, // Rule ID 1191 // |
| 17010 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
17010 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 17011 |
// MIs[0] Operand 1 |
17011 |
// MIs[0] Operand 1 |
| 17012 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT, |
17012 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT, |
| 17013 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
17013 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 17014 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
17014 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 17015 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
17015 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) => (CMP_LT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 17016 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_D_MMR6, |
17016 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_D_MMR6, |
| 17017 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
17017 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 17018 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
17018 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 17019 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
17019 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 17020 |
GIR_EraseFromParent, /*InsnID*/0, |
17020 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17021 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17021 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17022 |
// GIR_Coverage, 1191, |
17022 |
// GIR_Coverage, 1191, |
| 17023 |
GIR_Done, |
17023 |
GIR_Done, |
| 17024 |
// Label 1049: @41070 |
17024 |
// Label 1049: @41070 |
| 17025 |
GIM_Try, /*On fail goto*//*Label 1050*/ 41106, // Rule ID 1192 // |
17025 |
GIM_Try, /*On fail goto*//*Label 1050*/ 41106, // Rule ID 1192 // |
| 17026 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
17026 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 17027 |
// MIs[0] Operand 1 |
17027 |
// MIs[0] Operand 1 |
| 17028 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT, |
17028 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULT, |
| 17029 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
17029 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 17030 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
17030 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 17031 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
17031 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) => (CMP_ULT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 17032 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_D_MMR6, |
17032 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULT_D_MMR6, |
| 17033 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
17033 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 17034 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
17034 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 17035 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
17035 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 17036 |
GIR_EraseFromParent, /*InsnID*/0, |
17036 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17037 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17037 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17038 |
// GIR_Coverage, 1192, |
17038 |
// GIR_Coverage, 1192, |
| 17039 |
GIR_Done, |
17039 |
GIR_Done, |
| 17040 |
// Label 1050: @41106 |
17040 |
// Label 1050: @41106 |
| 17041 |
GIM_Try, /*On fail goto*//*Label 1051*/ 41142, // Rule ID 1193 // |
17041 |
GIM_Try, /*On fail goto*//*Label 1051*/ 41142, // Rule ID 1193 // |
| 17042 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
17042 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 17043 |
// MIs[0] Operand 1 |
17043 |
// MIs[0] Operand 1 |
| 17044 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE, |
17044 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE, |
| 17045 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
17045 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 17046 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
17046 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 17047 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
17047 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) => (CMP_LE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 17048 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_D_MMR6, |
17048 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_D_MMR6, |
| 17049 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
17049 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 17050 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
17050 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 17051 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
17051 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 17052 |
GIR_EraseFromParent, /*InsnID*/0, |
17052 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17053 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17053 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17054 |
// GIR_Coverage, 1193, |
17054 |
// GIR_Coverage, 1193, |
| 17055 |
GIR_Done, |
17055 |
GIR_Done, |
| 17056 |
// Label 1051: @41142 |
17056 |
// Label 1051: @41142 |
| 17057 |
GIM_Try, /*On fail goto*//*Label 1052*/ 41178, // Rule ID 1194 // |
17057 |
GIM_Try, /*On fail goto*//*Label 1052*/ 41178, // Rule ID 1194 // |
| 17058 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
17058 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 17059 |
// MIs[0] Operand 1 |
17059 |
// MIs[0] Operand 1 |
| 17060 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, |
17060 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ULE, |
| 17061 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
17061 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 17062 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
17062 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 17063 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
17063 |
// (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) => (CMP_ULE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 17064 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_D_MMR6, |
17064 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_ULE_D_MMR6, |
| 17065 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
17065 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 17066 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
17066 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fs |
| 17067 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
17067 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ft |
| 17068 |
GIR_EraseFromParent, /*InsnID*/0, |
17068 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17069 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17069 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17070 |
// GIR_Coverage, 1194, |
17070 |
// GIR_Coverage, 1194, |
| 17071 |
GIR_Done, |
17071 |
GIR_Done, |
| 17072 |
// Label 1052: @41178 |
17072 |
// Label 1052: @41178 |
| 17073 |
GIM_Reject, |
17073 |
GIM_Reject, |
| 17074 |
// Label 1045: @41179 |
17074 |
// Label 1045: @41179 |
| 17075 |
GIM_Reject, |
17075 |
GIM_Reject, |
| 17076 |
// Label 1036: @41180 |
17076 |
// Label 1036: @41180 |
| 17077 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1055*/ 41500, |
17077 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1055*/ 41500, |
| 17078 |
/*GILLT_s32*//*Label 1053*/ 41188, |
17078 |
/*GILLT_s32*//*Label 1053*/ 41188, |
| 17079 |
/*GILLT_s64*//*Label 1054*/ 41344, |
17079 |
/*GILLT_s64*//*Label 1054*/ 41344, |
| 17080 |
// Label 1053: @41188 |
17080 |
// Label 1053: @41188 |
| 17081 |
GIM_Try, /*On fail goto*//*Label 1056*/ 41343, |
17081 |
GIM_Try, /*On fail goto*//*Label 1056*/ 41343, |
| 17082 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17082 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17083 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17083 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17084 |
GIM_Try, /*On fail goto*//*Label 1057*/ 41246, // Rule ID 1723 // |
17084 |
GIM_Try, /*On fail goto*//*Label 1057*/ 41246, // Rule ID 1723 // |
| 17085 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
17085 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 17086 |
// MIs[0] Operand 1 |
17086 |
// MIs[0] Operand 1 |
| 17087 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE, |
17087 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE, |
| 17088 |
// (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UEQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] }) |
17088 |
// (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UEQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] }) |
| 17089 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17089 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17090 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_S, |
17090 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_S, |
| 17091 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17091 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17092 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
17092 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 17093 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
17093 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 17094 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17094 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17095 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
17095 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
| 17096 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17096 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17097 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17097 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17098 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
17098 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 17099 |
GIR_EraseFromParent, /*InsnID*/0, |
17099 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17100 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17100 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17101 |
// GIR_Coverage, 1723, |
17101 |
// GIR_Coverage, 1723, |
| 17102 |
GIR_Done, |
17102 |
GIR_Done, |
| 17103 |
// Label 1057: @41246 |
17103 |
// Label 1057: @41246 |
| 17104 |
GIM_Try, /*On fail goto*//*Label 1058*/ 41294, // Rule ID 1724 // |
17104 |
GIM_Try, /*On fail goto*//*Label 1058*/ 41294, // Rule ID 1724 // |
| 17105 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
17105 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 17106 |
// MIs[0] Operand 1 |
17106 |
// MIs[0] Operand 1 |
| 17107 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, |
17107 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, |
| 17108 |
// (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UN_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] }) |
17108 |
// (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UN_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] }) |
| 17109 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17109 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17110 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_S, |
17110 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_S, |
| 17111 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17111 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17112 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
17112 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 17113 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
17113 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 17114 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17114 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17115 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
17115 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
| 17116 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17116 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17117 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17117 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17118 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
17118 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 17119 |
GIR_EraseFromParent, /*InsnID*/0, |
17119 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17120 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17120 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17121 |
// GIR_Coverage, 1724, |
17121 |
// GIR_Coverage, 1724, |
| 17122 |
GIR_Done, |
17122 |
GIR_Done, |
| 17123 |
// Label 1058: @41294 |
17123 |
// Label 1058: @41294 |
| 17124 |
GIM_Try, /*On fail goto*//*Label 1059*/ 41342, // Rule ID 1725 // |
17124 |
GIM_Try, /*On fail goto*//*Label 1059*/ 41342, // Rule ID 1725 // |
| 17125 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
17125 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 17126 |
// MIs[0] Operand 1 |
17126 |
// MIs[0] Operand 1 |
| 17127 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, |
17127 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, |
| 17128 |
// (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_EQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] }) |
17128 |
// (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_EQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] }) |
| 17129 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17129 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17130 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_S, |
17130 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_S, |
| 17131 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17131 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17132 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
17132 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 17133 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
17133 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 17134 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17134 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17135 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
17135 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
| 17136 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17136 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17137 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17137 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17138 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
17138 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 17139 |
GIR_EraseFromParent, /*InsnID*/0, |
17139 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17140 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17140 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17141 |
// GIR_Coverage, 1725, |
17141 |
// GIR_Coverage, 1725, |
| 17142 |
GIR_Done, |
17142 |
GIR_Done, |
| 17143 |
// Label 1059: @41342 |
17143 |
// Label 1059: @41342 |
| 17144 |
GIM_Reject, |
17144 |
GIM_Reject, |
| 17145 |
// Label 1056: @41343 |
17145 |
// Label 1056: @41343 |
| 17146 |
GIM_Reject, |
17146 |
GIM_Reject, |
| 17147 |
// Label 1054: @41344 |
17147 |
// Label 1054: @41344 |
| 17148 |
GIM_Try, /*On fail goto*//*Label 1060*/ 41499, |
17148 |
GIM_Try, /*On fail goto*//*Label 1060*/ 41499, |
| 17149 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
17149 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 17150 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17150 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17151 |
GIM_Try, /*On fail goto*//*Label 1061*/ 41402, // Rule ID 1732 // |
17151 |
GIM_Try, /*On fail goto*//*Label 1061*/ 41402, // Rule ID 1732 // |
| 17152 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
17152 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 17153 |
// MIs[0] Operand 1 |
17153 |
// MIs[0] Operand 1 |
| 17154 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE, |
17154 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE, |
| 17155 |
// (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UEQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] }) |
17155 |
// (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UEQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] }) |
| 17156 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17156 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17157 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_D, |
17157 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_D, |
| 17158 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17158 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17159 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
17159 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 17160 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
17160 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 17161 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17161 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17162 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
17162 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
| 17163 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17163 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17164 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17164 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17165 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
17165 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 17166 |
GIR_EraseFromParent, /*InsnID*/0, |
17166 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17167 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17167 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17168 |
// GIR_Coverage, 1732, |
17168 |
// GIR_Coverage, 1732, |
| 17169 |
GIR_Done, |
17169 |
GIR_Done, |
| 17170 |
// Label 1061: @41402 |
17170 |
// Label 1061: @41402 |
| 17171 |
GIM_Try, /*On fail goto*//*Label 1062*/ 41450, // Rule ID 1733 // |
17171 |
GIM_Try, /*On fail goto*//*Label 1062*/ 41450, // Rule ID 1733 // |
| 17172 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
17172 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 17173 |
// MIs[0] Operand 1 |
17173 |
// MIs[0] Operand 1 |
| 17174 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, |
17174 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, |
| 17175 |
// (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UN_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] }) |
17175 |
// (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_UN_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] }) |
| 17176 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17176 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17177 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_D, |
17177 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_D, |
| 17178 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17178 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17179 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
17179 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 17180 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
17180 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 17181 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17181 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17182 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
17182 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
| 17183 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17183 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17184 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17184 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17185 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
17185 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 17186 |
GIR_EraseFromParent, /*InsnID*/0, |
17186 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17187 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17187 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17188 |
// GIR_Coverage, 1733, |
17188 |
// GIR_Coverage, 1733, |
| 17189 |
GIR_Done, |
17189 |
GIR_Done, |
| 17190 |
// Label 1062: @41450 |
17190 |
// Label 1062: @41450 |
| 17191 |
GIM_Try, /*On fail goto*//*Label 1063*/ 41498, // Rule ID 1734 // |
17191 |
GIM_Try, /*On fail goto*//*Label 1063*/ 41498, // Rule ID 1734 // |
| 17192 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
17192 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 17193 |
// MIs[0] Operand 1 |
17193 |
// MIs[0] Operand 1 |
| 17194 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, |
17194 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, |
| 17195 |
// (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_EQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] }) |
17195 |
// (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] }) => (NOR:{ *:[i32] } (CMP_EQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] }) |
| 17196 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17196 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17197 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_D, |
17197 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_D, |
| 17198 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17198 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17199 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
17199 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 17200 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
17200 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 17201 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17201 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17202 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
17202 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR, |
| 17203 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17203 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17204 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17204 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17205 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
17205 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 17206 |
GIR_EraseFromParent, /*InsnID*/0, |
17206 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17207 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17207 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17208 |
// GIR_Coverage, 1734, |
17208 |
// GIR_Coverage, 1734, |
| 17209 |
GIR_Done, |
17209 |
GIR_Done, |
| 17210 |
// Label 1063: @41498 |
17210 |
// Label 1063: @41498 |
| 17211 |
GIM_Reject, |
17211 |
GIM_Reject, |
| 17212 |
// Label 1060: @41499 |
17212 |
// Label 1060: @41499 |
| 17213 |
GIM_Reject, |
17213 |
GIM_Reject, |
| 17214 |
// Label 1055: @41500 |
17214 |
// Label 1055: @41500 |
| 17215 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1066*/ 41820, |
17215 |
GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/1, 3, /*)*//*default:*//*Label 1066*/ 41820, |
| 17216 |
/*GILLT_s32*//*Label 1064*/ 41508, |
17216 |
/*GILLT_s32*//*Label 1064*/ 41508, |
| 17217 |
/*GILLT_s64*//*Label 1065*/ 41664, |
17217 |
/*GILLT_s64*//*Label 1065*/ 41664, |
| 17218 |
// Label 1064: @41508 |
17218 |
// Label 1064: @41508 |
| 17219 |
GIM_Try, /*On fail goto*//*Label 1067*/ 41663, |
17219 |
GIM_Try, /*On fail goto*//*Label 1067*/ 41663, |
| 17220 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17220 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17221 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17221 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17222 |
GIM_Try, /*On fail goto*//*Label 1068*/ 41566, // Rule ID 2263 // |
17222 |
GIM_Try, /*On fail goto*//*Label 1068*/ 41566, // Rule ID 2263 // |
| 17223 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
17223 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 17224 |
// MIs[0] Operand 1 |
17224 |
// MIs[0] Operand 1 |
| 17225 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE, |
17225 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE, |
| 17226 |
// (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UEQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] }) |
17226 |
// (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UEQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] }) |
| 17227 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17227 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17228 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_S_MMR6, |
17228 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_S_MMR6, |
| 17229 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17229 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17230 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
17230 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 17231 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
17231 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 17232 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17232 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17233 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
17233 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
| 17234 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17234 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17235 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17235 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17236 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
17236 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 17237 |
GIR_EraseFromParent, /*InsnID*/0, |
17237 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17238 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17238 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17239 |
// GIR_Coverage, 2263, |
17239 |
// GIR_Coverage, 2263, |
| 17240 |
GIR_Done, |
17240 |
GIR_Done, |
| 17241 |
// Label 1068: @41566 |
17241 |
// Label 1068: @41566 |
| 17242 |
GIM_Try, /*On fail goto*//*Label 1069*/ 41614, // Rule ID 2264 // |
17242 |
GIM_Try, /*On fail goto*//*Label 1069*/ 41614, // Rule ID 2264 // |
| 17243 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
17243 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 17244 |
// MIs[0] Operand 1 |
17244 |
// MIs[0] Operand 1 |
| 17245 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, |
17245 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, |
| 17246 |
// (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UN_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] }) |
17246 |
// (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UN_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] }) |
| 17247 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17247 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17248 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_S_MMR6, |
17248 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_S_MMR6, |
| 17249 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17249 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17250 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
17250 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 17251 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
17251 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 17252 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17252 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17253 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
17253 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
| 17254 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17254 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17255 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17255 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17256 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
17256 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 17257 |
GIR_EraseFromParent, /*InsnID*/0, |
17257 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17258 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17258 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17259 |
// GIR_Coverage, 2264, |
17259 |
// GIR_Coverage, 2264, |
| 17260 |
GIR_Done, |
17260 |
GIR_Done, |
| 17261 |
// Label 1069: @41614 |
17261 |
// Label 1069: @41614 |
| 17262 |
GIM_Try, /*On fail goto*//*Label 1070*/ 41662, // Rule ID 2265 // |
17262 |
GIM_Try, /*On fail goto*//*Label 1070*/ 41662, // Rule ID 2265 // |
| 17263 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
17263 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 17264 |
// MIs[0] Operand 1 |
17264 |
// MIs[0] Operand 1 |
| 17265 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, |
17265 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, |
| 17266 |
// (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_EQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] }) |
17266 |
// (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_EQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] }) |
| 17267 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17267 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17268 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_S_MMR6, |
17268 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_S_MMR6, |
| 17269 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17269 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17270 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
17270 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 17271 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
17271 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 17272 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17272 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17273 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
17273 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
| 17274 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17274 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17275 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17275 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17276 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
17276 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 17277 |
GIR_EraseFromParent, /*InsnID*/0, |
17277 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17278 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17278 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17279 |
// GIR_Coverage, 2265, |
17279 |
// GIR_Coverage, 2265, |
| 17280 |
GIR_Done, |
17280 |
GIR_Done, |
| 17281 |
// Label 1070: @41662 |
17281 |
// Label 1070: @41662 |
| 17282 |
GIM_Reject, |
17282 |
GIM_Reject, |
| 17283 |
// Label 1067: @41663 |
17283 |
// Label 1067: @41663 |
| 17284 |
GIM_Reject, |
17284 |
GIM_Reject, |
| 17285 |
// Label 1065: @41664 |
17285 |
// Label 1065: @41664 |
| 17286 |
GIM_Try, /*On fail goto*//*Label 1071*/ 41819, |
17286 |
GIM_Try, /*On fail goto*//*Label 1071*/ 41819, |
| 17287 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
17287 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 17288 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17288 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17289 |
GIM_Try, /*On fail goto*//*Label 1072*/ 41722, // Rule ID 2272 // |
17289 |
GIM_Try, /*On fail goto*//*Label 1072*/ 41722, // Rule ID 2272 // |
| 17290 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
17290 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 17291 |
// MIs[0] Operand 1 |
17291 |
// MIs[0] Operand 1 |
| 17292 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE, |
17292 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ONE, |
| 17293 |
// (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UEQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] }) |
17293 |
// (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UEQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] }) |
| 17294 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17294 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17295 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_D_MMR6, |
17295 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UEQ_D_MMR6, |
| 17296 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17296 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17297 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
17297 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 17298 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
17298 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 17299 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17299 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17300 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
17300 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
| 17301 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17301 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17302 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17302 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17303 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
17303 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 17304 |
GIR_EraseFromParent, /*InsnID*/0, |
17304 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17305 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17305 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17306 |
// GIR_Coverage, 2272, |
17306 |
// GIR_Coverage, 2272, |
| 17307 |
GIR_Done, |
17307 |
GIR_Done, |
| 17308 |
// Label 1072: @41722 |
17308 |
// Label 1072: @41722 |
| 17309 |
GIM_Try, /*On fail goto*//*Label 1073*/ 41770, // Rule ID 2273 // |
17309 |
GIM_Try, /*On fail goto*//*Label 1073*/ 41770, // Rule ID 2273 // |
| 17310 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
17310 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 17311 |
// MIs[0] Operand 1 |
17311 |
// MIs[0] Operand 1 |
| 17312 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, |
17312 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, |
| 17313 |
// (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UN_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] }) |
17313 |
// (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_UN_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] }) |
| 17314 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17314 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17315 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_D_MMR6, |
17315 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_UN_D_MMR6, |
| 17316 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17316 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17317 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
17317 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 17318 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
17318 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 17319 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17319 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17320 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
17320 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
| 17321 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17321 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17322 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17322 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17323 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
17323 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 17324 |
GIR_EraseFromParent, /*InsnID*/0, |
17324 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17325 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17325 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17326 |
// GIR_Coverage, 2273, |
17326 |
// GIR_Coverage, 2273, |
| 17327 |
GIR_Done, |
17327 |
GIR_Done, |
| 17328 |
// Label 1073: @41770 |
17328 |
// Label 1073: @41770 |
| 17329 |
GIM_Try, /*On fail goto*//*Label 1074*/ 41818, // Rule ID 2274 // |
17329 |
GIM_Try, /*On fail goto*//*Label 1074*/ 41818, // Rule ID 2274 // |
| 17330 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
17330 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 17331 |
// MIs[0] Operand 1 |
17331 |
// MIs[0] Operand 1 |
| 17332 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, |
17332 |
GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE, |
| 17333 |
// (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_EQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] }) |
17333 |
// (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] }) => (NOR_MMR6:{ *:[i32] } (CMP_EQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] }) |
| 17334 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17334 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17335 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_D_MMR6, |
17335 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::CMP_EQ_D_MMR6, |
| 17336 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17336 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17337 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
17337 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs |
| 17338 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
17338 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs |
| 17339 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17339 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17340 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
17340 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6, |
| 17341 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17341 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17342 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17342 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17343 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
17343 |
GIR_AddRegister, /*InsnID*/0, Mips::ZERO, /*AddRegisterRegFlags*/0, |
| 17344 |
GIR_EraseFromParent, /*InsnID*/0, |
17344 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17345 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17345 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17346 |
// GIR_Coverage, 2274, |
17346 |
// GIR_Coverage, 2274, |
| 17347 |
GIR_Done, |
17347 |
GIR_Done, |
| 17348 |
// Label 1074: @41818 |
17348 |
// Label 1074: @41818 |
| 17349 |
GIM_Reject, |
17349 |
GIM_Reject, |
| 17350 |
// Label 1071: @41819 |
17350 |
// Label 1071: @41819 |
| 17351 |
GIM_Reject, |
17351 |
GIM_Reject, |
| 17352 |
// Label 1066: @41820 |
17352 |
// Label 1066: @41820 |
| 17353 |
GIM_Reject, |
17353 |
GIM_Reject, |
| 17354 |
// Label 1014: @41821 |
17354 |
// Label 1014: @41821 |
| 17355 |
GIM_Reject, |
17355 |
GIM_Reject, |
| 17356 |
// Label 29: @41822 |
17356 |
// Label 29: @41822 |
| 17357 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1077*/ 54101, |
17357 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1077*/ 54101, |
| 17358 |
/*GILLT_s32*//*Label 1075*/ 41830, |
17358 |
/*GILLT_s32*//*Label 1075*/ 41830, |
| 17359 |
/*GILLT_s64*//*Label 1076*/ 48847, |
17359 |
/*GILLT_s64*//*Label 1076*/ 48847, |
| 17360 |
// Label 1075: @41830 |
17360 |
// Label 1075: @41830 |
| 17361 |
GIM_Try, /*On fail goto*//*Label 1078*/ 41911, // Rule ID 1611 // |
17361 |
GIM_Try, /*On fail goto*//*Label 1078*/ 41911, // Rule ID 1611 // |
| 17362 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
17362 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17363 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17363 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17364 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17364 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17365 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17365 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17366 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17366 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17367 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17367 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17368 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17368 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17369 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17369 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17370 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17370 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17371 |
// MIs[1] Operand 1 |
17371 |
// MIs[1] Operand 1 |
| 17372 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
17372 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 17373 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17373 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17374 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17374 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17375 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17375 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17376 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17376 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17377 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17377 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17378 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F) |
17378 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F) |
| 17379 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
17379 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
| 17380 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17380 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17381 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17381 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17382 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17382 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17383 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17383 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17384 |
GIR_EraseFromParent, /*InsnID*/0, |
17384 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17385 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17385 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17386 |
// GIR_Coverage, 1611, |
17386 |
// GIR_Coverage, 1611, |
| 17387 |
GIR_Done, |
17387 |
GIR_Done, |
| 17388 |
// Label 1078: @41911 |
17388 |
// Label 1078: @41911 |
| 17389 |
GIM_Try, /*On fail goto*//*Label 1079*/ 41992, // Rule ID 1615 // |
17389 |
GIM_Try, /*On fail goto*//*Label 1079*/ 41992, // Rule ID 1615 // |
| 17390 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
17390 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17391 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17391 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17392 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17392 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17393 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17393 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17394 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17394 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17395 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17395 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17396 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17396 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17397 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17397 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17398 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17398 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17399 |
// MIs[1] Operand 1 |
17399 |
// MIs[1] Operand 1 |
| 17400 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
17400 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 17401 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17401 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17402 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17402 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17403 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17403 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17404 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17404 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17405 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17405 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17406 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F) |
17406 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F) |
| 17407 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I, |
17407 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I, |
| 17408 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17408 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17409 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17409 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17410 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17410 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17411 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17411 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17412 |
GIR_EraseFromParent, /*InsnID*/0, |
17412 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17413 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17413 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17414 |
// GIR_Coverage, 1615, |
17414 |
// GIR_Coverage, 1615, |
| 17415 |
GIR_Done, |
17415 |
GIR_Done, |
| 17416 |
// Label 1079: @41992 |
17416 |
// Label 1079: @41992 |
| 17417 |
GIM_Try, /*On fail goto*//*Label 1080*/ 42073, // Rule ID 1643 // |
17417 |
GIM_Try, /*On fail goto*//*Label 1080*/ 42073, // Rule ID 1643 // |
| 17418 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
17418 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17419 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17419 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17420 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17420 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17421 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17421 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17422 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17422 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17423 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17423 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17424 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17424 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17425 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
17425 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 17426 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
17426 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 17427 |
// MIs[1] Operand 1 |
17427 |
// MIs[1] Operand 1 |
| 17428 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
17428 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 17429 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
17429 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 17430 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17430 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17431 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17431 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17432 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17432 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17433 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17433 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17434 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F) |
17434 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F) |
| 17435 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I, |
17435 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I, |
| 17436 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17436 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17437 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17437 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17438 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17438 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17439 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17439 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17440 |
GIR_EraseFromParent, /*InsnID*/0, |
17440 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17441 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17441 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17442 |
// GIR_Coverage, 1643, |
17442 |
// GIR_Coverage, 1643, |
| 17443 |
GIR_Done, |
17443 |
GIR_Done, |
| 17444 |
// Label 1080: @42073 |
17444 |
// Label 1080: @42073 |
| 17445 |
GIM_Try, /*On fail goto*//*Label 1081*/ 42154, // Rule ID 1654 // |
17445 |
GIM_Try, /*On fail goto*//*Label 1081*/ 42154, // Rule ID 1654 // |
| 17446 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
17446 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17447 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17447 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17448 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17448 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17449 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17449 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17450 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17450 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17451 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17451 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17452 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17452 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17453 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
17453 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 17454 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
17454 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 17455 |
// MIs[1] Operand 1 |
17455 |
// MIs[1] Operand 1 |
| 17456 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
17456 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 17457 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
17457 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 17458 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17458 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17459 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17459 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17460 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17460 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17461 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17461 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17462 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F) |
17462 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F) |
| 17463 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I, |
17463 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I, |
| 17464 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17464 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17465 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17465 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17466 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17466 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17467 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17467 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17468 |
GIR_EraseFromParent, /*InsnID*/0, |
17468 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17469 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17469 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17470 |
// GIR_Coverage, 1654, |
17470 |
// GIR_Coverage, 1654, |
| 17471 |
GIR_Done, |
17471 |
GIR_Done, |
| 17472 |
// Label 1081: @42154 |
17472 |
// Label 1081: @42154 |
| 17473 |
GIM_Try, /*On fail goto*//*Label 1082*/ 42235, // Rule ID 1667 // |
17473 |
GIM_Try, /*On fail goto*//*Label 1082*/ 42235, // Rule ID 1667 // |
| 17474 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
17474 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17475 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17475 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17476 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17476 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17477 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17477 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17478 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
17478 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 17479 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17479 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17480 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17480 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17481 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17481 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17482 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17482 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17483 |
// MIs[1] Operand 1 |
17483 |
// MIs[1] Operand 1 |
| 17484 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
17484 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 17485 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17485 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17486 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17486 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17487 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
17487 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 17488 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
17488 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 17489 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17489 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17490 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F) |
17490 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F) |
| 17491 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
17491 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
| 17492 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
17492 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 17493 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17493 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17494 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17494 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17495 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17495 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17496 |
GIR_EraseFromParent, /*InsnID*/0, |
17496 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17497 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17497 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17498 |
// GIR_Coverage, 1667, |
17498 |
// GIR_Coverage, 1667, |
| 17499 |
GIR_Done, |
17499 |
GIR_Done, |
| 17500 |
// Label 1082: @42235 |
17500 |
// Label 1082: @42235 |
| 17501 |
GIM_Try, /*On fail goto*//*Label 1083*/ 42316, // Rule ID 1670 // |
17501 |
GIM_Try, /*On fail goto*//*Label 1083*/ 42316, // Rule ID 1670 // |
| 17502 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
17502 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17503 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17503 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17504 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17504 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17505 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17505 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17506 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
17506 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 17507 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17507 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17508 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17508 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17509 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17509 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17510 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17510 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17511 |
// MIs[1] Operand 1 |
17511 |
// MIs[1] Operand 1 |
| 17512 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
17512 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 17513 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17513 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17514 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17514 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17515 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
17515 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 17516 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
17516 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 17517 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17517 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17518 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F) |
17518 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F) |
| 17519 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S, |
17519 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S, |
| 17520 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
17520 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 17521 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17521 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17522 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17522 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17523 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17523 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17524 |
GIR_EraseFromParent, /*InsnID*/0, |
17524 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17525 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17525 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17526 |
// GIR_Coverage, 1670, |
17526 |
// GIR_Coverage, 1670, |
| 17527 |
GIR_Done, |
17527 |
GIR_Done, |
| 17528 |
// Label 1083: @42316 |
17528 |
// Label 1083: @42316 |
| 17529 |
GIM_Try, /*On fail goto*//*Label 1084*/ 42397, // Rule ID 1680 // |
17529 |
GIM_Try, /*On fail goto*//*Label 1084*/ 42397, // Rule ID 1680 // |
| 17530 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
17530 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17531 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17531 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17532 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17532 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17533 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17533 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17534 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
17534 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 17535 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17535 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17536 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17536 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17537 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
17537 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 17538 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
17538 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 17539 |
// MIs[1] Operand 1 |
17539 |
// MIs[1] Operand 1 |
| 17540 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
17540 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 17541 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
17541 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 17542 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17542 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17543 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
17543 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 17544 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
17544 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 17545 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17545 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17546 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F) |
17546 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F) |
| 17547 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_S, |
17547 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_S, |
| 17548 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
17548 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 17549 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17549 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17550 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17550 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17551 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17551 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17552 |
GIR_EraseFromParent, /*InsnID*/0, |
17552 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17553 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17553 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17554 |
// GIR_Coverage, 1680, |
17554 |
// GIR_Coverage, 1680, |
| 17555 |
GIR_Done, |
17555 |
GIR_Done, |
| 17556 |
// Label 1084: @42397 |
17556 |
// Label 1084: @42397 |
| 17557 |
GIM_Try, /*On fail goto*//*Label 1085*/ 42478, // Rule ID 1683 // |
17557 |
GIM_Try, /*On fail goto*//*Label 1085*/ 42478, // Rule ID 1683 // |
| 17558 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
17558 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17559 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17559 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17560 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17560 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17561 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17561 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17562 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
17562 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 17563 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17563 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17564 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17564 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17565 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
17565 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 17566 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
17566 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 17567 |
// MIs[1] Operand 1 |
17567 |
// MIs[1] Operand 1 |
| 17568 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
17568 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 17569 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
17569 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 17570 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17570 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17571 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
17571 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 17572 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
17572 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 17573 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17573 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17574 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F) |
17574 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F) |
| 17575 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S, |
17575 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S, |
| 17576 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
17576 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 17577 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17577 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17578 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17578 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17579 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17579 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17580 |
GIR_EraseFromParent, /*InsnID*/0, |
17580 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17581 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17581 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17582 |
// GIR_Coverage, 1683, |
17582 |
// GIR_Coverage, 1683, |
| 17583 |
GIR_Done, |
17583 |
GIR_Done, |
| 17584 |
// Label 1085: @42478 |
17584 |
// Label 1085: @42478 |
| 17585 |
GIM_Try, /*On fail goto*//*Label 1086*/ 42559, // Rule ID 1836 // |
17585 |
GIM_Try, /*On fail goto*//*Label 1086*/ 42559, // Rule ID 1836 // |
| 17586 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
17586 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 17587 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17587 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17588 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17588 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17589 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17589 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17590 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
17590 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 17591 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17591 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17592 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17592 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17593 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17593 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17594 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17594 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17595 |
// MIs[1] Operand 1 |
17595 |
// MIs[1] Operand 1 |
| 17596 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
17596 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 17597 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
17597 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 17598 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17598 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17599 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
17599 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 17600 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
17600 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 17601 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17601 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17602 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBeqZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a) |
17602 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBeqZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a) |
| 17603 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBeqZ, |
17603 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBeqZ, |
| 17604 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
17604 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
| 17605 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
17605 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
| 17606 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
17606 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
| 17607 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
17607 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
| 17608 |
GIR_EraseFromParent, /*InsnID*/0, |
17608 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17609 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17609 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17610 |
// GIR_Coverage, 1836, |
17610 |
// GIR_Coverage, 1836, |
| 17611 |
GIR_Done, |
17611 |
GIR_Done, |
| 17612 |
// Label 1086: @42559 |
17612 |
// Label 1086: @42559 |
| 17613 |
GIM_Try, /*On fail goto*//*Label 1087*/ 42640, // Rule ID 1839 // |
17613 |
GIM_Try, /*On fail goto*//*Label 1087*/ 42640, // Rule ID 1839 // |
| 17614 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
17614 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 17615 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17615 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17616 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17616 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17617 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17617 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17618 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
17618 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 17619 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17619 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17620 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17620 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17621 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17621 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17622 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17622 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17623 |
// MIs[1] Operand 1 |
17623 |
// MIs[1] Operand 1 |
| 17624 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
17624 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 17625 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
17625 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 17626 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17626 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17627 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
17627 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 17628 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
17628 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 17629 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17629 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17630 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a) |
17630 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a) |
| 17631 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBneZ, |
17631 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBneZ, |
| 17632 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
17632 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
| 17633 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
17633 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
| 17634 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
17634 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
| 17635 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
17635 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
| 17636 |
GIR_EraseFromParent, /*InsnID*/0, |
17636 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17637 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17637 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17638 |
// GIR_Coverage, 1839, |
17638 |
// GIR_Coverage, 1839, |
| 17639 |
GIR_Done, |
17639 |
GIR_Done, |
| 17640 |
// Label 1087: @42640 |
17640 |
// Label 1087: @42640 |
| 17641 |
GIM_Try, /*On fail goto*//*Label 1088*/ 42721, // Rule ID 2183 // |
17641 |
GIM_Try, /*On fail goto*//*Label 1088*/ 42721, // Rule ID 2183 // |
| 17642 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
17642 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 17643 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17643 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17644 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17644 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17645 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17645 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17646 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17646 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17647 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17647 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17648 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17648 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17649 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17649 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17650 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17650 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17651 |
// MIs[1] Operand 1 |
17651 |
// MIs[1] Operand 1 |
| 17652 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
17652 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 17653 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17653 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17654 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17654 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17655 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17655 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17656 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17656 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17657 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17657 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17658 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F) |
17658 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F) |
| 17659 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
17659 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
| 17660 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17660 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17661 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17661 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17662 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17662 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17663 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17663 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17664 |
GIR_EraseFromParent, /*InsnID*/0, |
17664 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17665 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17665 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17666 |
// GIR_Coverage, 2183, |
17666 |
// GIR_Coverage, 2183, |
| 17667 |
GIR_Done, |
17667 |
GIR_Done, |
| 17668 |
// Label 1088: @42721 |
17668 |
// Label 1088: @42721 |
| 17669 |
GIM_Try, /*On fail goto*//*Label 1089*/ 42802, // Rule ID 2187 // |
17669 |
GIM_Try, /*On fail goto*//*Label 1089*/ 42802, // Rule ID 2187 // |
| 17670 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6, |
17670 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6, |
| 17671 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17671 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17672 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17672 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17673 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17673 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17674 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17674 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17675 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17675 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17676 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17676 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17677 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17677 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17678 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17678 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17679 |
// MIs[1] Operand 1 |
17679 |
// MIs[1] Operand 1 |
| 17680 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
17680 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 17681 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17681 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17682 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17682 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17683 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17683 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17684 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17684 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17685 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17685 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17686 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F) |
17686 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F) |
| 17687 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, |
17687 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, |
| 17688 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17688 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17689 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17689 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17690 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17690 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17691 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17691 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17692 |
GIR_EraseFromParent, /*InsnID*/0, |
17692 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17693 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17693 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17694 |
// GIR_Coverage, 2187, |
17694 |
// GIR_Coverage, 2187, |
| 17695 |
GIR_Done, |
17695 |
GIR_Done, |
| 17696 |
// Label 1089: @42802 |
17696 |
// Label 1089: @42802 |
| 17697 |
GIM_Try, /*On fail goto*//*Label 1090*/ 42883, // Rule ID 2197 // |
17697 |
GIM_Try, /*On fail goto*//*Label 1090*/ 42883, // Rule ID 2197 // |
| 17698 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
17698 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 17699 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17699 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17700 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17700 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17701 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17701 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17702 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17702 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17703 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17703 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17704 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17704 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17705 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17705 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17706 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17706 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17707 |
// MIs[1] Operand 1 |
17707 |
// MIs[1] Operand 1 |
| 17708 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
17708 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 17709 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17709 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17710 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17710 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17711 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17711 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17712 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17712 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17713 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17713 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17714 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F) |
17714 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F) |
| 17715 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
17715 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
| 17716 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17716 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17717 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17717 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17718 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17718 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17719 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17719 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17720 |
GIR_EraseFromParent, /*InsnID*/0, |
17720 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17721 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17721 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17722 |
// GIR_Coverage, 2197, |
17722 |
// GIR_Coverage, 2197, |
| 17723 |
GIR_Done, |
17723 |
GIR_Done, |
| 17724 |
// Label 1090: @42883 |
17724 |
// Label 1090: @42883 |
| 17725 |
GIM_Try, /*On fail goto*//*Label 1091*/ 42964, // Rule ID 2201 // |
17725 |
GIM_Try, /*On fail goto*//*Label 1091*/ 42964, // Rule ID 2201 // |
| 17726 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
17726 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 17727 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17727 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17728 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17728 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17729 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17729 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17730 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17730 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17731 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17731 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17732 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17732 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17733 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17733 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17734 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17734 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17735 |
// MIs[1] Operand 1 |
17735 |
// MIs[1] Operand 1 |
| 17736 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
17736 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 17737 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17737 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17738 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17738 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17739 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17739 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17740 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17740 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17741 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17741 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17742 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F) |
17742 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F) |
| 17743 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, |
17743 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, |
| 17744 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17744 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17745 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17745 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17746 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17746 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17747 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17747 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17748 |
GIR_EraseFromParent, /*InsnID*/0, |
17748 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17749 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17749 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17750 |
// GIR_Coverage, 2201, |
17750 |
// GIR_Coverage, 2201, |
| 17751 |
GIR_Done, |
17751 |
GIR_Done, |
| 17752 |
// Label 1091: @42964 |
17752 |
// Label 1091: @42964 |
| 17753 |
GIM_Try, /*On fail goto*//*Label 1092*/ 43045, // Rule ID 2231 // |
17753 |
GIM_Try, /*On fail goto*//*Label 1092*/ 43045, // Rule ID 2231 // |
| 17754 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
17754 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 17755 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17755 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17756 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17756 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17757 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17757 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
17758 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 17759 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17759 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17760 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17760 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17761 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17761 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17762 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17762 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17763 |
// MIs[1] Operand 1 |
17763 |
// MIs[1] Operand 1 |
| 17764 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
17764 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 17765 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17765 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17766 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17766 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17767 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
17767 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 17768 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
17768 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 17769 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17769 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17770 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F) |
17770 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F) |
| 17771 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM, |
17771 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM, |
| 17772 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
17772 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 17773 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17773 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17774 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17774 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17775 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17775 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17776 |
GIR_EraseFromParent, /*InsnID*/0, |
17776 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17777 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17777 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17778 |
// GIR_Coverage, 2231, |
17778 |
// GIR_Coverage, 2231, |
| 17779 |
GIR_Done, |
17779 |
GIR_Done, |
| 17780 |
// Label 1092: @43045 |
17780 |
// Label 1092: @43045 |
| 17781 |
GIM_Try, /*On fail goto*//*Label 1093*/ 43126, // Rule ID 2234 // |
17781 |
GIM_Try, /*On fail goto*//*Label 1093*/ 43126, // Rule ID 2234 // |
| 17782 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
17782 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 17783 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17783 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17784 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17784 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17785 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17785 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17786 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
17786 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 17787 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17787 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17788 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17788 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17789 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17789 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17790 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17790 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17791 |
// MIs[1] Operand 1 |
17791 |
// MIs[1] Operand 1 |
| 17792 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
17792 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 17793 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17793 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17794 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
17794 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 17795 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
17795 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 17796 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
17796 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 17797 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17797 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17798 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F) |
17798 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F) |
| 17799 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM, |
17799 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM, |
| 17800 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
17800 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 17801 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17801 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17802 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17802 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17803 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17803 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17804 |
GIR_EraseFromParent, /*InsnID*/0, |
17804 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17805 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17805 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17806 |
// GIR_Coverage, 2234, |
17806 |
// GIR_Coverage, 2234, |
| 17807 |
GIR_Done, |
17807 |
GIR_Done, |
| 17808 |
// Label 1093: @43126 |
17808 |
// Label 1093: @43126 |
| 17809 |
GIM_Try, /*On fail goto*//*Label 1094*/ 43227, // Rule ID 1602 // |
17809 |
GIM_Try, /*On fail goto*//*Label 1094*/ 43227, // Rule ID 1602 // |
| 17810 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
17810 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17811 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17811 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17812 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17812 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17813 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17813 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17814 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17814 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17815 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17815 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17816 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17816 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17817 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17817 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17818 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17818 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17819 |
// MIs[1] Operand 1 |
17819 |
// MIs[1] Operand 1 |
| 17820 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
17820 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 17821 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17821 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17822 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17822 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17823 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17823 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17824 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17824 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17825 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17825 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17826 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
17826 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 17827 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17827 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17828 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
17828 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
| 17829 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17829 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17830 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17830 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17831 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
17831 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 17832 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17832 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17833 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
17833 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
| 17834 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17834 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17835 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17835 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17836 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17836 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17837 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17837 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17838 |
GIR_EraseFromParent, /*InsnID*/0, |
17838 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17839 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17839 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17840 |
// GIR_Coverage, 1602, |
17840 |
// GIR_Coverage, 1602, |
| 17841 |
GIR_Done, |
17841 |
GIR_Done, |
| 17842 |
// Label 1094: @43227 |
17842 |
// Label 1094: @43227 |
| 17843 |
GIM_Try, /*On fail goto*//*Label 1095*/ 43328, // Rule ID 1603 // |
17843 |
GIM_Try, /*On fail goto*//*Label 1095*/ 43328, // Rule ID 1603 // |
| 17844 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
17844 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17845 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17845 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17846 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17846 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17847 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17847 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17848 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17848 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17849 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17849 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17850 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17850 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17851 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17851 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17852 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17852 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17853 |
// MIs[1] Operand 1 |
17853 |
// MIs[1] Operand 1 |
| 17854 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
17854 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 17855 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17855 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17856 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17856 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17857 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17857 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17858 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17858 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17859 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17859 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17860 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
17860 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 17861 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17861 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17862 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
17862 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
| 17863 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17863 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17864 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17864 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17865 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
17865 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 17866 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17866 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17867 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
17867 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
| 17868 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17868 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17869 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17869 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17870 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17870 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17871 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17871 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17872 |
GIR_EraseFromParent, /*InsnID*/0, |
17872 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17873 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17873 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17874 |
// GIR_Coverage, 1603, |
17874 |
// GIR_Coverage, 1603, |
| 17875 |
GIR_Done, |
17875 |
GIR_Done, |
| 17876 |
// Label 1095: @43328 |
17876 |
// Label 1095: @43328 |
| 17877 |
GIM_Try, /*On fail goto*//*Label 1096*/ 43429, // Rule ID 1606 // |
17877 |
GIM_Try, /*On fail goto*//*Label 1096*/ 43429, // Rule ID 1606 // |
| 17878 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
17878 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17879 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17879 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17880 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17880 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17881 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17881 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17882 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17882 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17883 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17883 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17884 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17884 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17885 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17885 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17886 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17886 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17887 |
// MIs[1] Operand 1 |
17887 |
// MIs[1] Operand 1 |
| 17888 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
17888 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 17889 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17889 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17890 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17890 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17891 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17891 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17892 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17892 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17893 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17893 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17894 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F) |
17894 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F) |
| 17895 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17895 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17896 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
17896 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
| 17897 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17897 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17898 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
17898 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 17899 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17899 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17900 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17900 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17901 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
17901 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
| 17902 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17902 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17903 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17903 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17904 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17904 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17905 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17905 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17906 |
GIR_EraseFromParent, /*InsnID*/0, |
17906 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17907 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17907 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17908 |
// GIR_Coverage, 1606, |
17908 |
// GIR_Coverage, 1606, |
| 17909 |
GIR_Done, |
17909 |
GIR_Done, |
| 17910 |
// Label 1096: @43429 |
17910 |
// Label 1096: @43429 |
| 17911 |
GIM_Try, /*On fail goto*//*Label 1097*/ 43530, // Rule ID 1607 // |
17911 |
GIM_Try, /*On fail goto*//*Label 1097*/ 43530, // Rule ID 1607 // |
| 17912 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
17912 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17913 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17913 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17914 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17914 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17915 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17915 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17916 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17916 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17917 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17917 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17918 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17918 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17919 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17919 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17920 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17920 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17921 |
// MIs[1] Operand 1 |
17921 |
// MIs[1] Operand 1 |
| 17922 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
17922 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 17923 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17923 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17924 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17924 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17925 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17925 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17926 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17926 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17927 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17927 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17928 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F) |
17928 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F) |
| 17929 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17929 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17930 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
17930 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
| 17931 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17931 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17932 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
17932 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 17933 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17933 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17934 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17934 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17935 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
17935 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
| 17936 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17936 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17937 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17937 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17938 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17938 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17939 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17939 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17940 |
GIR_EraseFromParent, /*InsnID*/0, |
17940 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17941 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17941 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17942 |
// GIR_Coverage, 1607, |
17942 |
// GIR_Coverage, 1607, |
| 17943 |
GIR_Done, |
17943 |
GIR_Done, |
| 17944 |
// Label 1097: @43530 |
17944 |
// Label 1097: @43530 |
| 17945 |
GIM_Try, /*On fail goto*//*Label 1098*/ 43631, // Rule ID 1610 // |
17945 |
GIM_Try, /*On fail goto*//*Label 1098*/ 43631, // Rule ID 1610 // |
| 17946 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
17946 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17947 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17947 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17948 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17948 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17949 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17949 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17950 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17950 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17951 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17951 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17952 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17952 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17953 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17953 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17954 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17954 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17955 |
// MIs[1] Operand 1 |
17955 |
// MIs[1] Operand 1 |
| 17956 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
17956 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 17957 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17957 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17958 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17958 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17959 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17959 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17960 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17960 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17961 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17961 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17962 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
17962 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 17963 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17963 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17964 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
17964 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
| 17965 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17965 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 17966 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
17966 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 17967 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
17967 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 17968 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
17968 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 17969 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
17969 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
| 17970 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
17970 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 17971 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
17971 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 17972 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
17972 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 17973 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
17973 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 17974 |
GIR_EraseFromParent, /*InsnID*/0, |
17974 |
GIR_EraseFromParent, /*InsnID*/0, |
| 17975 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
17975 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 17976 |
// GIR_Coverage, 1610, |
17976 |
// GIR_Coverage, 1610, |
| 17977 |
GIR_Done, |
17977 |
GIR_Done, |
| 17978 |
// Label 1098: @43631 |
17978 |
// Label 1098: @43631 |
| 17979 |
GIM_Try, /*On fail goto*//*Label 1099*/ 43732, // Rule ID 1613 // |
17979 |
GIM_Try, /*On fail goto*//*Label 1099*/ 43732, // Rule ID 1613 // |
| 17980 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
17980 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 17981 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
17981 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 17982 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
17982 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 17983 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
17983 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 17984 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
17984 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 17985 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
17985 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 17986 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
17986 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 17987 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
17987 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 17988 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
17988 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 17989 |
// MIs[1] Operand 1 |
17989 |
// MIs[1] Operand 1 |
| 17990 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
17990 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 17991 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17991 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17992 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17992 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17993 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
17993 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 17994 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
17994 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 17995 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
17995 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 17996 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
17996 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 17997 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
17997 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 17998 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
17998 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
| 17999 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
17999 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18000 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18000 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18001 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18001 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18002 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18002 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18003 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I, |
18003 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I, |
| 18004 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
18004 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 18005 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18005 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18006 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18006 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18007 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18007 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18008 |
GIR_EraseFromParent, /*InsnID*/0, |
18008 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18009 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18009 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18010 |
// GIR_Coverage, 1613, |
18010 |
// GIR_Coverage, 1613, |
| 18011 |
GIR_Done, |
18011 |
GIR_Done, |
| 18012 |
// Label 1099: @43732 |
18012 |
// Label 1099: @43732 |
| 18013 |
GIM_Try, /*On fail goto*//*Label 1100*/ 43833, // Rule ID 1624 // |
18013 |
GIM_Try, /*On fail goto*//*Label 1100*/ 43833, // Rule ID 1624 // |
| 18014 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
18014 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18015 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18015 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18016 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18016 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18017 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18017 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18018 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
18018 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 18019 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18019 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18020 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18020 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18021 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
18021 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18022 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
18022 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 18023 |
// MIs[1] Operand 1 |
18023 |
// MIs[1] Operand 1 |
| 18024 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
18024 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 18025 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
18025 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 18026 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
18026 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 18027 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18027 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18028 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18028 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18029 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18029 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18030 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F) |
18030 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 18031 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18031 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18032 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
18032 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
| 18033 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18033 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18034 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18034 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18035 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18035 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18036 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18036 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18037 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
18037 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
| 18038 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
18038 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 18039 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18039 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18040 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18040 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18041 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18041 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18042 |
GIR_EraseFromParent, /*InsnID*/0, |
18042 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18043 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18043 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18044 |
// GIR_Coverage, 1624, |
18044 |
// GIR_Coverage, 1624, |
| 18045 |
GIR_Done, |
18045 |
GIR_Done, |
| 18046 |
// Label 1100: @43833 |
18046 |
// Label 1100: @43833 |
| 18047 |
GIM_Try, /*On fail goto*//*Label 1101*/ 43934, // Rule ID 1625 // |
18047 |
GIM_Try, /*On fail goto*//*Label 1101*/ 43934, // Rule ID 1625 // |
| 18048 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
18048 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18049 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18049 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18050 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18050 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18051 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18051 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18052 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
18052 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 18053 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18053 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18054 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18054 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18055 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
18055 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18056 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
18056 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 18057 |
// MIs[1] Operand 1 |
18057 |
// MIs[1] Operand 1 |
| 18058 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
18058 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 18059 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
18059 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 18060 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
18060 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 18061 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18061 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18062 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18062 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18063 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18063 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18064 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F) |
18064 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 18065 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18065 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18066 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
18066 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
| 18067 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18067 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18068 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18068 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18069 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18069 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18070 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18070 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18071 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
18071 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
| 18072 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
18072 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 18073 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18073 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18074 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18074 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18075 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18075 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18076 |
GIR_EraseFromParent, /*InsnID*/0, |
18076 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18077 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18077 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18078 |
// GIR_Coverage, 1625, |
18078 |
// GIR_Coverage, 1625, |
| 18079 |
GIR_Done, |
18079 |
GIR_Done, |
| 18080 |
// Label 1101: @43934 |
18080 |
// Label 1101: @43934 |
| 18081 |
GIM_Try, /*On fail goto*//*Label 1102*/ 44035, // Rule ID 1628 // |
18081 |
GIM_Try, /*On fail goto*//*Label 1102*/ 44035, // Rule ID 1628 // |
| 18082 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
18082 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18083 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18083 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18084 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18084 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18085 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18085 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18086 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
18086 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 18087 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18087 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18088 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18088 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18089 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
18089 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18090 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
18090 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 18091 |
// MIs[1] Operand 1 |
18091 |
// MIs[1] Operand 1 |
| 18092 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
18092 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 18093 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
18093 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 18094 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
18094 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 18095 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18095 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18096 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18096 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18097 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18097 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18098 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F) |
18098 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F) |
| 18099 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18099 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18100 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
18100 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
| 18101 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18101 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18102 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18102 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18103 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18103 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18104 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18104 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18105 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
18105 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
| 18106 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
18106 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 18107 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18107 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18108 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18108 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18109 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18109 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18110 |
GIR_EraseFromParent, /*InsnID*/0, |
18110 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18111 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18111 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18112 |
// GIR_Coverage, 1628, |
18112 |
// GIR_Coverage, 1628, |
| 18113 |
GIR_Done, |
18113 |
GIR_Done, |
| 18114 |
// Label 1102: @44035 |
18114 |
// Label 1102: @44035 |
| 18115 |
GIM_Try, /*On fail goto*//*Label 1103*/ 44136, // Rule ID 1629 // |
18115 |
GIM_Try, /*On fail goto*//*Label 1103*/ 44136, // Rule ID 1629 // |
| 18116 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
18116 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18117 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18117 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18118 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18118 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18119 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18119 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18120 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
18120 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 18121 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18121 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18122 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18122 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18123 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
18123 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18124 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
18124 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 18125 |
// MIs[1] Operand 1 |
18125 |
// MIs[1] Operand 1 |
| 18126 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
18126 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 18127 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
18127 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 18128 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
18128 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 18129 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18129 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18130 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18130 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18131 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18131 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18132 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F) |
18132 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F) |
| 18133 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18133 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18134 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
18134 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
| 18135 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18135 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18136 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18136 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18137 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18137 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18138 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18138 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18139 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
18139 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I, |
| 18140 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
18140 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 18141 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18141 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18142 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18142 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18143 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18143 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18144 |
GIR_EraseFromParent, /*InsnID*/0, |
18144 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18145 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18145 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18146 |
// GIR_Coverage, 1629, |
18146 |
// GIR_Coverage, 1629, |
| 18147 |
GIR_Done, |
18147 |
GIR_Done, |
| 18148 |
// Label 1103: @44136 |
18148 |
// Label 1103: @44136 |
| 18149 |
GIM_Try, /*On fail goto*//*Label 1104*/ 44237, // Rule ID 1642 // |
18149 |
GIM_Try, /*On fail goto*//*Label 1104*/ 44237, // Rule ID 1642 // |
| 18150 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
18150 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18151 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18151 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18152 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18152 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18153 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18153 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18154 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
18154 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 18155 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18155 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18156 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18156 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18157 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
18157 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18158 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
18158 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 18159 |
// MIs[1] Operand 1 |
18159 |
// MIs[1] Operand 1 |
| 18160 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
18160 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 18161 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
18161 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 18162 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
18162 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 18163 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18163 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18164 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18164 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18165 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18165 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18166 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F) |
18166 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 18167 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
18167 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 18168 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
18168 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
| 18169 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18169 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18170 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18170 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18171 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18171 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18172 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18172 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18173 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I, |
18173 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I, |
| 18174 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
18174 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 18175 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18175 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18176 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18176 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18177 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18177 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18178 |
GIR_EraseFromParent, /*InsnID*/0, |
18178 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18179 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18179 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18180 |
// GIR_Coverage, 1642, |
18180 |
// GIR_Coverage, 1642, |
| 18181 |
GIR_Done, |
18181 |
GIR_Done, |
| 18182 |
// Label 1104: @44237 |
18182 |
// Label 1104: @44237 |
| 18183 |
GIM_Try, /*On fail goto*//*Label 1105*/ 44338, // Rule ID 1652 // |
18183 |
GIM_Try, /*On fail goto*//*Label 1105*/ 44338, // Rule ID 1652 // |
| 18184 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
18184 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18185 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18185 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18186 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18186 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18187 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18187 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18188 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
18188 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 18189 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18189 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18190 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18190 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18191 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
18191 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18192 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
18192 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 18193 |
// MIs[1] Operand 1 |
18193 |
// MIs[1] Operand 1 |
| 18194 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
18194 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 18195 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
18195 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 18196 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
18196 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 18197 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18197 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18198 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18198 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18199 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18199 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18200 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F) |
18200 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 18201 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
18201 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 18202 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
18202 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
| 18203 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18203 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18204 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18204 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18205 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18205 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18206 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18206 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18207 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I, |
18207 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I, |
| 18208 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
18208 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 18209 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18209 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18210 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18210 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18211 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18211 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18212 |
GIR_EraseFromParent, /*InsnID*/0, |
18212 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18213 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18213 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18214 |
// GIR_Coverage, 1652, |
18214 |
// GIR_Coverage, 1652, |
| 18215 |
GIR_Done, |
18215 |
GIR_Done, |
| 18216 |
// Label 1105: @44338 |
18216 |
// Label 1105: @44338 |
| 18217 |
GIM_Try, /*On fail goto*//*Label 1106*/ 44439, // Rule ID 1658 // |
18217 |
GIM_Try, /*On fail goto*//*Label 1106*/ 44439, // Rule ID 1658 // |
| 18218 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
18218 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18219 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18219 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18220 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18220 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18221 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18221 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18222 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
18222 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 18223 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18223 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18224 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18224 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18225 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18225 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18226 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18226 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18227 |
// MIs[1] Operand 1 |
18227 |
// MIs[1] Operand 1 |
| 18228 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
18228 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 18229 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18229 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18230 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18230 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18231 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
18231 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 18232 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
18232 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 18233 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18233 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18234 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
18234 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
| 18235 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18235 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18236 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
18236 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
| 18237 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18237 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18238 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18238 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18239 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18239 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18240 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18240 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18241 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
18241 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
| 18242 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
18242 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 18243 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18243 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18244 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18244 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18245 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18245 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18246 |
GIR_EraseFromParent, /*InsnID*/0, |
18246 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18247 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18247 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18248 |
// GIR_Coverage, 1658, |
18248 |
// GIR_Coverage, 1658, |
| 18249 |
GIR_Done, |
18249 |
GIR_Done, |
| 18250 |
// Label 1106: @44439 |
18250 |
// Label 1106: @44439 |
| 18251 |
GIM_Try, /*On fail goto*//*Label 1107*/ 44540, // Rule ID 1659 // |
18251 |
GIM_Try, /*On fail goto*//*Label 1107*/ 44540, // Rule ID 1659 // |
| 18252 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
18252 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18253 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18253 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18254 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18254 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18255 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18255 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18256 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
18256 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 18257 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18257 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18258 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18258 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18259 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18259 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18260 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18260 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18261 |
// MIs[1] Operand 1 |
18261 |
// MIs[1] Operand 1 |
| 18262 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
18262 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 18263 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18263 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18264 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18264 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18265 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
18265 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 18266 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
18266 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 18267 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18267 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18268 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
18268 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
| 18269 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18269 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18270 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
18270 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
| 18271 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18271 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18272 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18272 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18273 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18273 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18274 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18274 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18275 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
18275 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
| 18276 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
18276 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 18277 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18277 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18278 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18278 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18279 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18279 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18280 |
GIR_EraseFromParent, /*InsnID*/0, |
18280 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18281 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18281 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18282 |
// GIR_Coverage, 1659, |
18282 |
// GIR_Coverage, 1659, |
| 18283 |
GIR_Done, |
18283 |
GIR_Done, |
| 18284 |
// Label 1107: @44540 |
18284 |
// Label 1107: @44540 |
| 18285 |
GIM_Try, /*On fail goto*//*Label 1108*/ 44641, // Rule ID 1662 // |
18285 |
GIM_Try, /*On fail goto*//*Label 1108*/ 44641, // Rule ID 1662 // |
| 18286 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
18286 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18287 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18287 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18288 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18288 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18289 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18289 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18290 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
18290 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 18291 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18291 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18292 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18292 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18293 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18293 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18294 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18294 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18295 |
// MIs[1] Operand 1 |
18295 |
// MIs[1] Operand 1 |
| 18296 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
18296 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 18297 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18297 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18298 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18298 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18299 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
18299 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 18300 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
18300 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 18301 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18301 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18302 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F) |
18302 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F) |
| 18303 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18303 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18304 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
18304 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
| 18305 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18305 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18306 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18306 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18307 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18307 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18308 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18308 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18309 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
18309 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
| 18310 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
18310 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 18311 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18311 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18312 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18312 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18313 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18313 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18314 |
GIR_EraseFromParent, /*InsnID*/0, |
18314 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18315 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18315 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18316 |
// GIR_Coverage, 1662, |
18316 |
// GIR_Coverage, 1662, |
| 18317 |
GIR_Done, |
18317 |
GIR_Done, |
| 18318 |
// Label 1108: @44641 |
18318 |
// Label 1108: @44641 |
| 18319 |
GIM_Try, /*On fail goto*//*Label 1109*/ 44742, // Rule ID 1663 // |
18319 |
GIM_Try, /*On fail goto*//*Label 1109*/ 44742, // Rule ID 1663 // |
| 18320 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
18320 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18321 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18321 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18322 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18322 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18323 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18323 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
18324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 18325 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18325 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18326 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18326 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18327 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18327 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18328 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18328 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18329 |
// MIs[1] Operand 1 |
18329 |
// MIs[1] Operand 1 |
| 18330 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
18330 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 18331 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18331 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18332 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18332 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18333 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
18333 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 18334 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
18334 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 18335 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18335 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18336 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F) |
18336 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F) |
| 18337 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18337 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18338 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
18338 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
| 18339 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18339 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18340 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18340 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18341 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18341 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18342 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18342 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18343 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
18343 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
| 18344 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
18344 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 18345 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18345 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18346 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18346 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18347 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18347 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18348 |
GIR_EraseFromParent, /*InsnID*/0, |
18348 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18349 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18349 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18350 |
// GIR_Coverage, 1663, |
18350 |
// GIR_Coverage, 1663, |
| 18351 |
GIR_Done, |
18351 |
GIR_Done, |
| 18352 |
// Label 1109: @44742 |
18352 |
// Label 1109: @44742 |
| 18353 |
GIM_Try, /*On fail goto*//*Label 1110*/ 44843, // Rule ID 1666 // |
18353 |
GIM_Try, /*On fail goto*//*Label 1110*/ 44843, // Rule ID 1666 // |
| 18354 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
18354 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18355 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18355 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18356 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18356 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18357 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18357 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18358 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
18358 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 18359 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18359 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18360 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18360 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18361 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18361 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18362 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18362 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18363 |
// MIs[1] Operand 1 |
18363 |
// MIs[1] Operand 1 |
| 18364 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
18364 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 18365 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18365 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18366 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18366 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18367 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
18367 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 18368 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
18368 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 18369 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18369 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18370 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
18370 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
| 18371 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18371 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18372 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
18372 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
| 18373 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18373 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18374 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18374 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18375 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18375 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18376 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18376 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18377 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
18377 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
| 18378 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
18378 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 18379 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18379 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18380 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18380 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18381 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18381 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18382 |
GIR_EraseFromParent, /*InsnID*/0, |
18382 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18383 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18383 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18384 |
// GIR_Coverage, 1666, |
18384 |
// GIR_Coverage, 1666, |
| 18385 |
GIR_Done, |
18385 |
GIR_Done, |
| 18386 |
// Label 1110: @44843 |
18386 |
// Label 1110: @44843 |
| 18387 |
GIM_Try, /*On fail goto*//*Label 1111*/ 44944, // Rule ID 1668 // |
18387 |
GIM_Try, /*On fail goto*//*Label 1111*/ 44944, // Rule ID 1668 // |
| 18388 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
18388 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18389 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18389 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18390 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18390 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18391 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18391 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18392 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
18392 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 18393 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18393 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18394 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18394 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18395 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18395 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18396 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18396 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18397 |
// MIs[1] Operand 1 |
18397 |
// MIs[1] Operand 1 |
| 18398 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
18398 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 18399 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18399 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18400 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18400 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18401 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
18401 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 18402 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
18402 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 18403 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18403 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18404 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
18404 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
| 18405 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18405 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18406 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
18406 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
| 18407 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18407 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18408 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18408 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18409 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18409 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18410 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18410 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18411 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S, |
18411 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S, |
| 18412 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
18412 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 18413 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18413 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18414 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18414 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18415 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18415 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18416 |
GIR_EraseFromParent, /*InsnID*/0, |
18416 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18417 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18417 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18418 |
// GIR_Coverage, 1668, |
18418 |
// GIR_Coverage, 1668, |
| 18419 |
GIR_Done, |
18419 |
GIR_Done, |
| 18420 |
// Label 1111: @44944 |
18420 |
// Label 1111: @44944 |
| 18421 |
GIM_Try, /*On fail goto*//*Label 1112*/ 45045, // Rule ID 1671 // |
18421 |
GIM_Try, /*On fail goto*//*Label 1112*/ 45045, // Rule ID 1671 // |
| 18422 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
18422 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18423 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18423 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18424 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18424 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18425 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18425 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18426 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
18426 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 18427 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18427 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18428 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18428 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18429 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
18429 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18430 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
18430 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 18431 |
// MIs[1] Operand 1 |
18431 |
// MIs[1] Operand 1 |
| 18432 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
18432 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 18433 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
18433 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 18434 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
18434 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 18435 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
18435 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 18436 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
18436 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 18437 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18437 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18438 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F) |
18438 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F) |
| 18439 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18439 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18440 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
18440 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
| 18441 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18441 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18442 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18442 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18443 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18443 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18444 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18444 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18445 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
18445 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
| 18446 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
18446 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 18447 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18447 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18448 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18448 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18449 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18449 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18450 |
GIR_EraseFromParent, /*InsnID*/0, |
18450 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18451 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18451 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18452 |
// GIR_Coverage, 1671, |
18452 |
// GIR_Coverage, 1671, |
| 18453 |
GIR_Done, |
18453 |
GIR_Done, |
| 18454 |
// Label 1112: @45045 |
18454 |
// Label 1112: @45045 |
| 18455 |
GIM_Try, /*On fail goto*//*Label 1113*/ 45146, // Rule ID 1672 // |
18455 |
GIM_Try, /*On fail goto*//*Label 1113*/ 45146, // Rule ID 1672 // |
| 18456 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
18456 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18457 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18457 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18458 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18458 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18459 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18459 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18460 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
18460 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 18461 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18461 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18462 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18462 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18463 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
18463 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18464 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
18464 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 18465 |
// MIs[1] Operand 1 |
18465 |
// MIs[1] Operand 1 |
| 18466 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
18466 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 18467 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
18467 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 18468 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
18468 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 18469 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
18469 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 18470 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
18470 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 18471 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18471 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18472 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F) |
18472 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F) |
| 18473 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18473 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18474 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
18474 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
| 18475 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18475 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18476 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18476 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18477 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18477 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18478 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18478 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18479 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
18479 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
| 18480 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
18480 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 18481 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18481 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18482 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18482 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18483 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18483 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18484 |
GIR_EraseFromParent, /*InsnID*/0, |
18484 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18485 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18485 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18486 |
// GIR_Coverage, 1672, |
18486 |
// GIR_Coverage, 1672, |
| 18487 |
GIR_Done, |
18487 |
GIR_Done, |
| 18488 |
// Label 1113: @45146 |
18488 |
// Label 1113: @45146 |
| 18489 |
GIM_Try, /*On fail goto*//*Label 1114*/ 45247, // Rule ID 1675 // |
18489 |
GIM_Try, /*On fail goto*//*Label 1114*/ 45247, // Rule ID 1675 // |
| 18490 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
18490 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18491 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18491 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18492 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18492 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18493 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18493 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18494 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
18494 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 18495 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18495 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18496 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18496 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18497 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
18497 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18498 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
18498 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 18499 |
// MIs[1] Operand 1 |
18499 |
// MIs[1] Operand 1 |
| 18500 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
18500 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 18501 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
18501 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 18502 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
18502 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 18503 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
18503 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 18504 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
18504 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 18505 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18505 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18506 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F) |
18506 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F) |
| 18507 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18507 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18508 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
18508 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
| 18509 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18509 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18510 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18510 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18511 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18511 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18512 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18512 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18513 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
18513 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
| 18514 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
18514 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 18515 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18515 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18516 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18516 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18517 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18517 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18518 |
GIR_EraseFromParent, /*InsnID*/0, |
18518 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18519 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18519 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18520 |
// GIR_Coverage, 1675, |
18520 |
// GIR_Coverage, 1675, |
| 18521 |
GIR_Done, |
18521 |
GIR_Done, |
| 18522 |
// Label 1114: @45247 |
18522 |
// Label 1114: @45247 |
| 18523 |
GIM_Try, /*On fail goto*//*Label 1115*/ 45348, // Rule ID 1676 // |
18523 |
GIM_Try, /*On fail goto*//*Label 1115*/ 45348, // Rule ID 1676 // |
| 18524 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
18524 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18525 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18525 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18526 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18526 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18527 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18527 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18528 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
18528 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 18529 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18529 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18530 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18530 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18531 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
18531 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18532 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
18532 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 18533 |
// MIs[1] Operand 1 |
18533 |
// MIs[1] Operand 1 |
| 18534 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
18534 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 18535 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
18535 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 18536 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
18536 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 18537 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
18537 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 18538 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
18538 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 18539 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18539 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18540 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F) |
18540 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F) |
| 18541 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18541 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18542 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
18542 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
| 18543 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18543 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18544 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18544 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18545 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18545 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18546 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18546 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18547 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
18547 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S, |
| 18548 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
18548 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 18549 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18549 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18550 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18550 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18551 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18551 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18552 |
GIR_EraseFromParent, /*InsnID*/0, |
18552 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18553 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18553 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18554 |
// GIR_Coverage, 1676, |
18554 |
// GIR_Coverage, 1676, |
| 18555 |
GIR_Done, |
18555 |
GIR_Done, |
| 18556 |
// Label 1115: @45348 |
18556 |
// Label 1115: @45348 |
| 18557 |
GIM_Try, /*On fail goto*//*Label 1116*/ 45449, // Rule ID 1679 // |
18557 |
GIM_Try, /*On fail goto*//*Label 1116*/ 45449, // Rule ID 1679 // |
| 18558 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
18558 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18559 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18559 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18560 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18560 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18561 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18561 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18562 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
18562 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 18563 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18563 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18564 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18564 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18565 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
18565 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18566 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
18566 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 18567 |
// MIs[1] Operand 1 |
18567 |
// MIs[1] Operand 1 |
| 18568 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
18568 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 18569 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
18569 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 18570 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
18570 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 18571 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
18571 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 18572 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
18572 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 18573 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18573 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18574 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F) |
18574 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F) |
| 18575 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
18575 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 18576 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
18576 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
| 18577 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18577 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18578 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18578 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18579 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18579 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18580 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18580 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18581 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_S, |
18581 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_S, |
| 18582 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
18582 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 18583 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18583 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18584 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18584 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18585 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18585 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18586 |
GIR_EraseFromParent, /*InsnID*/0, |
18586 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18587 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18587 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18588 |
// GIR_Coverage, 1679, |
18588 |
// GIR_Coverage, 1679, |
| 18589 |
GIR_Done, |
18589 |
GIR_Done, |
| 18590 |
// Label 1116: @45449 |
18590 |
// Label 1116: @45449 |
| 18591 |
GIM_Try, /*On fail goto*//*Label 1117*/ 45550, // Rule ID 1681 // |
18591 |
GIM_Try, /*On fail goto*//*Label 1117*/ 45550, // Rule ID 1681 // |
| 18592 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
18592 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 18593 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18593 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18594 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18594 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18595 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18595 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18596 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
18596 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 18597 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18597 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18598 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18598 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18599 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
18599 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 18600 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
18600 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 18601 |
// MIs[1] Operand 1 |
18601 |
// MIs[1] Operand 1 |
| 18602 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
18602 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 18603 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
18603 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 18604 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
18604 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 18605 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
18605 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 18606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
18606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 18607 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18607 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18608 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F) |
18608 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F) |
| 18609 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
18609 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 18610 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
18610 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
| 18611 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18611 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18612 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18612 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18613 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18613 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18614 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18614 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18615 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S, |
18615 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S, |
| 18616 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
18616 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 18617 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18617 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18618 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18618 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18619 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18619 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18620 |
GIR_EraseFromParent, /*InsnID*/0, |
18620 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18621 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18621 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18622 |
// GIR_Coverage, 1681, |
18622 |
// GIR_Coverage, 1681, |
| 18623 |
GIR_Done, |
18623 |
GIR_Done, |
| 18624 |
// Label 1117: @45550 |
18624 |
// Label 1117: @45550 |
| 18625 |
GIM_Try, /*On fail goto*//*Label 1118*/ 45635, // Rule ID 1828 // |
18625 |
GIM_Try, /*On fail goto*//*Label 1118*/ 45635, // Rule ID 1828 // |
| 18626 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
18626 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 18627 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18627 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18628 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18628 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18629 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18629 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18630 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
18630 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 18631 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18631 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18632 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18632 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18633 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18633 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18634 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18634 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18635 |
// MIs[1] Operand 1 |
18635 |
// MIs[1] Operand 1 |
| 18636 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
18636 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 18637 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18637 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18638 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18638 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18639 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18639 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18640 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18640 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18641 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18641 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18642 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b) |
18642 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b) |
| 18643 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSlt, |
18643 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSlt, |
| 18644 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
18644 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
| 18645 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
18645 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
| 18646 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
18646 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
| 18647 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
18647 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
| 18648 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
18648 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
| 18649 |
GIR_EraseFromParent, /*InsnID*/0, |
18649 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18650 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18650 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18651 |
// GIR_Coverage, 1828, |
18651 |
// GIR_Coverage, 1828, |
| 18652 |
GIR_Done, |
18652 |
GIR_Done, |
| 18653 |
// Label 1118: @45635 |
18653 |
// Label 1118: @45635 |
| 18654 |
GIM_Try, /*On fail goto*//*Label 1119*/ 45720, // Rule ID 1829 // |
18654 |
GIM_Try, /*On fail goto*//*Label 1119*/ 45720, // Rule ID 1829 // |
| 18655 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
18655 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 18656 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18656 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18657 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18657 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18658 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18658 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18659 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
18659 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 18660 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18660 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18661 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18661 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18662 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18662 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18663 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18663 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18664 |
// MIs[1] Operand 1 |
18664 |
// MIs[1] Operand 1 |
| 18665 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, |
18665 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, |
| 18666 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18666 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18667 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18667 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18668 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18668 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18669 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18669 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18670 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18670 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18671 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a) |
18671 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a) |
| 18672 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZSlt, |
18672 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZSlt, |
| 18673 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
18673 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
| 18674 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
18674 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
| 18675 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
18675 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
| 18676 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
18676 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
| 18677 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
18677 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
| 18678 |
GIR_EraseFromParent, /*InsnID*/0, |
18678 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18679 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18679 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18680 |
// GIR_Coverage, 1829, |
18680 |
// GIR_Coverage, 1829, |
| 18681 |
GIR_Done, |
18681 |
GIR_Done, |
| 18682 |
// Label 1119: @45720 |
18682 |
// Label 1119: @45720 |
| 18683 |
GIM_Try, /*On fail goto*//*Label 1120*/ 45805, // Rule ID 1830 // |
18683 |
GIM_Try, /*On fail goto*//*Label 1120*/ 45805, // Rule ID 1830 // |
| 18684 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
18684 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 18685 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18685 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18686 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18686 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18687 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18687 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18688 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
18688 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 18689 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18689 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18690 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18690 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18691 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18691 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18692 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18692 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18693 |
// MIs[1] Operand 1 |
18693 |
// MIs[1] Operand 1 |
| 18694 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
18694 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 18695 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18695 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18696 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18696 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18697 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18697 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18698 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18698 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18699 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18699 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18700 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b) |
18700 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b) |
| 18701 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSltu, |
18701 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSltu, |
| 18702 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
18702 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
| 18703 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
18703 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
| 18704 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
18704 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
| 18705 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
18705 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
| 18706 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
18706 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
| 18707 |
GIR_EraseFromParent, /*InsnID*/0, |
18707 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18708 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18708 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18709 |
// GIR_Coverage, 1830, |
18709 |
// GIR_Coverage, 1830, |
| 18710 |
GIR_Done, |
18710 |
GIR_Done, |
| 18711 |
// Label 1120: @45805 |
18711 |
// Label 1120: @45805 |
| 18712 |
GIM_Try, /*On fail goto*//*Label 1121*/ 45890, // Rule ID 1831 // |
18712 |
GIM_Try, /*On fail goto*//*Label 1121*/ 45890, // Rule ID 1831 // |
| 18713 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
18713 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 18714 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18714 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18715 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18715 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18716 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18716 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18717 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
18717 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 18718 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18718 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18719 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18719 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18720 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18720 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18721 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18721 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18722 |
// MIs[1] Operand 1 |
18722 |
// MIs[1] Operand 1 |
| 18723 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT, |
18723 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT, |
| 18724 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18724 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18725 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18725 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18726 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18726 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18727 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18727 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18728 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18728 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18729 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a) |
18729 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a) |
| 18730 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZSltu, |
18730 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZSltu, |
| 18731 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
18731 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
| 18732 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
18732 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
| 18733 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
18733 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
| 18734 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
18734 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
| 18735 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
18735 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
| 18736 |
GIR_EraseFromParent, /*InsnID*/0, |
18736 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18737 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18737 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18738 |
// GIR_Coverage, 1831, |
18738 |
// GIR_Coverage, 1831, |
| 18739 |
GIR_Done, |
18739 |
GIR_Done, |
| 18740 |
// Label 1121: @45890 |
18740 |
// Label 1121: @45890 |
| 18741 |
GIM_Try, /*On fail goto*//*Label 1122*/ 45975, // Rule ID 1833 // |
18741 |
GIM_Try, /*On fail goto*//*Label 1122*/ 45975, // Rule ID 1833 // |
| 18742 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
18742 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 18743 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18743 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18744 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18744 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18745 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18745 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18746 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
18746 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 18747 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18747 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18748 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18748 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18749 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18749 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18750 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18750 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18751 |
// MIs[1] Operand 1 |
18751 |
// MIs[1] Operand 1 |
| 18752 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
18752 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 18753 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18753 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18754 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18754 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18755 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18755 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18756 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18756 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18757 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18757 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18758 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETLE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a) |
18758 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETLE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a) |
| 18759 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSlt, |
18759 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSlt, |
| 18760 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
18760 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
| 18761 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
18761 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
| 18762 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
18762 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
| 18763 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
18763 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
| 18764 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
18764 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
| 18765 |
GIR_EraseFromParent, /*InsnID*/0, |
18765 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18766 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18766 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18767 |
// GIR_Coverage, 1833, |
18767 |
// GIR_Coverage, 1833, |
| 18768 |
GIR_Done, |
18768 |
GIR_Done, |
| 18769 |
// Label 1122: @45975 |
18769 |
// Label 1122: @45975 |
| 18770 |
GIM_Try, /*On fail goto*//*Label 1123*/ 46060, // Rule ID 1834 // |
18770 |
GIM_Try, /*On fail goto*//*Label 1123*/ 46060, // Rule ID 1834 // |
| 18771 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
18771 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 18772 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18772 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18773 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18773 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18774 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18774 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18775 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
18775 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 18776 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18776 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18777 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18777 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18778 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18778 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18779 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18779 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18780 |
// MIs[1] Operand 1 |
18780 |
// MIs[1] Operand 1 |
| 18781 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
18781 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 18782 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18782 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18783 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18783 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18784 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18784 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18785 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18785 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18786 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18786 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18787 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETULE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a) |
18787 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETULE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a) |
| 18788 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSltu, |
18788 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZSltu, |
| 18789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
18789 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
| 18790 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
18790 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
| 18791 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
18791 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
| 18792 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
18792 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
| 18793 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
18793 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
| 18794 |
GIR_EraseFromParent, /*InsnID*/0, |
18794 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18795 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18795 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18796 |
// GIR_Coverage, 1834, |
18796 |
// GIR_Coverage, 1834, |
| 18797 |
GIR_Done, |
18797 |
GIR_Done, |
| 18798 |
// Label 1123: @46060 |
18798 |
// Label 1123: @46060 |
| 18799 |
GIM_Try, /*On fail goto*//*Label 1124*/ 46145, // Rule ID 1835 // |
18799 |
GIM_Try, /*On fail goto*//*Label 1124*/ 46145, // Rule ID 1835 // |
| 18800 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
18800 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 18801 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18801 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18802 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18802 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18803 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18803 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18804 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
18804 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 18805 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18805 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18806 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18806 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18807 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18807 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18808 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18808 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18809 |
// MIs[1] Operand 1 |
18809 |
// MIs[1] Operand 1 |
| 18810 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
18810 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 18811 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18811 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18812 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18812 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18813 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18813 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18814 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18814 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18815 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18815 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18816 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a) |
18816 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBteqZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a) |
| 18817 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZCmp, |
18817 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBteqZCmp, |
| 18818 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
18818 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
| 18819 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
18819 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
| 18820 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
18820 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
| 18821 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
18821 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
| 18822 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
18822 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
| 18823 |
GIR_EraseFromParent, /*InsnID*/0, |
18823 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18824 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18824 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18825 |
// GIR_Coverage, 1835, |
18825 |
// GIR_Coverage, 1835, |
| 18826 |
GIR_Done, |
18826 |
GIR_Done, |
| 18827 |
// Label 1124: @46145 |
18827 |
// Label 1124: @46145 |
| 18828 |
GIM_Try, /*On fail goto*//*Label 1125*/ 46230, // Rule ID 1838 // |
18828 |
GIM_Try, /*On fail goto*//*Label 1125*/ 46230, // Rule ID 1838 // |
| 18829 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
18829 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 18830 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18830 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18831 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18831 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18832 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18832 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18833 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
18833 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 18834 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18834 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18835 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18835 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18836 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18836 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18837 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18837 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18838 |
// MIs[1] Operand 1 |
18838 |
// MIs[1] Operand 1 |
| 18839 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
18839 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 18840 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18840 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18841 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18841 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
18842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 18843 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
18843 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 18844 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18844 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18845 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a) |
18845 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelTBtneZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a) |
| 18846 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZCmp, |
18846 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelTBtneZCmp, |
| 18847 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
18847 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
| 18848 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
18848 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
| 18849 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
18849 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
| 18850 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
18850 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b |
| 18851 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
18851 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a |
| 18852 |
GIR_EraseFromParent, /*InsnID*/0, |
18852 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18853 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18853 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18854 |
// GIR_Coverage, 1838, |
18854 |
// GIR_Coverage, 1838, |
| 18855 |
GIR_Done, |
18855 |
GIR_Done, |
| 18856 |
// Label 1125: @46230 |
18856 |
// Label 1125: @46230 |
| 18857 |
GIM_Try, /*On fail goto*//*Label 1126*/ 46331, // Rule ID 2174 // |
18857 |
GIM_Try, /*On fail goto*//*Label 1126*/ 46331, // Rule ID 2174 // |
| 18858 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
18858 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 18859 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18859 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18860 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18860 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18861 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18861 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18862 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
18862 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 18863 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18863 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18864 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18864 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18865 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18865 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18866 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18866 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18867 |
// MIs[1] Operand 1 |
18867 |
// MIs[1] Operand 1 |
| 18868 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
18868 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 18869 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18869 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18870 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18870 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18871 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18871 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18872 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18872 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18873 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18873 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18874 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
18874 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 18875 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18875 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18876 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
18876 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
| 18877 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18877 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18878 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18878 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18879 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18879 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18880 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18880 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18881 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
18881 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
| 18882 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
18882 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 18883 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18883 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18884 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18884 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18885 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18885 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18886 |
GIR_EraseFromParent, /*InsnID*/0, |
18886 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18887 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18887 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18888 |
// GIR_Coverage, 2174, |
18888 |
// GIR_Coverage, 2174, |
| 18889 |
GIR_Done, |
18889 |
GIR_Done, |
| 18890 |
// Label 1126: @46331 |
18890 |
// Label 1126: @46331 |
| 18891 |
GIM_Try, /*On fail goto*//*Label 1127*/ 46432, // Rule ID 2175 // |
18891 |
GIM_Try, /*On fail goto*//*Label 1127*/ 46432, // Rule ID 2175 // |
| 18892 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
18892 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 18893 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18893 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18894 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18894 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18895 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18895 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18896 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
18896 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 18897 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18897 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18898 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18898 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18899 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18899 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18900 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18900 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18901 |
// MIs[1] Operand 1 |
18901 |
// MIs[1] Operand 1 |
| 18902 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
18902 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 18903 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18903 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18904 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18904 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18905 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18905 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18906 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18906 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18907 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18907 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18908 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
18908 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 18909 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18909 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18910 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
18910 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
| 18911 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18911 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18912 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18912 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18913 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18913 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18914 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18914 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18915 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
18915 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
| 18916 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
18916 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 18917 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18917 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18918 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18918 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18919 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18919 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18920 |
GIR_EraseFromParent, /*InsnID*/0, |
18920 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18921 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18921 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18922 |
// GIR_Coverage, 2175, |
18922 |
// GIR_Coverage, 2175, |
| 18923 |
GIR_Done, |
18923 |
GIR_Done, |
| 18924 |
// Label 1127: @46432 |
18924 |
// Label 1127: @46432 |
| 18925 |
GIM_Try, /*On fail goto*//*Label 1128*/ 46533, // Rule ID 2178 // |
18925 |
GIM_Try, /*On fail goto*//*Label 1128*/ 46533, // Rule ID 2178 // |
| 18926 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
18926 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 18927 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18927 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18928 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18928 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18929 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18929 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18930 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
18930 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 18931 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18931 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18932 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18932 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18933 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18933 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18934 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18934 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18935 |
// MIs[1] Operand 1 |
18935 |
// MIs[1] Operand 1 |
| 18936 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
18936 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 18937 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18937 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18938 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18938 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18939 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18939 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18940 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18940 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18941 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18941 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18942 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F) |
18942 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F) |
| 18943 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18943 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18944 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
18944 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
| 18945 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18945 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18946 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18946 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18947 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18947 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18948 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18948 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18949 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
18949 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
| 18950 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
18950 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 18951 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18951 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18952 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18952 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18954 |
GIR_EraseFromParent, /*InsnID*/0, |
18954 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18955 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18955 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18956 |
// GIR_Coverage, 2178, |
18956 |
// GIR_Coverage, 2178, |
| 18957 |
GIR_Done, |
18957 |
GIR_Done, |
| 18958 |
// Label 1128: @46533 |
18958 |
// Label 1128: @46533 |
| 18959 |
GIM_Try, /*On fail goto*//*Label 1129*/ 46634, // Rule ID 2179 // |
18959 |
GIM_Try, /*On fail goto*//*Label 1129*/ 46634, // Rule ID 2179 // |
| 18960 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
18960 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 18961 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18961 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18962 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18962 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18963 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18963 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18964 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
18964 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 18965 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18965 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 18966 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
18966 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 18967 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
18967 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 18968 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
18968 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 18969 |
// MIs[1] Operand 1 |
18969 |
// MIs[1] Operand 1 |
| 18970 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
18970 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 18971 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18971 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18972 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18972 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18973 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
18973 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 18974 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
18974 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 18975 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
18975 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 18976 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F) |
18976 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F) |
| 18977 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
18977 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 18978 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
18978 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
| 18979 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
18979 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 18980 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
18980 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 18981 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
18981 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 18982 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
18982 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 18983 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
18983 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
| 18984 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
18984 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 18985 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
18985 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 18986 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
18986 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 18987 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
18987 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 18988 |
GIR_EraseFromParent, /*InsnID*/0, |
18988 |
GIR_EraseFromParent, /*InsnID*/0, |
| 18989 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
18989 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 18990 |
// GIR_Coverage, 2179, |
18990 |
// GIR_Coverage, 2179, |
| 18991 |
GIR_Done, |
18991 |
GIR_Done, |
| 18992 |
// Label 1129: @46634 |
18992 |
// Label 1129: @46634 |
| 18993 |
GIM_Try, /*On fail goto*//*Label 1130*/ 46735, // Rule ID 2182 // |
18993 |
GIM_Try, /*On fail goto*//*Label 1130*/ 46735, // Rule ID 2182 // |
| 18994 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
18994 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 18995 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
18995 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 18996 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
18996 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 18997 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
18997 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 18998 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
18998 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 18999 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
18999 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19000 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19000 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19001 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19001 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19002 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19002 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19003 |
// MIs[1] Operand 1 |
19003 |
// MIs[1] Operand 1 |
| 19004 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
19004 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 19005 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19005 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19006 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19006 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19007 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19007 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19008 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19008 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19009 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19009 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19010 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
19010 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 19011 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19011 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19012 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
19012 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
| 19013 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19013 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19014 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19014 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19015 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19015 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19016 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19016 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19017 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
19017 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
| 19018 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19018 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19019 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19019 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19020 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19020 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19021 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19021 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19022 |
GIR_EraseFromParent, /*InsnID*/0, |
19022 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19023 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19023 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19024 |
// GIR_Coverage, 2182, |
19024 |
// GIR_Coverage, 2182, |
| 19025 |
GIR_Done, |
19025 |
GIR_Done, |
| 19026 |
// Label 1130: @46735 |
19026 |
// Label 1130: @46735 |
| 19027 |
GIM_Try, /*On fail goto*//*Label 1131*/ 46836, // Rule ID 2185 // |
19027 |
GIM_Try, /*On fail goto*//*Label 1131*/ 46836, // Rule ID 2185 // |
| 19028 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6, |
19028 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6, |
| 19029 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19029 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19030 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19030 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19031 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19031 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19032 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19032 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19033 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19033 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19034 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19034 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19035 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19035 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19036 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19036 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19037 |
// MIs[1] Operand 1 |
19037 |
// MIs[1] Operand 1 |
| 19038 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
19038 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 19039 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19039 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19040 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19040 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19041 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19041 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19042 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19042 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19043 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19043 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19044 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
19044 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 19045 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19045 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19046 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
19046 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
| 19047 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19047 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19048 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19048 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19049 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19049 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19050 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19050 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19051 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, |
19051 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, |
| 19052 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19052 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19053 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19053 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19054 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19054 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19055 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19055 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19056 |
GIR_EraseFromParent, /*InsnID*/0, |
19056 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19057 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19057 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19058 |
// GIR_Coverage, 2185, |
19058 |
// GIR_Coverage, 2185, |
| 19059 |
GIR_Done, |
19059 |
GIR_Done, |
| 19060 |
// Label 1131: @46836 |
19060 |
// Label 1131: @46836 |
| 19061 |
GIM_Try, /*On fail goto*//*Label 1132*/ 46937, // Rule ID 2188 // |
19061 |
GIM_Try, /*On fail goto*//*Label 1132*/ 46937, // Rule ID 2188 // |
| 19062 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19062 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19063 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19063 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19064 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19064 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19065 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19065 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19066 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19066 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19067 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19067 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19068 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19068 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19069 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19069 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19070 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19070 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19071 |
// MIs[1] Operand 1 |
19071 |
// MIs[1] Operand 1 |
| 19072 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
19072 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 19073 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19073 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19074 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19074 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19075 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19075 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19076 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19076 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19077 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19077 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19078 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
19078 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 19079 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19079 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19080 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
19080 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
| 19081 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19081 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19082 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19082 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19083 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19083 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19084 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19084 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19085 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
19085 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
| 19086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19087 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19087 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19088 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19088 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19089 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19089 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19090 |
GIR_EraseFromParent, /*InsnID*/0, |
19090 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19091 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19091 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19092 |
// GIR_Coverage, 2188, |
19092 |
// GIR_Coverage, 2188, |
| 19093 |
GIR_Done, |
19093 |
GIR_Done, |
| 19094 |
// Label 1132: @46937 |
19094 |
// Label 1132: @46937 |
| 19095 |
GIM_Try, /*On fail goto*//*Label 1133*/ 47038, // Rule ID 2189 // |
19095 |
GIM_Try, /*On fail goto*//*Label 1133*/ 47038, // Rule ID 2189 // |
| 19096 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19096 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19097 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19097 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19098 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19098 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19099 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19099 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19100 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19100 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19101 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19101 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19102 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19102 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19103 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19103 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19104 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19104 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19105 |
// MIs[1] Operand 1 |
19105 |
// MIs[1] Operand 1 |
| 19106 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
19106 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 19107 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19107 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19108 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19108 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19109 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19109 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19110 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19110 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19111 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19111 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19112 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
19112 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 19113 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19113 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19114 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
19114 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
| 19115 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19115 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19116 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19116 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19117 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19117 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19118 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19118 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19119 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
19119 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
| 19120 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19120 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19121 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19121 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19122 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19122 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19123 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19123 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19124 |
GIR_EraseFromParent, /*InsnID*/0, |
19124 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19125 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19125 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19126 |
// GIR_Coverage, 2189, |
19126 |
// GIR_Coverage, 2189, |
| 19127 |
GIR_Done, |
19127 |
GIR_Done, |
| 19128 |
// Label 1133: @47038 |
19128 |
// Label 1133: @47038 |
| 19129 |
GIM_Try, /*On fail goto*//*Label 1134*/ 47139, // Rule ID 2192 // |
19129 |
GIM_Try, /*On fail goto*//*Label 1134*/ 47139, // Rule ID 2192 // |
| 19130 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19130 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19131 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19131 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19132 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19132 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19133 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19133 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19134 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19134 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19135 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19135 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19136 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19136 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19137 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19137 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19138 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19138 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19139 |
// MIs[1] Operand 1 |
19139 |
// MIs[1] Operand 1 |
| 19140 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
19140 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 19141 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19141 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19142 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19142 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19143 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19143 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19144 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19144 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19145 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19145 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19146 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F) |
19146 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F) |
| 19147 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19147 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19148 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
19148 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
| 19149 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19149 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19150 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19150 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19151 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19151 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19152 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19152 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19153 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
19153 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
| 19154 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19154 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19155 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19155 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19156 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19156 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19157 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19157 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19158 |
GIR_EraseFromParent, /*InsnID*/0, |
19158 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19159 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19159 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19160 |
// GIR_Coverage, 2192, |
19160 |
// GIR_Coverage, 2192, |
| 19161 |
GIR_Done, |
19161 |
GIR_Done, |
| 19162 |
// Label 1134: @47139 |
19162 |
// Label 1134: @47139 |
| 19163 |
GIM_Try, /*On fail goto*//*Label 1135*/ 47240, // Rule ID 2193 // |
19163 |
GIM_Try, /*On fail goto*//*Label 1135*/ 47240, // Rule ID 2193 // |
| 19164 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19164 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19165 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19165 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19166 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19166 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19167 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19167 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19168 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19168 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19169 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19169 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19170 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19170 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19171 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19171 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19172 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19172 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19173 |
// MIs[1] Operand 1 |
19173 |
// MIs[1] Operand 1 |
| 19174 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
19174 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 19175 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19175 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19176 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19176 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19177 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19177 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19178 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19178 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19179 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19179 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19180 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F) |
19180 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F) |
| 19181 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19181 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19182 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
19182 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
| 19183 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19183 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19184 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19184 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19185 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19185 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19186 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19186 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19187 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
19187 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
| 19188 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19188 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19189 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19189 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19190 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19190 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19191 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19191 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19192 |
GIR_EraseFromParent, /*InsnID*/0, |
19192 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19193 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19193 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19194 |
// GIR_Coverage, 2193, |
19194 |
// GIR_Coverage, 2193, |
| 19195 |
GIR_Done, |
19195 |
GIR_Done, |
| 19196 |
// Label 1135: @47240 |
19196 |
// Label 1135: @47240 |
| 19197 |
GIM_Try, /*On fail goto*//*Label 1136*/ 47341, // Rule ID 2196 // |
19197 |
GIM_Try, /*On fail goto*//*Label 1136*/ 47341, // Rule ID 2196 // |
| 19198 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19198 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19199 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19199 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19200 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19200 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19201 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19201 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19202 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19202 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19203 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19203 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19204 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19204 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19205 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19205 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19206 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19206 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19207 |
// MIs[1] Operand 1 |
19207 |
// MIs[1] Operand 1 |
| 19208 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
19208 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 19209 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19209 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19210 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19210 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19212 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19212 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19213 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19213 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19214 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
19214 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 19215 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19215 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19216 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
19216 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
| 19217 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19217 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19218 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19218 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19219 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19219 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19220 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19220 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19221 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
19221 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_MM, |
| 19222 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19222 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19223 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19223 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19224 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19224 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19225 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19225 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19226 |
GIR_EraseFromParent, /*InsnID*/0, |
19226 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19227 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19227 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19228 |
// GIR_Coverage, 2196, |
19228 |
// GIR_Coverage, 2196, |
| 19229 |
GIR_Done, |
19229 |
GIR_Done, |
| 19230 |
// Label 1136: @47341 |
19230 |
// Label 1136: @47341 |
| 19231 |
GIM_Try, /*On fail goto*//*Label 1137*/ 47442, // Rule ID 2199 // |
19231 |
GIM_Try, /*On fail goto*//*Label 1137*/ 47442, // Rule ID 2199 // |
| 19232 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19232 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19233 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19233 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19234 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19234 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19235 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19235 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19236 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19236 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19237 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19237 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19238 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19238 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19239 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19239 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19240 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19240 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19241 |
// MIs[1] Operand 1 |
19241 |
// MIs[1] Operand 1 |
| 19242 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
19242 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 19243 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19243 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19244 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19244 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19245 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19245 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19246 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19246 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19247 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19247 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19248 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
19248 |
// (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F) |
| 19249 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19249 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19250 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
19250 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
| 19251 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19251 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19252 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19252 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19253 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19253 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19254 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19254 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19255 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, |
19255 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, |
| 19256 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19256 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19257 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19257 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19258 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19258 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19259 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19259 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19260 |
GIR_EraseFromParent, /*InsnID*/0, |
19260 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19261 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19261 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19262 |
// GIR_Coverage, 2199, |
19262 |
// GIR_Coverage, 2199, |
| 19263 |
GIR_Done, |
19263 |
GIR_Done, |
| 19264 |
// Label 1137: @47442 |
19264 |
// Label 1137: @47442 |
| 19265 |
GIM_Try, /*On fail goto*//*Label 1138*/ 47543, // Rule ID 2222 // |
19265 |
GIM_Try, /*On fail goto*//*Label 1138*/ 47543, // Rule ID 2222 // |
| 19266 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19266 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19267 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19267 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19268 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19268 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19269 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19269 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19270 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
19270 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 19271 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19271 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19272 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19272 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19273 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19273 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19274 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19274 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19275 |
// MIs[1] Operand 1 |
19275 |
// MIs[1] Operand 1 |
| 19276 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
19276 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 19277 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19277 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19278 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19278 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
19279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 19280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
19280 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 19281 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19281 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19282 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
19282 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
| 19283 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19283 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19284 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
19284 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
| 19285 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19285 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19286 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19286 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19287 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19287 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19288 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19288 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19289 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM, |
19289 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM, |
| 19290 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19290 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19291 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19291 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19292 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19292 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19293 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19293 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19294 |
GIR_EraseFromParent, /*InsnID*/0, |
19294 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19295 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19295 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19296 |
// GIR_Coverage, 2222, |
19296 |
// GIR_Coverage, 2222, |
| 19297 |
GIR_Done, |
19297 |
GIR_Done, |
| 19298 |
// Label 1138: @47543 |
19298 |
// Label 1138: @47543 |
| 19299 |
GIM_Try, /*On fail goto*//*Label 1139*/ 47644, // Rule ID 2223 // |
19299 |
GIM_Try, /*On fail goto*//*Label 1139*/ 47644, // Rule ID 2223 // |
| 19300 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19300 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19301 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19301 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19302 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19302 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19303 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19303 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19304 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
19304 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 19305 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19305 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19306 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19306 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19307 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19307 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19308 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19308 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19309 |
// MIs[1] Operand 1 |
19309 |
// MIs[1] Operand 1 |
| 19310 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
19310 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 19311 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19311 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19312 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19312 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19313 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
19313 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 19314 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
19314 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 19315 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19315 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19316 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
19316 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
| 19317 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19317 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19318 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
19318 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
| 19319 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19319 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19320 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19320 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19321 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19321 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19322 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19322 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19323 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM, |
19323 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM, |
| 19324 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19324 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19325 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19325 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19326 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19326 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19327 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19327 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19328 |
GIR_EraseFromParent, /*InsnID*/0, |
19328 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19329 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19329 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19330 |
// GIR_Coverage, 2223, |
19330 |
// GIR_Coverage, 2223, |
| 19331 |
GIR_Done, |
19331 |
GIR_Done, |
| 19332 |
// Label 1139: @47644 |
19332 |
// Label 1139: @47644 |
| 19333 |
GIM_Try, /*On fail goto*//*Label 1140*/ 47745, // Rule ID 2226 // |
19333 |
GIM_Try, /*On fail goto*//*Label 1140*/ 47745, // Rule ID 2226 // |
| 19334 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19334 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19335 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19335 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19336 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19336 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19337 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19337 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19338 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
19338 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 19339 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19339 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19340 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19340 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19341 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19341 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19342 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19342 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19343 |
// MIs[1] Operand 1 |
19343 |
// MIs[1] Operand 1 |
| 19344 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
19344 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 19345 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19345 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19346 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19346 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19347 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
19347 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 19348 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
19348 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 19349 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19349 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19350 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F) |
19350 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F) |
| 19351 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19351 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19352 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
19352 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
| 19353 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19353 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19354 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19354 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19355 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19355 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19356 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19356 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19357 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM, |
19357 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM, |
| 19358 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19358 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19359 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19359 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19360 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19360 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19361 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19361 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19362 |
GIR_EraseFromParent, /*InsnID*/0, |
19362 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19363 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19363 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19364 |
// GIR_Coverage, 2226, |
19364 |
// GIR_Coverage, 2226, |
| 19365 |
GIR_Done, |
19365 |
GIR_Done, |
| 19366 |
// Label 1140: @47745 |
19366 |
// Label 1140: @47745 |
| 19367 |
GIM_Try, /*On fail goto*//*Label 1141*/ 47846, // Rule ID 2227 // |
19367 |
GIM_Try, /*On fail goto*//*Label 1141*/ 47846, // Rule ID 2227 // |
| 19368 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19368 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19369 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19369 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19370 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19370 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19371 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19371 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19372 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
19372 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 19373 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19373 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19374 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19374 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19375 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19375 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19376 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19376 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19377 |
// MIs[1] Operand 1 |
19377 |
// MIs[1] Operand 1 |
| 19378 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
19378 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 19379 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19379 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19380 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19380 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19381 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
19381 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 19382 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
19382 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 19383 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19383 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19384 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F) |
19384 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F) |
| 19385 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19385 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19386 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
19386 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
| 19387 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19387 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19388 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19388 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19389 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19389 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19390 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19390 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19391 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM, |
19391 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM, |
| 19392 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19392 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19393 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19393 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19394 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19394 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19395 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19395 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19396 |
GIR_EraseFromParent, /*InsnID*/0, |
19396 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19397 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19397 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19398 |
// GIR_Coverage, 2227, |
19398 |
// GIR_Coverage, 2227, |
| 19399 |
GIR_Done, |
19399 |
GIR_Done, |
| 19400 |
// Label 1141: @47846 |
19400 |
// Label 1141: @47846 |
| 19401 |
GIM_Try, /*On fail goto*//*Label 1142*/ 47947, // Rule ID 2230 // |
19401 |
GIM_Try, /*On fail goto*//*Label 1142*/ 47947, // Rule ID 2230 // |
| 19402 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19402 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19403 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19403 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19404 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19404 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19405 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19405 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19406 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
19406 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 19407 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19407 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19408 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19408 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19409 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19409 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19410 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19410 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19411 |
// MIs[1] Operand 1 |
19411 |
// MIs[1] Operand 1 |
| 19412 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
19412 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 19413 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19413 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19414 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19414 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19415 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
19415 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 19416 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
19416 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 19417 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19417 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19418 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
19418 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
| 19419 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19419 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19420 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
19420 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
| 19421 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19421 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19422 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19422 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19423 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19423 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19424 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19424 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19425 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM, |
19425 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_S_MM, |
| 19426 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19426 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19427 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19427 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19428 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19428 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19429 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19429 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19430 |
GIR_EraseFromParent, /*InsnID*/0, |
19430 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19431 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19431 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19432 |
// GIR_Coverage, 2230, |
19432 |
// GIR_Coverage, 2230, |
| 19433 |
GIR_Done, |
19433 |
GIR_Done, |
| 19434 |
// Label 1142: @47947 |
19434 |
// Label 1142: @47947 |
| 19435 |
GIM_Try, /*On fail goto*//*Label 1143*/ 48048, // Rule ID 2232 // |
19435 |
GIM_Try, /*On fail goto*//*Label 1143*/ 48048, // Rule ID 2232 // |
| 19436 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19436 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19437 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19437 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19438 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19438 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19439 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19439 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19440 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
19440 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 19441 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19441 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19442 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19442 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19443 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19443 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19444 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19444 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19445 |
// MIs[1] Operand 1 |
19445 |
// MIs[1] Operand 1 |
| 19446 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
19446 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 19447 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19447 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19448 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19448 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19449 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
19449 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 19450 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
19450 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 19451 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19451 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19452 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
19452 |
// (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F) |
| 19453 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19453 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19454 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
19454 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
| 19455 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19455 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19456 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19456 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19457 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
19457 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 19458 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19458 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19459 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM, |
19459 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM, |
| 19460 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19460 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19461 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19461 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19462 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19462 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19463 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19463 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19464 |
GIR_EraseFromParent, /*InsnID*/0, |
19464 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19465 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19465 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19466 |
// GIR_Coverage, 2232, |
19466 |
// GIR_Coverage, 2232, |
| 19467 |
GIR_Done, |
19467 |
GIR_Done, |
| 19468 |
// Label 1143: @48048 |
19468 |
// Label 1143: @48048 |
| 19469 |
GIM_Try, /*On fail goto*//*Label 1144*/ 48087, // Rule ID 283 // |
19469 |
GIM_Try, /*On fail goto*//*Label 1144*/ 48087, // Rule ID 283 // |
| 19470 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32, |
19470 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32, |
| 19471 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19471 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19472 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19472 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19473 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19473 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19474 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19474 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19475 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
19475 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 19476 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19476 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19477 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19477 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19478 |
// (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) => (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) |
19478 |
// (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) => (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) |
| 19479 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I, |
19479 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I, |
| 19480 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19480 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19481 |
// GIR_Coverage, 283, |
19481 |
// GIR_Coverage, 283, |
| 19482 |
GIR_Done, |
19482 |
GIR_Done, |
| 19483 |
// Label 1144: @48087 |
19483 |
// Label 1144: @48087 |
| 19484 |
GIM_Try, /*On fail goto*//*Label 1145*/ 48126, // Rule ID 285 // |
19484 |
GIM_Try, /*On fail goto*//*Label 1145*/ 48126, // Rule ID 285 // |
| 19485 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32, |
19485 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32, |
| 19486 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19486 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19487 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19487 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19488 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19488 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19489 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
19489 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 19490 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
19490 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 19491 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
19491 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 19492 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
19492 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 19493 |
// (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) => (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) |
19493 |
// (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) => (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) |
| 19494 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_S, |
19494 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_S, |
| 19495 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19495 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19496 |
// GIR_Coverage, 285, |
19496 |
// GIR_Coverage, 285, |
| 19497 |
GIR_Done, |
19497 |
GIR_Done, |
| 19498 |
// Label 1145: @48126 |
19498 |
// Label 1145: @48126 |
| 19499 |
GIM_Try, /*On fail goto*//*Label 1146*/ 48182, // Rule ID 322 // |
19499 |
GIM_Try, /*On fail goto*//*Label 1146*/ 48182, // Rule ID 322 // |
| 19500 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
19500 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 19501 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19501 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19502 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19502 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19503 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19503 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19504 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
19504 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 19505 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID, |
19505 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID, |
| 19506 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
19506 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 19507 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
19507 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 19508 |
// (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
19508 |
// (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 19509 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S, |
19509 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S, |
| 19510 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19510 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19511 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in |
19511 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in |
| 19512 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs |
19512 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs |
| 19513 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft |
19513 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft |
| 19514 |
GIR_EraseFromParent, /*InsnID*/0, |
19514 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19515 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19515 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19516 |
// GIR_Coverage, 322, |
19516 |
// GIR_Coverage, 322, |
| 19517 |
GIR_Done, |
19517 |
GIR_Done, |
| 19518 |
// Label 1146: @48182 |
19518 |
// Label 1146: @48182 |
| 19519 |
GIM_Try, /*On fail goto*//*Label 1147*/ 48238, // Rule ID 1201 // |
19519 |
GIM_Try, /*On fail goto*//*Label 1147*/ 48238, // Rule ID 1201 // |
| 19520 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
19520 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 19521 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19521 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19522 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19522 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19523 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19523 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19524 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
19524 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 19525 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID, |
19525 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID, |
| 19526 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
19526 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 19527 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
19527 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 19528 |
// (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S_MMR6:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
19528 |
// (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S_MMR6:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 19529 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S_MMR6, |
19529 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S_MMR6, |
| 19530 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19530 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19531 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in |
19531 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in |
| 19532 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs |
19532 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs |
| 19533 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft |
19533 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft |
| 19534 |
GIR_EraseFromParent, /*InsnID*/0, |
19534 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19535 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19535 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19536 |
// GIR_Coverage, 1201, |
19536 |
// GIR_Coverage, 1201, |
| 19537 |
GIR_Done, |
19537 |
GIR_Done, |
| 19538 |
// Label 1147: @48238 |
19538 |
// Label 1147: @48238 |
| 19539 |
GIM_Try, /*On fail goto*//*Label 1148*/ 48294, // Rule ID 1614 // |
19539 |
GIM_Try, /*On fail goto*//*Label 1148*/ 48294, // Rule ID 1614 // |
| 19540 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
19540 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 19541 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19541 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19542 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19542 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19543 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19543 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19544 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19544 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19545 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
19545 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 19546 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19546 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19547 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19547 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19548 |
// (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F) |
19548 |
// (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F) |
| 19549 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I, |
19549 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I, |
| 19550 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19550 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19551 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19551 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19552 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
19552 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 19553 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19553 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19554 |
GIR_EraseFromParent, /*InsnID*/0, |
19554 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19555 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19555 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19556 |
// GIR_Coverage, 1614, |
19556 |
// GIR_Coverage, 1614, |
| 19557 |
GIR_Done, |
19557 |
GIR_Done, |
| 19558 |
// Label 1148: @48294 |
19558 |
// Label 1148: @48294 |
| 19559 |
GIM_Try, /*On fail goto*//*Label 1149*/ 48350, // Rule ID 1653 // |
19559 |
GIM_Try, /*On fail goto*//*Label 1149*/ 48350, // Rule ID 1653 // |
| 19560 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
19560 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 19561 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
19561 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19562 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19562 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19563 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19563 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19564 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19564 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19565 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
19565 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 19566 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19566 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19567 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19567 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19568 |
// (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F) |
19568 |
// (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F) |
| 19569 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I, |
19569 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I, |
| 19570 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19570 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19571 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19571 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19572 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
19572 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 19573 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19573 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19574 |
GIR_EraseFromParent, /*InsnID*/0, |
19574 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19575 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19575 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19576 |
// GIR_Coverage, 1653, |
19576 |
// GIR_Coverage, 1653, |
| 19577 |
GIR_Done, |
19577 |
GIR_Done, |
| 19578 |
// Label 1149: @48350 |
19578 |
// Label 1149: @48350 |
| 19579 |
GIM_Try, /*On fail goto*//*Label 1150*/ 48406, // Rule ID 1669 // |
19579 |
GIM_Try, /*On fail goto*//*Label 1150*/ 48406, // Rule ID 1669 // |
| 19580 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
19580 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 19581 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19581 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19582 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19582 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19583 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19583 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19584 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
19584 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 19585 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
19585 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 19586 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
19586 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 19587 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
19587 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 19588 |
// (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F) |
19588 |
// (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F) |
| 19589 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S, |
19589 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S, |
| 19590 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19590 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19591 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19591 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19592 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
19592 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 19593 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19593 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19594 |
GIR_EraseFromParent, /*InsnID*/0, |
19594 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19595 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19595 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19596 |
// GIR_Coverage, 1669, |
19596 |
// GIR_Coverage, 1669, |
| 19597 |
GIR_Done, |
19597 |
GIR_Done, |
| 19598 |
// Label 1150: @48406 |
19598 |
// Label 1150: @48406 |
| 19599 |
GIM_Try, /*On fail goto*//*Label 1151*/ 48462, // Rule ID 1682 // |
19599 |
GIM_Try, /*On fail goto*//*Label 1151*/ 48462, // Rule ID 1682 // |
| 19600 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
19600 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 19601 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
19601 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 19602 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19602 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19603 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19603 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19604 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
19604 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 19605 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
19605 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 19606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
19606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 19607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
19607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 19608 |
// (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F) |
19608 |
// (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F) |
| 19609 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S, |
19609 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S, |
| 19610 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19610 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19611 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19611 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19612 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
19612 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 19613 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19613 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19614 |
GIR_EraseFromParent, /*InsnID*/0, |
19614 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19615 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19615 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19616 |
// GIR_Coverage, 1682, |
19616 |
// GIR_Coverage, 1682, |
| 19617 |
GIR_Done, |
19617 |
GIR_Done, |
| 19618 |
// Label 1151: @48462 |
19618 |
// Label 1151: @48462 |
| 19619 |
GIM_Try, /*On fail goto*//*Label 1152*/ 48518, // Rule ID 1840 // |
19619 |
GIM_Try, /*On fail goto*//*Label 1152*/ 48518, // Rule ID 1840 // |
| 19620 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
19620 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 19621 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19621 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19622 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19622 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19623 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19623 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19624 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
19624 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID, |
| 19625 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
19625 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID, |
| 19626 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
19626 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID, |
| 19627 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
19627 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID, |
| 19628 |
// (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a) |
19628 |
// (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a) |
| 19629 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBneZ, |
19629 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBneZ, |
| 19630 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
19630 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_ |
| 19631 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
19631 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x |
| 19632 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
19632 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y |
| 19633 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a |
19633 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 19634 |
GIR_EraseFromParent, /*InsnID*/0, |
19634 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19635 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19635 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19636 |
// GIR_Coverage, 1840, |
19636 |
// GIR_Coverage, 1840, |
| 19637 |
GIR_Done, |
19637 |
GIR_Done, |
| 19638 |
// Label 1152: @48518 |
19638 |
// Label 1152: @48518 |
| 19639 |
GIM_Try, /*On fail goto*//*Label 1153*/ 48574, // Rule ID 2186 // |
19639 |
GIM_Try, /*On fail goto*//*Label 1153*/ 48574, // Rule ID 2186 // |
| 19640 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6, |
19640 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6, |
| 19641 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19641 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19642 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19642 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19643 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19643 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19644 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19644 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19645 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
19645 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 19646 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19646 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19647 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19647 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19648 |
// (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F) |
19648 |
// (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F) |
| 19649 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, |
19649 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, |
| 19650 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19650 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19651 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19651 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19652 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
19652 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 19653 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19653 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19654 |
GIR_EraseFromParent, /*InsnID*/0, |
19654 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19655 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19655 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19656 |
// GIR_Coverage, 2186, |
19656 |
// GIR_Coverage, 2186, |
| 19657 |
GIR_Done, |
19657 |
GIR_Done, |
| 19658 |
// Label 1153: @48574 |
19658 |
// Label 1153: @48574 |
| 19659 |
GIM_Try, /*On fail goto*//*Label 1154*/ 48630, // Rule ID 2200 // |
19659 |
GIM_Try, /*On fail goto*//*Label 1154*/ 48630, // Rule ID 2200 // |
| 19660 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19660 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19661 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19661 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19662 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19662 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19663 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19663 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19664 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19664 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19665 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
19665 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 19666 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19666 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19667 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
19667 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 19668 |
// (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F) |
19668 |
// (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F) |
| 19669 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, |
19669 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM, |
| 19670 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19670 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19671 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19671 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19672 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
19672 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 19673 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19673 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19674 |
GIR_EraseFromParent, /*InsnID*/0, |
19674 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19675 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19675 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19676 |
// GIR_Coverage, 2200, |
19676 |
// GIR_Coverage, 2200, |
| 19677 |
GIR_Done, |
19677 |
GIR_Done, |
| 19678 |
// Label 1154: @48630 |
19678 |
// Label 1154: @48630 |
| 19679 |
GIM_Try, /*On fail goto*//*Label 1155*/ 48686, // Rule ID 2233 // |
19679 |
GIM_Try, /*On fail goto*//*Label 1155*/ 48686, // Rule ID 2233 // |
| 19680 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
19680 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6, |
| 19681 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19681 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19682 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19682 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19683 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19683 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19684 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
19684 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 19685 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
19685 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 19686 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
19686 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 19687 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
19687 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID, |
| 19688 |
// (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F) |
19688 |
// (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F) |
| 19689 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM, |
19689 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM, |
| 19690 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19690 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19691 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19691 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19692 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
19692 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 19693 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19693 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19694 |
GIR_EraseFromParent, /*InsnID*/0, |
19694 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19695 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19695 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19696 |
// GIR_Coverage, 2233, |
19696 |
// GIR_Coverage, 2233, |
| 19697 |
GIR_Done, |
19697 |
GIR_Done, |
| 19698 |
// Label 1155: @48686 |
19698 |
// Label 1155: @48686 |
| 19699 |
GIM_Try, /*On fail goto*//*Label 1156*/ 48766, // Rule ID 1751 // |
19699 |
GIM_Try, /*On fail goto*//*Label 1156*/ 48766, // Rule ID 1751 // |
| 19700 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
19700 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 19701 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19701 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19702 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19702 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19703 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19703 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19704 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19704 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19705 |
// (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond)) |
19705 |
// (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond)) |
| 19706 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19706 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19707 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
19707 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 19708 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ, |
19708 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ, |
| 19709 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
19709 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 19710 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f |
19710 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f |
| 19711 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond |
19711 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 19712 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
19712 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 19713 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ, |
19713 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ, |
| 19714 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19714 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19715 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t |
19715 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t |
| 19716 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond |
19716 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 19717 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19717 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19718 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR, |
19718 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR, |
| 19719 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19719 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19720 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19720 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19721 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
19721 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 19722 |
GIR_EraseFromParent, /*InsnID*/0, |
19722 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19723 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19723 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19724 |
// GIR_Coverage, 1751, |
19724 |
// GIR_Coverage, 1751, |
| 19725 |
GIR_Done, |
19725 |
GIR_Done, |
| 19726 |
// Label 1156: @48766 |
19726 |
// Label 1156: @48766 |
| 19727 |
GIM_Try, /*On fail goto*//*Label 1157*/ 48846, // Rule ID 2250 // |
19727 |
GIM_Try, /*On fail goto*//*Label 1157*/ 48846, // Rule ID 2250 // |
| 19728 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
19728 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 19729 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19729 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19730 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
19730 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 19731 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
19731 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, |
| 19732 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
19732 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 19733 |
// (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond)) |
19733 |
// (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond)) |
| 19734 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
19734 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 19735 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
19735 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 19736 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ_MMR6, |
19736 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ_MMR6, |
| 19737 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
19737 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 19738 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f |
19738 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f |
| 19739 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond |
19739 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 19740 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
19740 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 19741 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ_MMR6, |
19741 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ_MMR6, |
| 19742 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
19742 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 19743 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t |
19743 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t |
| 19744 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond |
19744 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 19745 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
19745 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 19746 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR_MM, |
19746 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR_MM, |
| 19747 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19747 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19748 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
19748 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 19749 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
19749 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 19750 |
GIR_EraseFromParent, /*InsnID*/0, |
19750 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19751 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19751 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19752 |
// GIR_Coverage, 2250, |
19752 |
// GIR_Coverage, 2250, |
| 19753 |
GIR_Done, |
19753 |
GIR_Done, |
| 19754 |
// Label 1157: @48846 |
19754 |
// Label 1157: @48846 |
| 19755 |
GIM_Reject, |
19755 |
GIM_Reject, |
| 19756 |
// Label 1076: @48847 |
19756 |
// Label 1076: @48847 |
| 19757 |
GIM_Try, /*On fail goto*//*Label 1158*/ 48928, // Rule ID 1641 // |
19757 |
GIM_Try, /*On fail goto*//*Label 1158*/ 48928, // Rule ID 1641 // |
| 19758 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
19758 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 19759 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19759 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19760 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
19760 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 19761 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
19761 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 19762 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
19762 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 19763 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19763 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19764 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19764 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19765 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19765 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19766 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19766 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19767 |
// MIs[1] Operand 1 |
19767 |
// MIs[1] Operand 1 |
| 19768 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
19768 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 19769 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19769 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19770 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
19770 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 19771 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
19771 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 19772 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
19772 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 19773 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19773 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19774 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F) |
19774 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F) |
| 19775 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
19775 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
| 19776 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19776 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19777 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19777 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19778 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19778 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19779 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19779 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19780 |
GIR_EraseFromParent, /*InsnID*/0, |
19780 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19781 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19781 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19782 |
// GIR_Coverage, 1641, |
19782 |
// GIR_Coverage, 1641, |
| 19783 |
GIR_Done, |
19783 |
GIR_Done, |
| 19784 |
// Label 1158: @48928 |
19784 |
// Label 1158: @48928 |
| 19785 |
GIM_Try, /*On fail goto*//*Label 1159*/ 49009, // Rule ID 1645 // |
19785 |
GIM_Try, /*On fail goto*//*Label 1159*/ 49009, // Rule ID 1645 // |
| 19786 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
19786 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 19787 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19787 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19788 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
19788 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 19789 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
19789 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 19790 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
19790 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 19791 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19791 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19792 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19792 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19793 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
19793 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 19794 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
19794 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 19795 |
// MIs[1] Operand 1 |
19795 |
// MIs[1] Operand 1 |
| 19796 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
19796 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 19797 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
19797 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 19798 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
19798 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 19799 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
19799 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 19800 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
19800 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 19801 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19801 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19802 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F) |
19802 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F) |
| 19803 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I64, |
19803 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I64, |
| 19804 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19804 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19805 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19805 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19806 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19806 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19807 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19807 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19808 |
GIR_EraseFromParent, /*InsnID*/0, |
19808 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19809 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19809 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19810 |
// GIR_Coverage, 1645, |
19810 |
// GIR_Coverage, 1645, |
| 19811 |
GIR_Done, |
19811 |
GIR_Done, |
| 19812 |
// Label 1159: @49009 |
19812 |
// Label 1159: @49009 |
| 19813 |
GIM_Try, /*On fail goto*//*Label 1160*/ 49090, // Rule ID 1651 // |
19813 |
GIM_Try, /*On fail goto*//*Label 1160*/ 49090, // Rule ID 1651 // |
| 19814 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
19814 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 19815 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19815 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19816 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
19816 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 19817 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
19817 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 19818 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
19818 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 19819 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19819 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19820 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19820 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19821 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19821 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19822 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19822 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19823 |
// MIs[1] Operand 1 |
19823 |
// MIs[1] Operand 1 |
| 19824 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
19824 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 19825 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19825 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19826 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
19826 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 19827 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
19827 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 19828 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
19828 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 19829 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19829 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19830 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F) |
19830 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F) |
| 19831 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64, |
19831 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64, |
| 19832 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19832 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19833 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19833 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19834 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19834 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19835 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19835 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19836 |
GIR_EraseFromParent, /*InsnID*/0, |
19836 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19837 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19837 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19838 |
// GIR_Coverage, 1651, |
19838 |
// GIR_Coverage, 1651, |
| 19839 |
GIR_Done, |
19839 |
GIR_Done, |
| 19840 |
// Label 1160: @49090 |
19840 |
// Label 1160: @49090 |
| 19841 |
GIM_Try, /*On fail goto*//*Label 1161*/ 49171, // Rule ID 1657 // |
19841 |
GIM_Try, /*On fail goto*//*Label 1161*/ 49171, // Rule ID 1657 // |
| 19842 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
19842 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 19843 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19843 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19844 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
19844 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 19845 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
19845 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 19846 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
19846 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 19847 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19847 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19848 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19848 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19849 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
19849 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 19850 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
19850 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 19851 |
// MIs[1] Operand 1 |
19851 |
// MIs[1] Operand 1 |
| 19852 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
19852 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 19853 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
19853 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 19854 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
19854 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 19855 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
19855 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 19856 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
19856 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 19857 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19857 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19858 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F) |
19858 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F) |
| 19859 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64, |
19859 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64, |
| 19860 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
19860 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 19861 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19861 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19862 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19862 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19863 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19863 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19864 |
GIR_EraseFromParent, /*InsnID*/0, |
19864 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19865 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19865 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19866 |
// GIR_Coverage, 1657, |
19866 |
// GIR_Coverage, 1657, |
| 19867 |
GIR_Done, |
19867 |
GIR_Done, |
| 19868 |
// Label 1161: @49171 |
19868 |
// Label 1161: @49171 |
| 19869 |
GIM_Try, /*On fail goto*//*Label 1162*/ 49252, // Rule ID 1693 // |
19869 |
GIM_Try, /*On fail goto*//*Label 1162*/ 49252, // Rule ID 1693 // |
| 19870 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
19870 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 19871 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19871 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19872 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
19872 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 19873 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
19873 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 19874 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
19874 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 19875 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19875 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19876 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19876 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19877 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19877 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19878 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19878 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19879 |
// MIs[1] Operand 1 |
19879 |
// MIs[1] Operand 1 |
| 19880 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
19880 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 19881 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19881 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19882 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
19882 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 19883 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
19883 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 19884 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
19884 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 19885 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19885 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19886 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F) |
19886 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F) |
| 19887 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32, |
19887 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32, |
| 19888 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19888 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19889 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19889 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19890 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19890 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19891 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19891 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19892 |
GIR_EraseFromParent, /*InsnID*/0, |
19892 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19893 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19893 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19894 |
// GIR_Coverage, 1693, |
19894 |
// GIR_Coverage, 1693, |
| 19895 |
GIR_Done, |
19895 |
GIR_Done, |
| 19896 |
// Label 1162: @49252 |
19896 |
// Label 1162: @49252 |
| 19897 |
GIM_Try, /*On fail goto*//*Label 1163*/ 49333, // Rule ID 1696 // |
19897 |
GIM_Try, /*On fail goto*//*Label 1163*/ 49333, // Rule ID 1696 // |
| 19898 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
19898 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 19899 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19899 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19900 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
19900 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 19901 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
19901 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 19902 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
19902 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 19903 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19903 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19904 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19904 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19905 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19905 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19906 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19906 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19907 |
// MIs[1] Operand 1 |
19907 |
// MIs[1] Operand 1 |
| 19908 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
19908 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 19909 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19909 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19910 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
19910 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 19911 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
19911 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 19912 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
19912 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 19913 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19913 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19914 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F) |
19914 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F) |
| 19915 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32, |
19915 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32, |
| 19916 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19916 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19917 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19917 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19918 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19918 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19919 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19919 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19920 |
GIR_EraseFromParent, /*InsnID*/0, |
19920 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19921 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19921 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19922 |
// GIR_Coverage, 1696, |
19922 |
// GIR_Coverage, 1696, |
| 19923 |
GIR_Done, |
19923 |
GIR_Done, |
| 19924 |
// Label 1163: @49333 |
19924 |
// Label 1163: @49333 |
| 19925 |
GIM_Try, /*On fail goto*//*Label 1164*/ 49414, // Rule ID 1714 // |
19925 |
GIM_Try, /*On fail goto*//*Label 1164*/ 49414, // Rule ID 1714 // |
| 19926 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
19926 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 19927 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19927 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19928 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
19928 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 19929 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
19929 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 19930 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
19930 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 19931 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19931 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19932 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19932 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19933 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19933 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19934 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19934 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19935 |
// MIs[1] Operand 1 |
19935 |
// MIs[1] Operand 1 |
| 19936 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
19936 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 19937 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19937 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19938 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
19938 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 19939 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
19939 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 19940 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
19940 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 19941 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19941 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19942 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F) |
19942 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F) |
| 19943 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
19943 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
| 19944 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19944 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19945 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19945 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19946 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19946 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19947 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19947 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19948 |
GIR_EraseFromParent, /*InsnID*/0, |
19948 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19949 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19949 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19950 |
// GIR_Coverage, 1714, |
19950 |
// GIR_Coverage, 1714, |
| 19951 |
GIR_Done, |
19951 |
GIR_Done, |
| 19952 |
// Label 1164: @49414 |
19952 |
// Label 1164: @49414 |
| 19953 |
GIM_Try, /*On fail goto*//*Label 1165*/ 49495, // Rule ID 1716 // |
19953 |
GIM_Try, /*On fail goto*//*Label 1165*/ 49495, // Rule ID 1716 // |
| 19954 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
19954 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 19955 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19955 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19956 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
19956 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 19957 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
19957 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 19958 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
19958 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 19959 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19959 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19960 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19960 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19961 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
19961 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 19962 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
19962 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 19963 |
// MIs[1] Operand 1 |
19963 |
// MIs[1] Operand 1 |
| 19964 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
19964 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 19965 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
19965 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 19966 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
19966 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 19967 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
19967 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 19968 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
19968 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 19969 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19969 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19970 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F) |
19970 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F) |
| 19971 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_D64, |
19971 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_D64, |
| 19972 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
19972 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 19973 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
19973 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 19974 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
19974 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 19975 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
19975 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 19976 |
GIR_EraseFromParent, /*InsnID*/0, |
19976 |
GIR_EraseFromParent, /*InsnID*/0, |
| 19977 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
19977 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 19978 |
// GIR_Coverage, 1716, |
19978 |
// GIR_Coverage, 1716, |
| 19979 |
GIR_Done, |
19979 |
GIR_Done, |
| 19980 |
// Label 1165: @49495 |
19980 |
// Label 1165: @49495 |
| 19981 |
GIM_Try, /*On fail goto*//*Label 1166*/ 49576, // Rule ID 1719 // |
19981 |
GIM_Try, /*On fail goto*//*Label 1166*/ 49576, // Rule ID 1719 // |
| 19982 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
19982 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 19983 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
19983 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 19984 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
19984 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 19985 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
19985 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 19986 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
19986 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 19987 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
19987 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 19988 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
19988 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 19989 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
19989 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 19990 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
19990 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 19991 |
// MIs[1] Operand 1 |
19991 |
// MIs[1] Operand 1 |
| 19992 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
19992 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 19993 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
19993 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 19994 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
19994 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 19995 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
19995 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 19996 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
19996 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 19997 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
19997 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 19998 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F) |
19998 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F) |
| 19999 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64, |
19999 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64, |
| 20000 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20000 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20001 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20001 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20002 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20002 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20003 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20003 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20004 |
GIR_EraseFromParent, /*InsnID*/0, |
20004 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20005 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20005 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20006 |
// GIR_Coverage, 1719, |
20006 |
// GIR_Coverage, 1719, |
| 20007 |
GIR_Done, |
20007 |
GIR_Done, |
| 20008 |
// Label 1166: @49576 |
20008 |
// Label 1166: @49576 |
| 20009 |
GIM_Try, /*On fail goto*//*Label 1167*/ 49657, // Rule ID 1722 // |
20009 |
GIM_Try, /*On fail goto*//*Label 1167*/ 49657, // Rule ID 1722 // |
| 20010 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20010 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20011 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20011 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20012 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20012 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20013 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20013 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20014 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
20014 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 20015 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20015 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20016 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20016 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20017 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
20017 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20018 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
20018 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20019 |
// MIs[1] Operand 1 |
20019 |
// MIs[1] Operand 1 |
| 20020 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
20020 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 20021 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20021 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20022 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
20022 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 20023 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
20023 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 20024 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
20024 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 20025 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20025 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20026 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F) |
20026 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F) |
| 20027 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64, |
20027 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64, |
| 20028 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20028 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20029 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20029 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20030 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20030 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20031 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20031 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20032 |
GIR_EraseFromParent, /*InsnID*/0, |
20032 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20033 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20033 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20034 |
// GIR_Coverage, 1722, |
20034 |
// GIR_Coverage, 1722, |
| 20035 |
GIR_Done, |
20035 |
GIR_Done, |
| 20036 |
// Label 1167: @49657 |
20036 |
// Label 1167: @49657 |
| 20037 |
GIM_Try, /*On fail goto*//*Label 1168*/ 49738, // Rule ID 2244 // |
20037 |
GIM_Try, /*On fail goto*//*Label 1168*/ 49738, // Rule ID 2244 // |
| 20038 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
20038 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
| 20039 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20039 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20040 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20040 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20041 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20041 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20042 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
20042 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 20043 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20043 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20044 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20044 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20045 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20045 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20046 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20046 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20047 |
// MIs[1] Operand 1 |
20047 |
// MIs[1] Operand 1 |
| 20048 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
20048 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 20049 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20049 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20050 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
20050 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 20051 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
20051 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 20052 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
20052 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 20053 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20053 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20054 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F) |
20054 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F) |
| 20055 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM, |
20055 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM, |
| 20056 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20056 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20057 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20057 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20058 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20058 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20059 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20059 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20060 |
GIR_EraseFromParent, /*InsnID*/0, |
20060 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20061 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20061 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20062 |
// GIR_Coverage, 2244, |
20062 |
// GIR_Coverage, 2244, |
| 20063 |
GIR_Done, |
20063 |
GIR_Done, |
| 20064 |
// Label 1168: @49738 |
20064 |
// Label 1168: @49738 |
| 20065 |
GIM_Try, /*On fail goto*//*Label 1169*/ 49819, // Rule ID 2247 // |
20065 |
GIM_Try, /*On fail goto*//*Label 1169*/ 49819, // Rule ID 2247 // |
| 20066 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
20066 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
| 20067 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20067 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20068 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20068 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20069 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20069 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20070 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
20070 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 20071 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20071 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20072 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20072 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20073 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20073 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20074 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20074 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20075 |
// MIs[1] Operand 1 |
20075 |
// MIs[1] Operand 1 |
| 20076 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
20076 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 20077 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20077 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20078 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
20078 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, |
| 20079 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
20079 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 20080 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
20080 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 20081 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20081 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20082 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F) |
20082 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F) |
| 20083 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM, |
20083 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM, |
| 20084 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20084 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20085 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20085 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20087 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20087 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20088 |
GIR_EraseFromParent, /*InsnID*/0, |
20088 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20089 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20089 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20090 |
// GIR_Coverage, 2247, |
20090 |
// GIR_Coverage, 2247, |
| 20091 |
GIR_Done, |
20091 |
GIR_Done, |
| 20092 |
// Label 1169: @49819 |
20092 |
// Label 1169: @49819 |
| 20093 |
GIM_Try, /*On fail goto*//*Label 1170*/ 49920, // Rule ID 1616 // |
20093 |
GIM_Try, /*On fail goto*//*Label 1170*/ 49920, // Rule ID 1616 // |
| 20094 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20094 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20095 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20095 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20096 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20096 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20097 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20097 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20098 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
20098 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 20099 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20099 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20100 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20100 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20101 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20101 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20102 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20102 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20103 |
// MIs[1] Operand 1 |
20103 |
// MIs[1] Operand 1 |
| 20104 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
20104 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 20105 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20105 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20106 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20106 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20107 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20107 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20108 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20108 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20109 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20109 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20110 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F) |
20110 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F) |
| 20111 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20111 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20112 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
20112 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
| 20113 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20113 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20114 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20114 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20115 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20115 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20116 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20116 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20117 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
20117 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
| 20118 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
20118 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 20119 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20119 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20120 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20120 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20121 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20121 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20122 |
GIR_EraseFromParent, /*InsnID*/0, |
20122 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20123 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20123 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20124 |
// GIR_Coverage, 1616, |
20124 |
// GIR_Coverage, 1616, |
| 20125 |
GIR_Done, |
20125 |
GIR_Done, |
| 20126 |
// Label 1170: @49920 |
20126 |
// Label 1170: @49920 |
| 20127 |
GIM_Try, /*On fail goto*//*Label 1171*/ 50021, // Rule ID 1617 // |
20127 |
GIM_Try, /*On fail goto*//*Label 1171*/ 50021, // Rule ID 1617 // |
| 20128 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20128 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20129 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20129 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20130 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20130 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20131 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20131 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20132 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
20132 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 20133 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20133 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20134 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20134 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20135 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20135 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20136 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20136 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20137 |
// MIs[1] Operand 1 |
20137 |
// MIs[1] Operand 1 |
| 20138 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
20138 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 20139 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20139 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20140 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20140 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20141 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20141 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20142 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20142 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20143 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20143 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20144 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F) |
20144 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F) |
| 20145 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20145 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20146 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
20146 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
| 20147 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20147 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20148 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20148 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20149 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20149 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20150 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20150 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20151 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
20151 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
| 20152 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
20152 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 20153 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20153 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20154 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20154 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20155 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20155 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20156 |
GIR_EraseFromParent, /*InsnID*/0, |
20156 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20157 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20157 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20158 |
// GIR_Coverage, 1617, |
20158 |
// GIR_Coverage, 1617, |
| 20159 |
GIR_Done, |
20159 |
GIR_Done, |
| 20160 |
// Label 1171: @50021 |
20160 |
// Label 1171: @50021 |
| 20161 |
GIM_Try, /*On fail goto*//*Label 1172*/ 50122, // Rule ID 1620 // |
20161 |
GIM_Try, /*On fail goto*//*Label 1172*/ 50122, // Rule ID 1620 // |
| 20162 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20162 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20163 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20163 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20164 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20164 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20165 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20165 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20166 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
20166 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 20167 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20167 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20168 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20168 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20169 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20169 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20170 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20170 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20171 |
// MIs[1] Operand 1 |
20171 |
// MIs[1] Operand 1 |
| 20172 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
20172 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 20173 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20173 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20174 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20174 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20175 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20175 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20176 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20176 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20177 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20177 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20178 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F) |
20178 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F) |
| 20179 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20179 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20180 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
20180 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
| 20181 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20181 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20182 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20182 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20183 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20183 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20184 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20184 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20185 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
20185 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
| 20186 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
20186 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 20187 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20187 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20188 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20188 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20189 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20189 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20190 |
GIR_EraseFromParent, /*InsnID*/0, |
20190 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20191 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20191 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20192 |
// GIR_Coverage, 1620, |
20192 |
// GIR_Coverage, 1620, |
| 20193 |
GIR_Done, |
20193 |
GIR_Done, |
| 20194 |
// Label 1172: @50122 |
20194 |
// Label 1172: @50122 |
| 20195 |
GIM_Try, /*On fail goto*//*Label 1173*/ 50223, // Rule ID 1621 // |
20195 |
GIM_Try, /*On fail goto*//*Label 1173*/ 50223, // Rule ID 1621 // |
| 20196 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20196 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20197 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20197 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20198 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20198 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20199 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20199 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20200 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
20200 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 20201 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20201 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20202 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20202 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20203 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20203 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20204 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20204 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20205 |
// MIs[1] Operand 1 |
20205 |
// MIs[1] Operand 1 |
| 20206 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
20206 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 20207 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20207 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20208 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20208 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20209 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20209 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20210 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20210 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20211 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20211 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20212 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F) |
20212 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F) |
| 20213 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20213 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20214 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
20214 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
| 20215 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20215 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20216 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20216 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20217 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20217 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20218 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20218 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20219 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
20219 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
| 20220 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
20220 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 20221 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20221 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20222 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20222 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20223 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20223 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20224 |
GIR_EraseFromParent, /*InsnID*/0, |
20224 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20225 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20225 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20226 |
// GIR_Coverage, 1621, |
20226 |
// GIR_Coverage, 1621, |
| 20227 |
GIR_Done, |
20227 |
GIR_Done, |
| 20228 |
// Label 1173: @50223 |
20228 |
// Label 1173: @50223 |
| 20229 |
GIM_Try, /*On fail goto*//*Label 1174*/ 50324, // Rule ID 1632 // |
20229 |
GIM_Try, /*On fail goto*//*Label 1174*/ 50324, // Rule ID 1632 // |
| 20230 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20230 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20231 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20231 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20232 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20232 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20233 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20233 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
20234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 20235 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20235 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20236 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20236 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20237 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
20237 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20238 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
20238 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20239 |
// MIs[1] Operand 1 |
20239 |
// MIs[1] Operand 1 |
| 20240 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
20240 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 20241 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20241 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20242 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20242 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20243 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20243 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20244 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20244 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20245 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20245 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20246 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F) |
20246 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F) |
| 20247 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20247 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20248 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
20248 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
| 20249 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20249 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20250 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20250 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20251 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20251 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20252 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20252 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20253 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
20253 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
| 20254 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
20254 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 20255 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20255 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20256 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20256 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20257 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20257 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20258 |
GIR_EraseFromParent, /*InsnID*/0, |
20258 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20259 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20259 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20260 |
// GIR_Coverage, 1632, |
20260 |
// GIR_Coverage, 1632, |
| 20261 |
GIR_Done, |
20261 |
GIR_Done, |
| 20262 |
// Label 1174: @50324 |
20262 |
// Label 1174: @50324 |
| 20263 |
GIM_Try, /*On fail goto*//*Label 1175*/ 50425, // Rule ID 1633 // |
20263 |
GIM_Try, /*On fail goto*//*Label 1175*/ 50425, // Rule ID 1633 // |
| 20264 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20264 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20265 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20265 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20266 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20266 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20267 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20267 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20268 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
20268 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 20269 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20269 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20270 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20270 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20271 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
20271 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20272 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
20272 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20273 |
// MIs[1] Operand 1 |
20273 |
// MIs[1] Operand 1 |
| 20274 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
20274 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 20275 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20275 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20276 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20276 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20277 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20277 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20279 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20279 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20280 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F) |
20280 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F) |
| 20281 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20281 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20282 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
20282 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
| 20283 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20283 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20284 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20284 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20285 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20285 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20286 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20286 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20287 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
20287 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
| 20288 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
20288 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 20289 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20289 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20290 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20290 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20291 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20291 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20292 |
GIR_EraseFromParent, /*InsnID*/0, |
20292 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20293 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20293 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20294 |
// GIR_Coverage, 1633, |
20294 |
// GIR_Coverage, 1633, |
| 20295 |
GIR_Done, |
20295 |
GIR_Done, |
| 20296 |
// Label 1175: @50425 |
20296 |
// Label 1175: @50425 |
| 20297 |
GIM_Try, /*On fail goto*//*Label 1176*/ 50526, // Rule ID 1636 // |
20297 |
GIM_Try, /*On fail goto*//*Label 1176*/ 50526, // Rule ID 1636 // |
| 20298 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20298 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20299 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20299 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20300 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20300 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20301 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20301 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20302 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
20302 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 20303 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20303 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20304 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20304 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20305 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
20305 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20306 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
20306 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20307 |
// MIs[1] Operand 1 |
20307 |
// MIs[1] Operand 1 |
| 20308 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
20308 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 20309 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20309 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20310 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20310 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20311 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20311 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20312 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20312 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20313 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20313 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20314 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F) |
20314 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F) |
| 20315 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20315 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20316 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
20316 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
| 20317 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20317 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20318 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20318 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20319 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20319 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20320 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20320 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20321 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
20321 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
| 20322 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
20322 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 20323 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20323 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20324 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20324 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20325 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20325 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20326 |
GIR_EraseFromParent, /*InsnID*/0, |
20326 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20327 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20327 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20328 |
// GIR_Coverage, 1636, |
20328 |
// GIR_Coverage, 1636, |
| 20329 |
GIR_Done, |
20329 |
GIR_Done, |
| 20330 |
// Label 1176: @50526 |
20330 |
// Label 1176: @50526 |
| 20331 |
GIM_Try, /*On fail goto*//*Label 1177*/ 50627, // Rule ID 1637 // |
20331 |
GIM_Try, /*On fail goto*//*Label 1177*/ 50627, // Rule ID 1637 // |
| 20332 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20332 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20333 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20333 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20334 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20334 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20335 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20335 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20336 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
20336 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 20337 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20337 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20338 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20338 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20339 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
20339 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20340 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
20340 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20341 |
// MIs[1] Operand 1 |
20341 |
// MIs[1] Operand 1 |
| 20342 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
20342 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 20343 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20343 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20344 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20344 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20345 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20345 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20346 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20346 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20347 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20347 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20348 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F) |
20348 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F) |
| 20349 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20349 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20350 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
20350 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
| 20351 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20351 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20352 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20352 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20353 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20353 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20354 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20354 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20355 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
20355 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
| 20356 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
20356 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 20357 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20357 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20358 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20358 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20359 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20359 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20360 |
GIR_EraseFromParent, /*InsnID*/0, |
20360 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20361 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20361 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20362 |
// GIR_Coverage, 1637, |
20362 |
// GIR_Coverage, 1637, |
| 20363 |
GIR_Done, |
20363 |
GIR_Done, |
| 20364 |
// Label 1177: @50627 |
20364 |
// Label 1177: @50627 |
| 20365 |
GIM_Try, /*On fail goto*//*Label 1178*/ 50728, // Rule ID 1640 // |
20365 |
GIM_Try, /*On fail goto*//*Label 1178*/ 50728, // Rule ID 1640 // |
| 20366 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20366 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20367 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20367 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20368 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20368 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20369 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20369 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20370 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
20370 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 20371 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20371 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20372 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20372 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20373 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20373 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20374 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20374 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20375 |
// MIs[1] Operand 1 |
20375 |
// MIs[1] Operand 1 |
| 20376 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
20376 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 20377 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20377 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20378 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20378 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20379 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20379 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20380 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20380 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20381 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20381 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20382 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F) |
20382 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F) |
| 20383 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20383 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20384 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
20384 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
| 20385 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20385 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20386 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20386 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20387 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20387 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20388 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20388 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20389 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
20389 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_I64, |
| 20390 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
20390 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 20391 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20391 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20392 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20392 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20393 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20393 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20394 |
GIR_EraseFromParent, /*InsnID*/0, |
20394 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20395 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20395 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20396 |
// GIR_Coverage, 1640, |
20396 |
// GIR_Coverage, 1640, |
| 20397 |
GIR_Done, |
20397 |
GIR_Done, |
| 20398 |
// Label 1178: @50728 |
20398 |
// Label 1178: @50728 |
| 20399 |
GIM_Try, /*On fail goto*//*Label 1179*/ 50829, // Rule ID 1644 // |
20399 |
GIM_Try, /*On fail goto*//*Label 1179*/ 50829, // Rule ID 1644 // |
| 20400 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20400 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20401 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20401 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20402 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20402 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20403 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20403 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20404 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
20404 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 20405 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20405 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20406 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20406 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20407 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
20407 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20408 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
20408 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20409 |
// MIs[1] Operand 1 |
20409 |
// MIs[1] Operand 1 |
| 20410 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
20410 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 20411 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20411 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20412 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20412 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20413 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20413 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20414 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20414 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20415 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20415 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20416 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F) |
20416 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F) |
| 20417 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
20417 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 20418 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
20418 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
| 20419 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20419 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20420 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20420 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20421 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20421 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20422 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20422 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20423 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I64, |
20423 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_I64, |
| 20424 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
20424 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 20425 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20425 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20426 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20426 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20427 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20427 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20428 |
GIR_EraseFromParent, /*InsnID*/0, |
20428 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20429 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20429 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20430 |
// GIR_Coverage, 1644, |
20430 |
// GIR_Coverage, 1644, |
| 20431 |
GIR_Done, |
20431 |
GIR_Done, |
| 20432 |
// Label 1179: @50829 |
20432 |
// Label 1179: @50829 |
| 20433 |
GIM_Try, /*On fail goto*//*Label 1180*/ 50930, // Rule ID 1649 // |
20433 |
GIM_Try, /*On fail goto*//*Label 1180*/ 50930, // Rule ID 1649 // |
| 20434 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20434 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20435 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20435 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20436 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20436 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20437 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20437 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20438 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
20438 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 20439 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20439 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20440 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20440 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20441 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20441 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20442 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20442 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20443 |
// MIs[1] Operand 1 |
20443 |
// MIs[1] Operand 1 |
| 20444 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
20444 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 20445 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20445 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20446 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20446 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20447 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20447 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20448 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20448 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20449 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20449 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20450 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F) |
20450 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F) |
| 20451 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20451 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20452 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
20452 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
| 20453 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20453 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20454 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20454 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20455 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20455 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20456 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20456 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20457 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64, |
20457 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64, |
| 20458 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
20458 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 20459 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20459 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20460 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20460 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20461 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20461 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20462 |
GIR_EraseFromParent, /*InsnID*/0, |
20462 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20463 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20463 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20464 |
// GIR_Coverage, 1649, |
20464 |
// GIR_Coverage, 1649, |
| 20465 |
GIR_Done, |
20465 |
GIR_Done, |
| 20466 |
// Label 1180: @50930 |
20466 |
// Label 1180: @50930 |
| 20467 |
GIM_Try, /*On fail goto*//*Label 1181*/ 51031, // Rule ID 1655 // |
20467 |
GIM_Try, /*On fail goto*//*Label 1181*/ 51031, // Rule ID 1655 // |
| 20468 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20468 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20469 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20469 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20470 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20470 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20471 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20471 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20472 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
20472 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 20473 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20473 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20474 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20474 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20475 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
20475 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20476 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
20476 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20477 |
// MIs[1] Operand 1 |
20477 |
// MIs[1] Operand 1 |
| 20478 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
20478 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 20479 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20479 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20480 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20480 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20481 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20481 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20482 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20482 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20483 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20483 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20484 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F) |
20484 |
// (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F) |
| 20485 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
20485 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 20486 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
20486 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
| 20487 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20487 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20488 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20488 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20489 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20489 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20490 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20490 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20491 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64, |
20491 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64, |
| 20492 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
20492 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 20493 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20493 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20494 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20494 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20495 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20495 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20496 |
GIR_EraseFromParent, /*InsnID*/0, |
20496 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20497 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20497 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20498 |
// GIR_Coverage, 1655, |
20498 |
// GIR_Coverage, 1655, |
| 20499 |
GIR_Done, |
20499 |
GIR_Done, |
| 20500 |
// Label 1181: @51031 |
20500 |
// Label 1181: @51031 |
| 20501 |
GIM_Try, /*On fail goto*//*Label 1182*/ 51132, // Rule ID 1684 // |
20501 |
GIM_Try, /*On fail goto*//*Label 1182*/ 51132, // Rule ID 1684 // |
| 20502 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20502 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20503 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20503 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20504 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20504 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20505 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20505 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20506 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
20506 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 20507 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20507 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20508 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20508 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20509 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20509 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20510 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20510 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20511 |
// MIs[1] Operand 1 |
20511 |
// MIs[1] Operand 1 |
| 20512 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
20512 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 20513 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20513 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20514 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20514 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20515 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
20515 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 20516 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
20516 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 20517 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20517 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20518 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
20518 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
| 20519 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20519 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20520 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
20520 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
| 20521 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20521 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20522 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20522 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20523 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20523 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20524 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20524 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20525 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32, |
20525 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32, |
| 20526 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20526 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20527 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20527 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20528 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20528 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20529 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20529 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20530 |
GIR_EraseFromParent, /*InsnID*/0, |
20530 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20531 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20531 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20532 |
// GIR_Coverage, 1684, |
20532 |
// GIR_Coverage, 1684, |
| 20533 |
GIR_Done, |
20533 |
GIR_Done, |
| 20534 |
// Label 1182: @51132 |
20534 |
// Label 1182: @51132 |
| 20535 |
GIM_Try, /*On fail goto*//*Label 1183*/ 51233, // Rule ID 1685 // |
20535 |
GIM_Try, /*On fail goto*//*Label 1183*/ 51233, // Rule ID 1685 // |
| 20536 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20536 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20537 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20537 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20538 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20538 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20539 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20539 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20540 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
20540 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 20541 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20541 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20542 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20542 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20543 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20543 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20544 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20544 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20545 |
// MIs[1] Operand 1 |
20545 |
// MIs[1] Operand 1 |
| 20546 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
20546 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 20547 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20547 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20548 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20548 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20549 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
20549 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 20550 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
20550 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 20551 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20551 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20552 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
20552 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
| 20553 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20553 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20554 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
20554 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
| 20555 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20555 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20556 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20556 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20557 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20557 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20558 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20558 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20559 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32, |
20559 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32, |
| 20560 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20560 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20561 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20561 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20562 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20562 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20563 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20563 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20564 |
GIR_EraseFromParent, /*InsnID*/0, |
20564 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20565 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20565 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20566 |
// GIR_Coverage, 1685, |
20566 |
// GIR_Coverage, 1685, |
| 20567 |
GIR_Done, |
20567 |
GIR_Done, |
| 20568 |
// Label 1183: @51233 |
20568 |
// Label 1183: @51233 |
| 20569 |
GIM_Try, /*On fail goto*//*Label 1184*/ 51334, // Rule ID 1688 // |
20569 |
GIM_Try, /*On fail goto*//*Label 1184*/ 51334, // Rule ID 1688 // |
| 20570 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20570 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20571 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20571 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20572 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20572 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20573 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20573 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20574 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
20574 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 20575 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20575 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20576 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20576 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20577 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20577 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20578 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20578 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20579 |
// MIs[1] Operand 1 |
20579 |
// MIs[1] Operand 1 |
| 20580 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
20580 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 20581 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20581 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20582 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20582 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20583 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
20583 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 20584 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
20584 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 20585 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20585 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20586 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F) |
20586 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F) |
| 20587 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20587 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20588 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
20588 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
| 20589 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20589 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20590 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20590 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20591 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20591 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20592 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20592 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20593 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32, |
20593 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32, |
| 20594 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20594 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20595 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20595 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20596 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20596 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20597 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20597 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20598 |
GIR_EraseFromParent, /*InsnID*/0, |
20598 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20599 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20599 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20600 |
// GIR_Coverage, 1688, |
20600 |
// GIR_Coverage, 1688, |
| 20601 |
GIR_Done, |
20601 |
GIR_Done, |
| 20602 |
// Label 1184: @51334 |
20602 |
// Label 1184: @51334 |
| 20603 |
GIM_Try, /*On fail goto*//*Label 1185*/ 51435, // Rule ID 1689 // |
20603 |
GIM_Try, /*On fail goto*//*Label 1185*/ 51435, // Rule ID 1689 // |
| 20604 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20604 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20605 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20605 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20606 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20606 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20607 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20607 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20608 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
20608 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 20609 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20609 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20610 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20610 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20611 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20611 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20612 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20612 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20613 |
// MIs[1] Operand 1 |
20613 |
// MIs[1] Operand 1 |
| 20614 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
20614 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 20615 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20615 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20616 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20616 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20617 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
20617 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 20618 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
20618 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 20619 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20619 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20620 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F) |
20620 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F) |
| 20621 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20621 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20622 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
20622 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
| 20623 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20623 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20624 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20624 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20625 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20625 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20626 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20626 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20627 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32, |
20627 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32, |
| 20628 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20628 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20629 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20629 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20630 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20630 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20631 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20631 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20632 |
GIR_EraseFromParent, /*InsnID*/0, |
20632 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20633 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20633 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20634 |
// GIR_Coverage, 1689, |
20634 |
// GIR_Coverage, 1689, |
| 20635 |
GIR_Done, |
20635 |
GIR_Done, |
| 20636 |
// Label 1185: @51435 |
20636 |
// Label 1185: @51435 |
| 20637 |
GIM_Try, /*On fail goto*//*Label 1186*/ 51536, // Rule ID 1692 // |
20637 |
GIM_Try, /*On fail goto*//*Label 1186*/ 51536, // Rule ID 1692 // |
| 20638 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20638 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20639 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20639 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20640 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20640 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20641 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20641 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20642 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
20642 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 20643 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20643 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20644 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20644 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20645 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20645 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20646 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20646 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20647 |
// MIs[1] Operand 1 |
20647 |
// MIs[1] Operand 1 |
| 20648 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
20648 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 20649 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20649 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20650 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20650 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20651 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
20651 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 20652 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
20652 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 20653 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20653 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20654 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
20654 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
| 20655 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20655 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20656 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
20656 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
| 20657 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20657 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20658 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20658 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20659 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20659 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20660 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20660 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20661 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32, |
20661 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32, |
| 20662 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20662 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20663 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20663 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20664 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20664 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20665 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20665 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20666 |
GIR_EraseFromParent, /*InsnID*/0, |
20666 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20667 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20667 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20668 |
// GIR_Coverage, 1692, |
20668 |
// GIR_Coverage, 1692, |
| 20669 |
GIR_Done, |
20669 |
GIR_Done, |
| 20670 |
// Label 1186: @51536 |
20670 |
// Label 1186: @51536 |
| 20671 |
GIM_Try, /*On fail goto*//*Label 1187*/ 51637, // Rule ID 1694 // |
20671 |
GIM_Try, /*On fail goto*//*Label 1187*/ 51637, // Rule ID 1694 // |
| 20672 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20672 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20673 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20673 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20674 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20674 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20675 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20675 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20676 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
20676 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 20677 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20677 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20678 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20678 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20679 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20679 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20680 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20680 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20681 |
// MIs[1] Operand 1 |
20681 |
// MIs[1] Operand 1 |
| 20682 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
20682 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 20683 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20683 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20684 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20684 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20685 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
20685 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 20686 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
20686 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 20687 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20687 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20688 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
20688 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
| 20689 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20689 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20690 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
20690 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
| 20691 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20691 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20692 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20692 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20693 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20693 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20694 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20694 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20695 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32, |
20695 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32, |
| 20696 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20696 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20697 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20697 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20698 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20698 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20699 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20699 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20700 |
GIR_EraseFromParent, /*InsnID*/0, |
20700 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20701 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20701 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20702 |
// GIR_Coverage, 1694, |
20702 |
// GIR_Coverage, 1694, |
| 20703 |
GIR_Done, |
20703 |
GIR_Done, |
| 20704 |
// Label 1187: @51637 |
20704 |
// Label 1187: @51637 |
| 20705 |
GIM_Try, /*On fail goto*//*Label 1188*/ 51738, // Rule ID 1697 // |
20705 |
GIM_Try, /*On fail goto*//*Label 1188*/ 51738, // Rule ID 1697 // |
| 20706 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20706 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20707 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20707 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20708 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20708 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20709 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20709 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20710 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
20710 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 20711 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20711 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20712 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20712 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20713 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20713 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20714 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20714 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20715 |
// MIs[1] Operand 1 |
20715 |
// MIs[1] Operand 1 |
| 20716 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
20716 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 20717 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20717 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20718 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20718 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20719 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
20719 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 20720 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
20720 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 20721 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20721 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20722 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F) |
20722 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F) |
| 20723 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20723 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20724 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
20724 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
| 20725 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20725 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20726 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20726 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20727 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20727 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20728 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20728 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20729 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
20729 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
| 20730 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20730 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20731 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20731 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20732 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20732 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20733 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20733 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20734 |
GIR_EraseFromParent, /*InsnID*/0, |
20734 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20735 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20735 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20736 |
// GIR_Coverage, 1697, |
20736 |
// GIR_Coverage, 1697, |
| 20737 |
GIR_Done, |
20737 |
GIR_Done, |
| 20738 |
// Label 1188: @51738 |
20738 |
// Label 1188: @51738 |
| 20739 |
GIM_Try, /*On fail goto*//*Label 1189*/ 51839, // Rule ID 1698 // |
20739 |
GIM_Try, /*On fail goto*//*Label 1189*/ 51839, // Rule ID 1698 // |
| 20740 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20740 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20741 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20741 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20742 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20742 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20743 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20743 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20744 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
20744 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 20745 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20745 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20746 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20746 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20747 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20747 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20748 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20748 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20749 |
// MIs[1] Operand 1 |
20749 |
// MIs[1] Operand 1 |
| 20750 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
20750 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 20751 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20751 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20752 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20752 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20753 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
20753 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 20754 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
20754 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 20755 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20755 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20756 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F) |
20756 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F) |
| 20757 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20757 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20758 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
20758 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
| 20759 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20759 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20760 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20760 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20761 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20761 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20762 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20762 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20763 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
20763 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
| 20764 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20764 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20765 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20766 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20766 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20767 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20767 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20768 |
GIR_EraseFromParent, /*InsnID*/0, |
20768 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20769 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20769 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20770 |
// GIR_Coverage, 1698, |
20770 |
// GIR_Coverage, 1698, |
| 20771 |
GIR_Done, |
20771 |
GIR_Done, |
| 20772 |
// Label 1189: @51839 |
20772 |
// Label 1189: @51839 |
| 20773 |
GIM_Try, /*On fail goto*//*Label 1190*/ 51940, // Rule ID 1701 // |
20773 |
GIM_Try, /*On fail goto*//*Label 1190*/ 51940, // Rule ID 1701 // |
| 20774 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20774 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20775 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20775 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20776 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20776 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20777 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20777 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
20778 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 20779 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20779 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20780 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20780 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20781 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20781 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20782 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20782 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20783 |
// MIs[1] Operand 1 |
20783 |
// MIs[1] Operand 1 |
| 20784 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
20784 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 20785 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20785 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20786 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20786 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20787 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
20787 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 20788 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
20788 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 20789 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20789 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20790 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F) |
20790 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F) |
| 20791 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20791 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20792 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
20792 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT, |
| 20793 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20793 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20794 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20794 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20795 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20795 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20796 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20796 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20797 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
20797 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
| 20798 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20798 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20799 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20799 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20800 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20800 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20801 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20801 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20802 |
GIR_EraseFromParent, /*InsnID*/0, |
20802 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20803 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20803 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20804 |
// GIR_Coverage, 1701, |
20804 |
// GIR_Coverage, 1701, |
| 20805 |
GIR_Done, |
20805 |
GIR_Done, |
| 20806 |
// Label 1190: @51940 |
20806 |
// Label 1190: @51940 |
| 20807 |
GIM_Try, /*On fail goto*//*Label 1191*/ 52041, // Rule ID 1702 // |
20807 |
GIM_Try, /*On fail goto*//*Label 1191*/ 52041, // Rule ID 1702 // |
| 20808 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20808 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20809 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20809 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20810 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20810 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20811 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20811 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20812 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
20812 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 20813 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20813 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20814 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20814 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20815 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20815 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20816 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20816 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20817 |
// MIs[1] Operand 1 |
20817 |
// MIs[1] Operand 1 |
| 20818 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
20818 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 20819 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20819 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20820 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20820 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20821 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
20821 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 20822 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
20822 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 20823 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20823 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20824 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F) |
20824 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F) |
| 20825 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20825 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20826 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
20826 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu, |
| 20827 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20827 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20828 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20828 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20829 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20829 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20830 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20830 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20831 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
20831 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
| 20832 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20832 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20833 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20833 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20834 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20834 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20835 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20835 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20836 |
GIR_EraseFromParent, /*InsnID*/0, |
20836 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20837 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20837 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20838 |
// GIR_Coverage, 1702, |
20838 |
// GIR_Coverage, 1702, |
| 20839 |
GIR_Done, |
20839 |
GIR_Done, |
| 20840 |
// Label 1191: @52041 |
20840 |
// Label 1191: @52041 |
| 20841 |
GIM_Try, /*On fail goto*//*Label 1192*/ 52142, // Rule ID 1705 // |
20841 |
GIM_Try, /*On fail goto*//*Label 1192*/ 52142, // Rule ID 1705 // |
| 20842 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20842 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20843 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20843 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20844 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20844 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20845 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20845 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20846 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
20846 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 20847 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20847 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20848 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20848 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20849 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
20849 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20850 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
20850 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20851 |
// MIs[1] Operand 1 |
20851 |
// MIs[1] Operand 1 |
| 20852 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
20852 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 20853 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20853 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20854 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20854 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20855 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
20855 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 20856 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
20856 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 20857 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20857 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20858 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F) |
20858 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F) |
| 20859 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20859 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20860 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
20860 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
| 20861 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20861 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20862 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20862 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20863 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20863 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20864 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20864 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20865 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
20865 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
| 20866 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20866 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20867 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20867 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20868 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20868 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20869 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20869 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20870 |
GIR_EraseFromParent, /*InsnID*/0, |
20870 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20871 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20871 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20872 |
// GIR_Coverage, 1705, |
20872 |
// GIR_Coverage, 1705, |
| 20873 |
GIR_Done, |
20873 |
GIR_Done, |
| 20874 |
// Label 1192: @52142 |
20874 |
// Label 1192: @52142 |
| 20875 |
GIM_Try, /*On fail goto*//*Label 1193*/ 52243, // Rule ID 1706 // |
20875 |
GIM_Try, /*On fail goto*//*Label 1193*/ 52243, // Rule ID 1706 // |
| 20876 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20876 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20877 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20877 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20878 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20878 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20879 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20879 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20880 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
20880 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 20881 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20881 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20882 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20882 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20883 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
20883 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20884 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
20884 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20885 |
// MIs[1] Operand 1 |
20885 |
// MIs[1] Operand 1 |
| 20886 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
20886 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 20887 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20887 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20888 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20888 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20889 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
20889 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 20890 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
20890 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 20891 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20891 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20892 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F) |
20892 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F) |
| 20893 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20893 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20894 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
20894 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
| 20895 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20895 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20896 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20896 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20897 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20897 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20898 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20898 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20899 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
20899 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
| 20900 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20900 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20901 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20901 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20902 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20902 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20903 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20903 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20904 |
GIR_EraseFromParent, /*InsnID*/0, |
20904 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20905 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20905 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20906 |
// GIR_Coverage, 1706, |
20906 |
// GIR_Coverage, 1706, |
| 20907 |
GIR_Done, |
20907 |
GIR_Done, |
| 20908 |
// Label 1193: @52243 |
20908 |
// Label 1193: @52243 |
| 20909 |
GIM_Try, /*On fail goto*//*Label 1194*/ 52344, // Rule ID 1709 // |
20909 |
GIM_Try, /*On fail goto*//*Label 1194*/ 52344, // Rule ID 1709 // |
| 20910 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20910 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20911 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20911 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20912 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20912 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20913 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20913 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20914 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
20914 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 20915 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20915 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20916 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20916 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20917 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
20917 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20918 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
20918 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20919 |
// MIs[1] Operand 1 |
20919 |
// MIs[1] Operand 1 |
| 20920 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
20920 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 20921 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20921 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20922 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20922 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20923 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
20923 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 20924 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
20924 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 20925 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20925 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20926 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F) |
20926 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F) |
| 20927 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20927 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20928 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
20928 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT64, |
| 20929 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20929 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20930 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20930 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20931 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20931 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20932 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20932 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20933 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
20933 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
| 20934 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20934 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20935 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20935 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20936 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20936 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20937 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20937 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20938 |
GIR_EraseFromParent, /*InsnID*/0, |
20938 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20939 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20939 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20940 |
// GIR_Coverage, 1709, |
20940 |
// GIR_Coverage, 1709, |
| 20941 |
GIR_Done, |
20941 |
GIR_Done, |
| 20942 |
// Label 1194: @52344 |
20942 |
// Label 1194: @52344 |
| 20943 |
GIM_Try, /*On fail goto*//*Label 1195*/ 52445, // Rule ID 1710 // |
20943 |
GIM_Try, /*On fail goto*//*Label 1195*/ 52445, // Rule ID 1710 // |
| 20944 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20944 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20945 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20945 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20946 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20946 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20947 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20947 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20948 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
20948 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 20949 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20949 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20950 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20950 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20951 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
20951 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 20952 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
20952 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 20953 |
// MIs[1] Operand 1 |
20953 |
// MIs[1] Operand 1 |
| 20954 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
20954 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 20955 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
20955 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 20956 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
20956 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 20957 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
20957 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 20958 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
20958 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 20959 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20959 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20960 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F) |
20960 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F) |
| 20961 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20961 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20962 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
20962 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu64, |
| 20963 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20963 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20964 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20964 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 20965 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20965 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20966 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
20966 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 20967 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
20967 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
| 20968 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
20968 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 20969 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
20969 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 20970 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
20970 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 20971 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
20971 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 20972 |
GIR_EraseFromParent, /*InsnID*/0, |
20972 |
GIR_EraseFromParent, /*InsnID*/0, |
| 20973 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
20973 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 20974 |
// GIR_Coverage, 1710, |
20974 |
// GIR_Coverage, 1710, |
| 20975 |
GIR_Done, |
20975 |
GIR_Done, |
| 20976 |
// Label 1195: @52445 |
20976 |
// Label 1195: @52445 |
| 20977 |
GIM_Try, /*On fail goto*//*Label 1196*/ 52546, // Rule ID 1713 // |
20977 |
GIM_Try, /*On fail goto*//*Label 1196*/ 52546, // Rule ID 1713 // |
| 20978 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
20978 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 20979 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
20979 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 20980 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
20980 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 20981 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
20981 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 20982 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
20982 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 20983 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
20983 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 20984 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
20984 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 20985 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
20985 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 20986 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
20986 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 20987 |
// MIs[1] Operand 1 |
20987 |
// MIs[1] Operand 1 |
| 20988 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
20988 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 20989 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
20989 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 20990 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
20990 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 20991 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
20991 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 20992 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
20992 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 20993 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
20993 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 20994 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F) |
20994 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F) |
| 20995 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
20995 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 20996 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
20996 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
| 20997 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
20997 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 20998 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
20998 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 20999 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
20999 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 21000 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
21000 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21001 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
21001 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D64, |
| 21002 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21002 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21003 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21003 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21004 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
21004 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21005 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21005 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21006 |
GIR_EraseFromParent, /*InsnID*/0, |
21006 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21007 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21007 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21008 |
// GIR_Coverage, 1713, |
21008 |
// GIR_Coverage, 1713, |
| 21009 |
GIR_Done, |
21009 |
GIR_Done, |
| 21010 |
// Label 1196: @52546 |
21010 |
// Label 1196: @52546 |
| 21011 |
GIM_Try, /*On fail goto*//*Label 1197*/ 52647, // Rule ID 1715 // |
21011 |
GIM_Try, /*On fail goto*//*Label 1197*/ 52647, // Rule ID 1715 // |
| 21012 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
21012 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21013 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21013 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21014 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21014 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21015 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21015 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
21016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 21017 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21017 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21018 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
21018 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 21019 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
21019 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 21020 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
21020 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 21021 |
// MIs[1] Operand 1 |
21021 |
// MIs[1] Operand 1 |
| 21022 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
21022 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 21023 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
21023 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 21024 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
21024 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 21025 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
21025 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 21026 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
21026 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 21027 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21027 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21028 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F) |
21028 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F) |
| 21029 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
21029 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21030 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
21030 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
| 21031 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
21031 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21032 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
21032 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 21033 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
21033 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 21034 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
21034 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21035 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_D64, |
21035 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I64_D64, |
| 21036 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21036 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21037 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21037 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21038 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
21038 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21039 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21039 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21040 |
GIR_EraseFromParent, /*InsnID*/0, |
21040 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21041 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21041 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21042 |
// GIR_Coverage, 1715, |
21042 |
// GIR_Coverage, 1715, |
| 21043 |
GIR_Done, |
21043 |
GIR_Done, |
| 21044 |
// Label 1197: @52647 |
21044 |
// Label 1197: @52647 |
| 21045 |
GIM_Try, /*On fail goto*//*Label 1198*/ 52748, // Rule ID 1717 // |
21045 |
GIM_Try, /*On fail goto*//*Label 1198*/ 52748, // Rule ID 1717 // |
| 21046 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
21046 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21047 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21047 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21048 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21048 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21049 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21049 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21050 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
21050 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 21051 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21051 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21052 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
21052 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 21053 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
21053 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 21054 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
21054 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 21055 |
// MIs[1] Operand 1 |
21055 |
// MIs[1] Operand 1 |
| 21056 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
21056 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 21057 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
21057 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 21058 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
21058 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 21059 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
21059 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 21060 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
21060 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 21061 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21061 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21062 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F) |
21062 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F) |
| 21063 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
21063 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21064 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
21064 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR, |
| 21065 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
21065 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21066 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
21066 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 21067 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
21067 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 21068 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
21068 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21069 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64, |
21069 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64, |
| 21070 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21070 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21071 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21071 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21072 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
21072 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21073 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21073 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21074 |
GIR_EraseFromParent, /*InsnID*/0, |
21074 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21075 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21075 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21076 |
// GIR_Coverage, 1717, |
21076 |
// GIR_Coverage, 1717, |
| 21077 |
GIR_Done, |
21077 |
GIR_Done, |
| 21078 |
// Label 1198: @52748 |
21078 |
// Label 1198: @52748 |
| 21079 |
GIM_Try, /*On fail goto*//*Label 1199*/ 52849, // Rule ID 1720 // |
21079 |
GIM_Try, /*On fail goto*//*Label 1199*/ 52849, // Rule ID 1720 // |
| 21080 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
21080 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21081 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21081 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21082 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21082 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21083 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21083 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21084 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
21084 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 21085 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21085 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21086 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
21086 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 21087 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
21087 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 21088 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
21088 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 21089 |
// MIs[1] Operand 1 |
21089 |
// MIs[1] Operand 1 |
| 21090 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
21090 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 21091 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
21091 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 21092 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
21092 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 21093 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
21093 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 21094 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
21094 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 21095 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21095 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21096 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F) |
21096 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F) |
| 21097 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
21097 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21098 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
21098 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR64, |
| 21099 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
21099 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21100 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
21100 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 21101 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
21101 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 21102 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
21102 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21103 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64, |
21103 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64, |
| 21104 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21104 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21105 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21105 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21106 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
21106 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21107 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21107 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21108 |
GIR_EraseFromParent, /*InsnID*/0, |
21108 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21109 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21109 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21110 |
// GIR_Coverage, 1720, |
21110 |
// GIR_Coverage, 1720, |
| 21111 |
GIR_Done, |
21111 |
GIR_Done, |
| 21112 |
// Label 1199: @52849 |
21112 |
// Label 1199: @52849 |
| 21113 |
GIM_Try, /*On fail goto*//*Label 1200*/ 52950, // Rule ID 2235 // |
21113 |
GIM_Try, /*On fail goto*//*Label 1200*/ 52950, // Rule ID 2235 // |
| 21114 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
21114 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
| 21115 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21115 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21116 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21116 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21117 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21117 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21118 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
21118 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 21119 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21119 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21120 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
21120 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 21121 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
21121 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 21122 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
21122 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 21123 |
// MIs[1] Operand 1 |
21123 |
// MIs[1] Operand 1 |
| 21124 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
21124 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, |
| 21125 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
21125 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 21126 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
21126 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 21127 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21127 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21128 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
21128 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 21129 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21129 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21130 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
21130 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
| 21131 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
21131 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21132 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
21132 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
| 21133 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
21133 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21134 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
21134 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 21135 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
21135 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 21136 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
21136 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21137 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM, |
21137 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM, |
| 21138 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21138 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21139 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21139 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21140 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
21140 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21141 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21141 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21142 |
GIR_EraseFromParent, /*InsnID*/0, |
21142 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21143 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21143 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21144 |
// GIR_Coverage, 2235, |
21144 |
// GIR_Coverage, 2235, |
| 21145 |
GIR_Done, |
21145 |
GIR_Done, |
| 21146 |
// Label 1200: @52950 |
21146 |
// Label 1200: @52950 |
| 21147 |
GIM_Try, /*On fail goto*//*Label 1201*/ 53051, // Rule ID 2236 // |
21147 |
GIM_Try, /*On fail goto*//*Label 1201*/ 53051, // Rule ID 2236 // |
| 21148 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
21148 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
| 21149 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21149 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21150 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21150 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21151 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21151 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21152 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
21152 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 21153 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21153 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21154 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
21154 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 21155 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
21155 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 21156 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
21156 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 21157 |
// MIs[1] Operand 1 |
21157 |
// MIs[1] Operand 1 |
| 21158 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
21158 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, |
| 21159 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
21159 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 21160 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
21160 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 21161 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21161 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21162 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
21162 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 21163 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21163 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21164 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
21164 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
| 21165 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
21165 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21166 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
21166 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
| 21167 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
21167 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21168 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
21168 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 21169 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
21169 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 21170 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
21170 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21171 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM, |
21171 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM, |
| 21172 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21172 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21173 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21173 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21174 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
21174 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21175 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21175 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21176 |
GIR_EraseFromParent, /*InsnID*/0, |
21176 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21177 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21177 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21178 |
// GIR_Coverage, 2236, |
21178 |
// GIR_Coverage, 2236, |
| 21179 |
GIR_Done, |
21179 |
GIR_Done, |
| 21180 |
// Label 1201: @53051 |
21180 |
// Label 1201: @53051 |
| 21181 |
GIM_Try, /*On fail goto*//*Label 1202*/ 53152, // Rule ID 2239 // |
21181 |
GIM_Try, /*On fail goto*//*Label 1202*/ 53152, // Rule ID 2239 // |
| 21182 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
21182 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
| 21183 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21183 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21184 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21184 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21185 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21185 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21186 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
21186 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 21187 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21187 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21188 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
21188 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 21189 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
21189 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 21190 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
21190 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 21191 |
// MIs[1] Operand 1 |
21191 |
// MIs[1] Operand 1 |
| 21192 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
21192 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, |
| 21193 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
21193 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 21194 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
21194 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 21195 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21195 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21196 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
21196 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 21197 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21197 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21198 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F) |
21198 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F) |
| 21199 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
21199 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21200 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
21200 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLT_MM, |
| 21201 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
21201 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21202 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
21202 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 21203 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
21203 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 21204 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
21204 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21205 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM, |
21205 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM, |
| 21206 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21206 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21207 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21207 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21208 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
21208 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21209 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21209 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21210 |
GIR_EraseFromParent, /*InsnID*/0, |
21210 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21211 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21211 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21212 |
// GIR_Coverage, 2239, |
21212 |
// GIR_Coverage, 2239, |
| 21213 |
GIR_Done, |
21213 |
GIR_Done, |
| 21214 |
// Label 1202: @53152 |
21214 |
// Label 1202: @53152 |
| 21215 |
GIM_Try, /*On fail goto*//*Label 1203*/ 53253, // Rule ID 2240 // |
21215 |
GIM_Try, /*On fail goto*//*Label 1203*/ 53253, // Rule ID 2240 // |
| 21216 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
21216 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
| 21217 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21217 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21218 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21218 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21219 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21219 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21220 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
21220 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 21221 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21221 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21222 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
21222 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 21223 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
21223 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 21224 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
21224 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 21225 |
// MIs[1] Operand 1 |
21225 |
// MIs[1] Operand 1 |
| 21226 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
21226 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, |
| 21227 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
21227 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 21228 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
21228 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 21229 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21229 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21230 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
21230 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 21231 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21231 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21232 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F) |
21232 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F) |
| 21233 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
21233 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21234 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
21234 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SLTu_MM, |
| 21235 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
21235 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21236 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
21236 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 21237 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
21237 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 21238 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
21238 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21239 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM, |
21239 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM, |
| 21240 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21240 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21241 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21241 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21242 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
21242 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21243 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21243 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21244 |
GIR_EraseFromParent, /*InsnID*/0, |
21244 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21245 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21245 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21246 |
// GIR_Coverage, 2240, |
21246 |
// GIR_Coverage, 2240, |
| 21247 |
GIR_Done, |
21247 |
GIR_Done, |
| 21248 |
// Label 1203: @53253 |
21248 |
// Label 1203: @53253 |
| 21249 |
GIM_Try, /*On fail goto*//*Label 1204*/ 53354, // Rule ID 2243 // |
21249 |
GIM_Try, /*On fail goto*//*Label 1204*/ 53354, // Rule ID 2243 // |
| 21250 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
21250 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
| 21251 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21251 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21252 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21252 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21253 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21253 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21254 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
21254 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 21255 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21255 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21256 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
21256 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 21257 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
21257 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 21258 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
21258 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 21259 |
// MIs[1] Operand 1 |
21259 |
// MIs[1] Operand 1 |
| 21260 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
21260 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, |
| 21261 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
21261 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 21262 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
21262 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 21263 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21263 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21264 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
21264 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 21265 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21265 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21266 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
21266 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
| 21267 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
21267 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21268 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
21268 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
| 21269 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
21269 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21270 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
21270 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 21271 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
21271 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 21272 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
21272 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21273 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM, |
21273 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVZ_I_D32_MM, |
| 21274 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21274 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21275 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21275 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21276 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
21276 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21277 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21277 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21278 |
GIR_EraseFromParent, /*InsnID*/0, |
21278 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21279 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21279 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21280 |
// GIR_Coverage, 2243, |
21280 |
// GIR_Coverage, 2243, |
| 21281 |
GIR_Done, |
21281 |
GIR_Done, |
| 21282 |
// Label 1204: @53354 |
21282 |
// Label 1204: @53354 |
| 21283 |
GIM_Try, /*On fail goto*//*Label 1205*/ 53455, // Rule ID 2245 // |
21283 |
GIM_Try, /*On fail goto*//*Label 1205*/ 53455, // Rule ID 2245 // |
| 21284 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
21284 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
| 21285 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21285 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21286 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21286 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21287 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21287 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21288 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
21288 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 21289 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21289 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21290 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
21290 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, |
| 21291 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
21291 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 21292 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
21292 |
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 21293 |
// MIs[1] Operand 1 |
21293 |
// MIs[1] Operand 1 |
| 21294 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
21294 |
GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, |
| 21295 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
21295 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 21296 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
21296 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/Mips::GPR32RegClassID, |
| 21297 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21297 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21298 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
21298 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 21299 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21299 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21300 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
21300 |
// (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F) |
| 21301 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
21301 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 21302 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
21302 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::XOR_MM, |
| 21303 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
21303 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21304 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
21304 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs |
| 21305 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
21305 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs |
| 21306 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
21306 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21307 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM, |
21307 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM, |
| 21308 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21308 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21309 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21309 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21310 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
21310 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21311 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21311 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21312 |
GIR_EraseFromParent, /*InsnID*/0, |
21312 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21313 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21313 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21314 |
// GIR_Coverage, 2245, |
21314 |
// GIR_Coverage, 2245, |
| 21315 |
GIR_Done, |
21315 |
GIR_Done, |
| 21316 |
// Label 1205: @53455 |
21316 |
// Label 1205: @53455 |
| 21317 |
GIM_Try, /*On fail goto*//*Label 1206*/ 53494, // Rule ID 284 // |
21317 |
GIM_Try, /*On fail goto*//*Label 1206*/ 53494, // Rule ID 284 // |
| 21318 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32, |
21318 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32, |
| 21319 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21319 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21320 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21320 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21321 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21321 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21322 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
21322 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 21323 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
21323 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 21324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
21324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 21325 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
21325 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 21326 |
// (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) => (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) |
21326 |
// (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) => (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) |
| 21327 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I64, |
21327 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I64, |
| 21328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21329 |
// GIR_Coverage, 284, |
21329 |
// GIR_Coverage, 284, |
| 21330 |
GIR_Done, |
21330 |
GIR_Done, |
| 21331 |
// Label 1206: @53494 |
21331 |
// Label 1206: @53494 |
| 21332 |
GIM_Try, /*On fail goto*//*Label 1207*/ 53533, // Rule ID 286 // |
21332 |
GIM_Try, /*On fail goto*//*Label 1207*/ 53533, // Rule ID 286 // |
| 21333 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotMips4_32, |
21333 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotMips4_32, |
| 21334 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21334 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21335 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21335 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21336 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21336 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21337 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
21337 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 21338 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
21338 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 21339 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21339 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21340 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
21340 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 21341 |
// (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) |
21341 |
// (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) |
| 21342 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D32, |
21342 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D32, |
| 21343 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21343 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21344 |
// GIR_Coverage, 286, |
21344 |
// GIR_Coverage, 286, |
| 21345 |
GIR_Done, |
21345 |
GIR_Done, |
| 21346 |
// Label 1207: @53533 |
21346 |
// Label 1207: @53533 |
| 21347 |
GIM_Try, /*On fail goto*//*Label 1208*/ 53572, // Rule ID 287 // |
21347 |
GIM_Try, /*On fail goto*//*Label 1208*/ 53572, // Rule ID 287 // |
| 21348 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotMips4_32, |
21348 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotMips4_32, |
| 21349 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21349 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21350 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21350 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21351 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21351 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21352 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
21352 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 21353 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
21353 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 21354 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
21354 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 21355 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
21355 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 21356 |
// (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) |
21356 |
// (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) |
| 21357 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D64, |
21357 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D64, |
| 21358 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21358 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21359 |
// GIR_Coverage, 287, |
21359 |
// GIR_Coverage, 287, |
| 21360 |
GIR_Done, |
21360 |
GIR_Done, |
| 21361 |
// Label 1208: @53572 |
21361 |
// Label 1208: @53572 |
| 21362 |
GIM_Try, /*On fail goto*//*Label 1209*/ 53628, // Rule ID 1650 // |
21362 |
GIM_Try, /*On fail goto*//*Label 1209*/ 53628, // Rule ID 1650 // |
| 21363 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
21363 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21364 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21364 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21365 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21365 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21366 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21366 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21367 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
21367 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 21368 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
21368 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 21369 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
21369 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 21370 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
21370 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 21371 |
// (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F) |
21371 |
// (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F) |
| 21372 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64, |
21372 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64, |
| 21373 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
21373 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 21374 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21374 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21375 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
21375 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 21376 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21376 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21377 |
GIR_EraseFromParent, /*InsnID*/0, |
21377 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21378 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21378 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21379 |
// GIR_Coverage, 1650, |
21379 |
// GIR_Coverage, 1650, |
| 21380 |
GIR_Done, |
21380 |
GIR_Done, |
| 21381 |
// Label 1209: @53628 |
21381 |
// Label 1209: @53628 |
| 21382 |
GIM_Try, /*On fail goto*//*Label 1210*/ 53684, // Rule ID 1656 // |
21382 |
GIM_Try, /*On fail goto*//*Label 1210*/ 53684, // Rule ID 1656 // |
| 21383 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
21383 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21384 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
21384 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21385 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21385 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21386 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21386 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21387 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
21387 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 21388 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
21388 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 21389 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
21389 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 21390 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
21390 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID, |
| 21391 |
// (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F) |
21391 |
// (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F) |
| 21392 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64, |
21392 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64, |
| 21393 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
21393 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 21394 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21394 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21395 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
21395 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 21396 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21396 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21397 |
GIR_EraseFromParent, /*InsnID*/0, |
21397 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21398 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21398 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21399 |
// GIR_Coverage, 1656, |
21399 |
// GIR_Coverage, 1656, |
| 21400 |
GIR_Done, |
21400 |
GIR_Done, |
| 21401 |
// Label 1210: @53684 |
21401 |
// Label 1210: @53684 |
| 21402 |
GIM_Try, /*On fail goto*//*Label 1211*/ 53740, // Rule ID 1695 // |
21402 |
GIM_Try, /*On fail goto*//*Label 1211*/ 53740, // Rule ID 1695 // |
| 21403 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
21403 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21404 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21404 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21405 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21405 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21406 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21406 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21407 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
21407 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 21408 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
21408 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 21409 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21409 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21410 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
21410 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 21411 |
// (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F) |
21411 |
// (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F) |
| 21412 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32, |
21412 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32, |
| 21413 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21413 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21414 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21414 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21415 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
21415 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 21416 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21416 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21417 |
GIR_EraseFromParent, /*InsnID*/0, |
21417 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21418 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21418 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21419 |
// GIR_Coverage, 1695, |
21419 |
// GIR_Coverage, 1695, |
| 21420 |
GIR_Done, |
21420 |
GIR_Done, |
| 21421 |
// Label 1211: @53740 |
21421 |
// Label 1211: @53740 |
| 21422 |
GIM_Try, /*On fail goto*//*Label 1212*/ 53796, // Rule ID 1718 // |
21422 |
GIM_Try, /*On fail goto*//*Label 1212*/ 53796, // Rule ID 1718 // |
| 21423 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
21423 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21424 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21424 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21425 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21425 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21426 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21426 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21427 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
21427 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 21428 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
21428 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 21429 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
21429 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 21430 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
21430 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 21431 |
// (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F) |
21431 |
// (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F) |
| 21432 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64, |
21432 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64, |
| 21433 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21433 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21434 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21434 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21435 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
21435 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 21436 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21436 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21437 |
GIR_EraseFromParent, /*InsnID*/0, |
21437 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21438 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21438 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21439 |
// GIR_Coverage, 1718, |
21439 |
// GIR_Coverage, 1718, |
| 21440 |
GIR_Done, |
21440 |
GIR_Done, |
| 21441 |
// Label 1212: @53796 |
21441 |
// Label 1212: @53796 |
| 21442 |
GIM_Try, /*On fail goto*//*Label 1213*/ 53852, // Rule ID 1721 // |
21442 |
GIM_Try, /*On fail goto*//*Label 1213*/ 53852, // Rule ID 1721 // |
| 21443 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
21443 |
GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21444 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
21444 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21445 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21445 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21446 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21446 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21447 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
21447 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 21448 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
21448 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 21449 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
21449 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 21450 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
21450 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID, |
| 21451 |
// (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F) |
21451 |
// (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F) |
| 21452 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64, |
21452 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64, |
| 21453 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21453 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21454 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21454 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21455 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
21455 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 21456 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21456 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21457 |
GIR_EraseFromParent, /*InsnID*/0, |
21457 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21458 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21458 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21459 |
// GIR_Coverage, 1721, |
21459 |
// GIR_Coverage, 1721, |
| 21460 |
GIR_Done, |
21460 |
GIR_Done, |
| 21461 |
// Label 1213: @53852 |
21461 |
// Label 1213: @53852 |
| 21462 |
GIM_Try, /*On fail goto*//*Label 1214*/ 53908, // Rule ID 2246 // |
21462 |
GIM_Try, /*On fail goto*//*Label 1214*/ 53908, // Rule ID 2246 // |
| 21463 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
21463 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6, |
| 21464 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21464 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21465 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21465 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21466 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21466 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21467 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
21467 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 21468 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
21468 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 21469 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21469 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21470 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
21470 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID, |
| 21471 |
// (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F) |
21471 |
// (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F) |
| 21472 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM, |
21472 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM, |
| 21473 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21473 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21474 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
21474 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T |
| 21475 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
21475 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 21476 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
21476 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F |
| 21477 |
GIR_EraseFromParent, /*InsnID*/0, |
21477 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21478 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21478 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21479 |
// GIR_Coverage, 2246, |
21479 |
// GIR_Coverage, 2246, |
| 21480 |
GIR_Done, |
21480 |
GIR_Done, |
| 21481 |
// Label 1214: @53908 |
21481 |
// Label 1214: @53908 |
| 21482 |
GIM_Try, /*On fail goto*//*Label 1215*/ 53988, // Rule ID 1754 // |
21482 |
GIM_Try, /*On fail goto*//*Label 1215*/ 53988, // Rule ID 1754 // |
| 21483 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
21483 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
| 21484 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
21484 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21485 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21485 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21486 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21486 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21487 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
21487 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 21488 |
// (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond)) |
21488 |
// (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond)) |
| 21489 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
21489 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21490 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
21490 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 21491 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ64, |
21491 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ64, |
| 21492 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
21492 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 21493 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f |
21493 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f |
| 21494 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond |
21494 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 21495 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
21495 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21496 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64, |
21496 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64, |
| 21497 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
21497 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21498 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t |
21498 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t |
| 21499 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond |
21499 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 21500 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
21500 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21501 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64, |
21501 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64, |
| 21502 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
21502 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 21503 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
21503 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21504 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
21504 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, |
| 21505 |
GIR_EraseFromParent, /*InsnID*/0, |
21505 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21506 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21506 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21507 |
// GIR_Coverage, 1754, |
21507 |
// GIR_Coverage, 1754, |
| 21508 |
GIR_Done, |
21508 |
GIR_Done, |
| 21509 |
// Label 1215: @53988 |
21509 |
// Label 1215: @53988 |
| 21510 |
GIM_Try, /*On fail goto*//*Label 1216*/ 54100, // Rule ID 1765 // |
21510 |
GIM_Try, /*On fail goto*//*Label 1216*/ 54100, // Rule ID 1765 // |
| 21511 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
21511 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc, |
| 21512 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21512 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21513 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21513 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21514 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
21514 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, |
| 21515 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
21515 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 21516 |
// (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond))) |
21516 |
// (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond))) |
| 21517 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
21517 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 21518 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
21518 |
GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 21519 |
GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
21519 |
GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 21520 |
GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, |
21520 |
GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, |
| 21521 |
GIR_BuildMI, /*InsnID*/4, /*Opcode*/Mips::SLL64_32, |
21521 |
GIR_BuildMI, /*InsnID*/4, /*Opcode*/Mips::SLL64_32, |
| 21522 |
GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
21522 |
GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define, |
| 21523 |
GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond |
21523 |
GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 21524 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
21524 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 21525 |
GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SELEQZ64, |
21525 |
GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SELEQZ64, |
| 21526 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
21526 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, |
| 21527 |
GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f |
21527 |
GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f |
| 21528 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
21528 |
GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0, |
| 21529 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
21529 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 21530 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL64_32, |
21530 |
GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL64_32, |
| 21531 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
21531 |
GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, |
| 21532 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond |
21532 |
GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond |
| 21533 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
21533 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 21534 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64, |
21534 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64, |
| 21535 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
21535 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 21536 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t |
21536 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t |
| 21537 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
21537 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, |
| 21538 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
21538 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 21539 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64, |
21539 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64, |
| 21540 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
21540 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 21541 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
21541 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 21542 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, |
21542 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0, |
| 21543 |
GIR_EraseFromParent, /*InsnID*/0, |
21543 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21544 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21544 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21545 |
// GIR_Coverage, 1765, |
21545 |
// GIR_Coverage, 1765, |
| 21546 |
GIR_Done, |
21546 |
GIR_Done, |
| 21547 |
// Label 1216: @54100 |
21547 |
// Label 1216: @54100 |
| 21548 |
GIM_Reject, |
21548 |
GIM_Reject, |
| 21549 |
// Label 1077: @54101 |
21549 |
// Label 1077: @54101 |
| 21550 |
GIM_Reject, |
21550 |
GIM_Reject, |
| 21551 |
// Label 30: @54102 |
21551 |
// Label 30: @54102 |
| 21552 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1219*/ 54188, |
21552 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1219*/ 54188, |
| 21553 |
/*GILLT_s32*//*Label 1217*/ 54110, |
21553 |
/*GILLT_s32*//*Label 1217*/ 54110, |
| 21554 |
/*GILLT_s64*//*Label 1218*/ 54156, |
21554 |
/*GILLT_s64*//*Label 1218*/ 54156, |
| 21555 |
// Label 1217: @54110 |
21555 |
// Label 1217: @54110 |
| 21556 |
GIM_Try, /*On fail goto*//*Label 1220*/ 54155, |
21556 |
GIM_Try, /*On fail goto*//*Label 1220*/ 54155, |
| 21557 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21557 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21558 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
21558 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 21559 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
21559 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 21560 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
21560 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 21561 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
21561 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 21562 |
GIM_Try, /*On fail goto*//*Label 1221*/ 54143, // Rule ID 319 // |
21562 |
GIM_Try, /*On fail goto*//*Label 1221*/ 54143, // Rule ID 319 // |
| 21563 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
21563 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 21564 |
// (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
21564 |
// (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 21565 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUHU, |
21565 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUHU, |
| 21566 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21566 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21567 |
// GIR_Coverage, 319, |
21567 |
// GIR_Coverage, 319, |
| 21568 |
GIR_Done, |
21568 |
GIR_Done, |
| 21569 |
// Label 1221: @54143 |
21569 |
// Label 1221: @54143 |
| 21570 |
GIM_Try, /*On fail goto*//*Label 1222*/ 54154, // Rule ID 1169 // |
21570 |
GIM_Try, /*On fail goto*//*Label 1222*/ 54154, // Rule ID 1169 // |
| 21571 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
21571 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 21572 |
// (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
21572 |
// (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 21573 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUHU_MMR6, |
21573 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUHU_MMR6, |
| 21574 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21574 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21575 |
// GIR_Coverage, 1169, |
21575 |
// GIR_Coverage, 1169, |
| 21576 |
GIR_Done, |
21576 |
GIR_Done, |
| 21577 |
// Label 1222: @54154 |
21577 |
// Label 1222: @54154 |
| 21578 |
GIM_Reject, |
21578 |
GIM_Reject, |
| 21579 |
// Label 1220: @54155 |
21579 |
// Label 1220: @54155 |
| 21580 |
GIM_Reject, |
21580 |
GIM_Reject, |
| 21581 |
// Label 1218: @54156 |
21581 |
// Label 1218: @54156 |
| 21582 |
GIM_Try, /*On fail goto*//*Label 1223*/ 54187, // Rule ID 334 // |
21582 |
GIM_Try, /*On fail goto*//*Label 1223*/ 54187, // Rule ID 334 // |
| 21583 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
21583 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
| 21584 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
21584 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21585 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21585 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21586 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
21586 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 21587 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
21587 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 21588 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
21588 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 21589 |
// (mulhu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUHU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
21589 |
// (mulhu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUHU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 21590 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUHU, |
21590 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUHU, |
| 21591 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21591 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21592 |
// GIR_Coverage, 334, |
21592 |
// GIR_Coverage, 334, |
| 21593 |
GIR_Done, |
21593 |
GIR_Done, |
| 21594 |
// Label 1223: @54187 |
21594 |
// Label 1223: @54187 |
| 21595 |
GIM_Reject, |
21595 |
GIM_Reject, |
| 21596 |
// Label 1219: @54188 |
21596 |
// Label 1219: @54188 |
| 21597 |
GIM_Reject, |
21597 |
GIM_Reject, |
| 21598 |
// Label 31: @54189 |
21598 |
// Label 31: @54189 |
| 21599 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1226*/ 54275, |
21599 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1226*/ 54275, |
| 21600 |
/*GILLT_s32*//*Label 1224*/ 54197, |
21600 |
/*GILLT_s32*//*Label 1224*/ 54197, |
| 21601 |
/*GILLT_s64*//*Label 1225*/ 54243, |
21601 |
/*GILLT_s64*//*Label 1225*/ 54243, |
| 21602 |
// Label 1224: @54197 |
21602 |
// Label 1224: @54197 |
| 21603 |
GIM_Try, /*On fail goto*//*Label 1227*/ 54242, |
21603 |
GIM_Try, /*On fail goto*//*Label 1227*/ 54242, |
| 21604 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21604 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21605 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
21605 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 21606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
21606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 21607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
21607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 21608 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
21608 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID, |
| 21609 |
GIM_Try, /*On fail goto*//*Label 1228*/ 54230, // Rule ID 318 // |
21609 |
GIM_Try, /*On fail goto*//*Label 1228*/ 54230, // Rule ID 318 // |
| 21610 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
21610 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips, |
| 21611 |
// (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
21611 |
// (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 21612 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUH, |
21612 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUH, |
| 21613 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21613 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21614 |
// GIR_Coverage, 318, |
21614 |
// GIR_Coverage, 318, |
| 21615 |
GIR_Done, |
21615 |
GIR_Done, |
| 21616 |
// Label 1228: @54230 |
21616 |
// Label 1228: @54230 |
| 21617 |
GIM_Try, /*On fail goto*//*Label 1229*/ 54241, // Rule ID 1168 // |
21617 |
GIM_Try, /*On fail goto*//*Label 1229*/ 54241, // Rule ID 1168 // |
| 21618 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
21618 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 21619 |
// (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
21619 |
// (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUH_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) |
| 21620 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUH_MMR6, |
21620 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUH_MMR6, |
| 21621 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21621 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21622 |
// GIR_Coverage, 1168, |
21622 |
// GIR_Coverage, 1168, |
| 21623 |
GIR_Done, |
21623 |
GIR_Done, |
| 21624 |
// Label 1229: @54241 |
21624 |
// Label 1229: @54241 |
| 21625 |
GIM_Reject, |
21625 |
GIM_Reject, |
| 21626 |
// Label 1227: @54242 |
21626 |
// Label 1227: @54242 |
| 21627 |
GIM_Reject, |
21627 |
GIM_Reject, |
| 21628 |
// Label 1225: @54243 |
21628 |
// Label 1225: @54243 |
| 21629 |
GIM_Try, /*On fail goto*//*Label 1230*/ 54274, // Rule ID 333 // |
21629 |
GIM_Try, /*On fail goto*//*Label 1230*/ 54274, // Rule ID 333 // |
| 21630 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
21630 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
| 21631 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
21631 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21632 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21632 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21633 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
21633 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 21634 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
21634 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 21635 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
21635 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID, |
| 21636 |
// (mulhs:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUH:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
21636 |
// (mulhs:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUH:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) |
| 21637 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUH, |
21637 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUH, |
| 21638 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21638 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21639 |
// GIR_Coverage, 333, |
21639 |
// GIR_Coverage, 333, |
| 21640 |
GIR_Done, |
21640 |
GIR_Done, |
| 21641 |
// Label 1230: @54274 |
21641 |
// Label 1230: @54274 |
| 21642 |
GIM_Reject, |
21642 |
GIM_Reject, |
| 21643 |
// Label 1226: @54275 |
21643 |
// Label 1226: @54275 |
| 21644 |
GIM_Reject, |
21644 |
GIM_Reject, |
| 21645 |
// Label 32: @54276 |
21645 |
// Label 32: @54276 |
| 21646 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1235*/ 55154, |
21646 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1235*/ 55154, |
| 21647 |
/*GILLT_s32*//*Label 1231*/ 54288, |
21647 |
/*GILLT_s32*//*Label 1231*/ 54288, |
| 21648 |
/*GILLT_s64*//*Label 1232*/ 54488, 0, |
21648 |
/*GILLT_s64*//*Label 1232*/ 54488, 0, |
| 21649 |
/*GILLT_v2s64*//*Label 1233*/ 54836, 0, |
21649 |
/*GILLT_v2s64*//*Label 1233*/ 54836, 0, |
| 21650 |
/*GILLT_v4s32*//*Label 1234*/ 54995, |
21650 |
/*GILLT_v4s32*//*Label 1234*/ 54995, |
| 21651 |
// Label 1231: @54288 |
21651 |
// Label 1231: @54288 |
| 21652 |
GIM_Try, /*On fail goto*//*Label 1236*/ 54487, |
21652 |
GIM_Try, /*On fail goto*//*Label 1236*/ 54487, |
| 21653 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
21653 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 21654 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
21654 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 21655 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
21655 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 21656 |
GIM_Try, /*On fail goto*//*Label 1237*/ 54359, // Rule ID 157 // |
21656 |
GIM_Try, /*On fail goto*//*Label 1237*/ 54359, // Rule ID 157 // |
| 21657 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
21657 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21658 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21658 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21659 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
21659 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 21660 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
21660 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 21661 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
21661 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 21662 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
21662 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 21663 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
21663 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 21664 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
21664 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 21665 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21665 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21666 |
// (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
21666 |
// (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 21667 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S, |
21667 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S, |
| 21668 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21668 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21669 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr |
21669 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr |
| 21670 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
21670 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
| 21671 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
21671 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
| 21672 |
GIR_EraseFromParent, /*InsnID*/0, |
21672 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21673 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21673 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21674 |
// GIR_Coverage, 157, |
21674 |
// GIR_Coverage, 157, |
| 21675 |
GIR_Done, |
21675 |
GIR_Done, |
| 21676 |
// Label 1237: @54359 |
21676 |
// Label 1237: @54359 |
| 21677 |
GIM_Try, /*On fail goto*//*Label 1238*/ 54416, // Rule ID 2307 // |
21677 |
GIM_Try, /*On fail goto*//*Label 1238*/ 54416, // Rule ID 2307 // |
| 21678 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
21678 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21679 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
21679 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 21680 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
21680 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 21681 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
21681 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 21682 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
21682 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 21683 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
21683 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 21684 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
21684 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 21685 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
21685 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 21686 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21686 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21687 |
// (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
21687 |
// (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 21688 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S, |
21688 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S, |
| 21689 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21689 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21690 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr |
21690 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr |
| 21691 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
21691 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
| 21692 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
21692 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
| 21693 |
GIR_EraseFromParent, /*InsnID*/0, |
21693 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21694 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21694 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21695 |
// GIR_Coverage, 2307, |
21695 |
// GIR_Coverage, 2307, |
| 21696 |
GIR_Done, |
21696 |
GIR_Done, |
| 21697 |
// Label 1238: @54416 |
21697 |
// Label 1238: @54416 |
| 21698 |
GIM_Try, /*On fail goto*//*Label 1239*/ 54435, // Rule ID 145 // |
21698 |
GIM_Try, /*On fail goto*//*Label 1239*/ 54435, // Rule ID 145 // |
| 21699 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
21699 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 21700 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
21700 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 21701 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
21701 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 21702 |
// (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
21702 |
// (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 21703 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S, |
21703 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S, |
| 21704 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21704 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21705 |
// GIR_Coverage, 145, |
21705 |
// GIR_Coverage, 145, |
| 21706 |
GIR_Done, |
21706 |
GIR_Done, |
| 21707 |
// Label 1239: @54435 |
21707 |
// Label 1239: @54435 |
| 21708 |
GIM_Try, /*On fail goto*//*Label 1240*/ 54454, // Rule ID 1118 // |
21708 |
GIM_Try, /*On fail goto*//*Label 1240*/ 54454, // Rule ID 1118 // |
| 21709 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
21709 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
| 21710 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
21710 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 21711 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
21711 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 21712 |
// (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
21712 |
// (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 21713 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S_MM, |
21713 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S_MM, |
| 21714 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21714 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21715 |
// GIR_Coverage, 1118, |
21715 |
// GIR_Coverage, 1118, |
| 21716 |
GIR_Done, |
21716 |
GIR_Done, |
| 21717 |
// Label 1240: @54454 |
21717 |
// Label 1240: @54454 |
| 21718 |
GIM_Try, /*On fail goto*//*Label 1241*/ 54486, // Rule ID 1176 // |
21718 |
GIM_Try, /*On fail goto*//*Label 1241*/ 54486, // Rule ID 1176 // |
| 21719 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
21719 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 21720 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
21720 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 21721 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
21721 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 21722 |
// (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) |
21722 |
// (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) |
| 21723 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FADD_S_MMR6, |
21723 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FADD_S_MMR6, |
| 21724 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21724 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21725 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft |
21725 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft |
| 21726 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs |
21726 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs |
| 21727 |
GIR_EraseFromParent, /*InsnID*/0, |
21727 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21728 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21728 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21729 |
// GIR_Coverage, 1176, |
21729 |
// GIR_Coverage, 1176, |
| 21730 |
GIR_Done, |
21730 |
GIR_Done, |
| 21731 |
// Label 1241: @54486 |
21731 |
// Label 1241: @54486 |
| 21732 |
GIM_Reject, |
21732 |
GIM_Reject, |
| 21733 |
// Label 1236: @54487 |
21733 |
// Label 1236: @54487 |
| 21734 |
GIM_Reject, |
21734 |
GIM_Reject, |
| 21735 |
// Label 1232: @54488 |
21735 |
// Label 1232: @54488 |
| 21736 |
GIM_Try, /*On fail goto*//*Label 1242*/ 54835, |
21736 |
GIM_Try, /*On fail goto*//*Label 1242*/ 54835, |
| 21737 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
21737 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 21738 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
21738 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 21739 |
GIM_Try, /*On fail goto*//*Label 1243*/ 54559, // Rule ID 159 // |
21739 |
GIM_Try, /*On fail goto*//*Label 1243*/ 54559, // Rule ID 159 // |
| 21740 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
21740 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21741 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
21741 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 21742 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21742 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21743 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
21743 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 21744 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
21744 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 21745 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
21745 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 21746 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
21746 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 21747 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21747 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21748 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21748 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21749 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21749 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21750 |
// (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
21750 |
// (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 21751 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32, |
21751 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32, |
| 21752 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21752 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21753 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr |
21753 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr |
| 21754 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
21754 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
| 21755 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
21755 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
| 21756 |
GIR_EraseFromParent, /*InsnID*/0, |
21756 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21757 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21757 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21758 |
// GIR_Coverage, 159, |
21758 |
// GIR_Coverage, 159, |
| 21759 |
GIR_Done, |
21759 |
GIR_Done, |
| 21760 |
// Label 1243: @54559 |
21760 |
// Label 1243: @54559 |
| 21761 |
GIM_Try, /*On fail goto*//*Label 1244*/ 54620, // Rule ID 161 // |
21761 |
GIM_Try, /*On fail goto*//*Label 1244*/ 54620, // Rule ID 161 // |
| 21762 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
21762 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21763 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
21763 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 21764 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21764 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21765 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
21765 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 21766 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
21766 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 21767 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
21767 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 21768 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
21768 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 21769 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
21769 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 21770 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
21770 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 21771 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21771 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21772 |
// (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
21772 |
// (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 21773 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64, |
21773 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64, |
| 21774 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21774 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21775 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr |
21775 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr |
| 21776 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
21776 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
| 21777 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
21777 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
| 21778 |
GIR_EraseFromParent, /*InsnID*/0, |
21778 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21779 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21779 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21780 |
// GIR_Coverage, 161, |
21780 |
// GIR_Coverage, 161, |
| 21781 |
GIR_Done, |
21781 |
GIR_Done, |
| 21782 |
// Label 1244: @54620 |
21782 |
// Label 1244: @54620 |
| 21783 |
GIM_Try, /*On fail goto*//*Label 1245*/ 54681, // Rule ID 2308 // |
21783 |
GIM_Try, /*On fail goto*//*Label 1245*/ 54681, // Rule ID 2308 // |
| 21784 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
21784 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21785 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
21785 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 21786 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
21786 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 21787 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
21787 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 21788 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
21788 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 21789 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
21789 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 21790 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
21790 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 21791 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
21791 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 21792 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21792 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21793 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21793 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21794 |
// (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
21794 |
// (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 21795 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32, |
21795 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32, |
| 21796 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21796 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21797 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr |
21797 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr |
| 21798 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
21798 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
| 21799 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
21799 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
| 21800 |
GIR_EraseFromParent, /*InsnID*/0, |
21800 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21801 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21801 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21802 |
// GIR_Coverage, 2308, |
21802 |
// GIR_Coverage, 2308, |
| 21803 |
GIR_Done, |
21803 |
GIR_Done, |
| 21804 |
// Label 1245: @54681 |
21804 |
// Label 1245: @54681 |
| 21805 |
GIM_Try, /*On fail goto*//*Label 1246*/ 54742, // Rule ID 2309 // |
21805 |
GIM_Try, /*On fail goto*//*Label 1246*/ 54742, // Rule ID 2309 // |
| 21806 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
21806 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 21807 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
21807 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 21808 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
21808 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 21809 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
21809 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 21810 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
21810 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 21811 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
21811 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 21812 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
21812 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 21813 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
21813 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 21814 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
21814 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 21815 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21815 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21816 |
// (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
21816 |
// (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 21817 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64, |
21817 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64, |
| 21818 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
21818 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 21819 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr |
21819 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr |
| 21820 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
21820 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
| 21821 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
21821 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
| 21822 |
GIR_EraseFromParent, /*InsnID*/0, |
21822 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21823 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21823 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21824 |
// GIR_Coverage, 2309, |
21824 |
// GIR_Coverage, 2309, |
| 21825 |
GIR_Done, |
21825 |
GIR_Done, |
| 21826 |
// Label 1246: @54742 |
21826 |
// Label 1246: @54742 |
| 21827 |
GIM_Try, /*On fail goto*//*Label 1247*/ 54765, // Rule ID 146 // |
21827 |
GIM_Try, /*On fail goto*//*Label 1247*/ 54765, // Rule ID 146 // |
| 21828 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
21828 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
| 21829 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
21829 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 21830 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
21830 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 21831 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21831 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21832 |
// (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
21832 |
// (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 21833 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32, |
21833 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32, |
| 21834 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21834 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21835 |
// GIR_Coverage, 146, |
21835 |
// GIR_Coverage, 146, |
| 21836 |
GIR_Done, |
21836 |
GIR_Done, |
| 21837 |
// Label 1247: @54765 |
21837 |
// Label 1247: @54765 |
| 21838 |
GIM_Try, /*On fail goto*//*Label 1248*/ 54788, // Rule ID 147 // |
21838 |
GIM_Try, /*On fail goto*//*Label 1248*/ 54788, // Rule ID 147 // |
| 21839 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
21839 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
| 21840 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
21840 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 21841 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
21841 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 21842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
21842 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 21843 |
// (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
21843 |
// (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 21844 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64, |
21844 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64, |
| 21845 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21845 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21846 |
// GIR_Coverage, 147, |
21846 |
// GIR_Coverage, 147, |
| 21847 |
GIR_Done, |
21847 |
GIR_Done, |
| 21848 |
// Label 1248: @54788 |
21848 |
// Label 1248: @54788 |
| 21849 |
GIM_Try, /*On fail goto*//*Label 1249*/ 54811, // Rule ID 1122 // |
21849 |
GIM_Try, /*On fail goto*//*Label 1249*/ 54811, // Rule ID 1122 // |
| 21850 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
21850 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
| 21851 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
21851 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 21852 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
21852 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 21853 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
21853 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 21854 |
// (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
21854 |
// (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 21855 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32_MM, |
21855 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32_MM, |
| 21856 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21856 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21857 |
// GIR_Coverage, 1122, |
21857 |
// GIR_Coverage, 1122, |
| 21858 |
GIR_Done, |
21858 |
GIR_Done, |
| 21859 |
// Label 1249: @54811 |
21859 |
// Label 1249: @54811 |
| 21860 |
GIM_Try, /*On fail goto*//*Label 1250*/ 54834, // Rule ID 1123 // |
21860 |
GIM_Try, /*On fail goto*//*Label 1250*/ 54834, // Rule ID 1123 // |
| 21861 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
21861 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
| 21862 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
21862 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 21863 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
21863 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 21864 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
21864 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 21865 |
// (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
21865 |
// (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 21866 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64_MM, |
21866 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64_MM, |
| 21867 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21867 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21868 |
// GIR_Coverage, 1123, |
21868 |
// GIR_Coverage, 1123, |
| 21869 |
GIR_Done, |
21869 |
GIR_Done, |
| 21870 |
// Label 1250: @54834 |
21870 |
// Label 1250: @54834 |
| 21871 |
GIM_Reject, |
21871 |
GIM_Reject, |
| 21872 |
// Label 1242: @54835 |
21872 |
// Label 1242: @54835 |
| 21873 |
GIM_Reject, |
21873 |
GIM_Reject, |
| 21874 |
// Label 1233: @54836 |
21874 |
// Label 1233: @54836 |
| 21875 |
GIM_Try, /*On fail goto*//*Label 1251*/ 54994, |
21875 |
GIM_Try, /*On fail goto*//*Label 1251*/ 54994, |
| 21876 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
21876 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21877 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
21877 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21878 |
GIM_Try, /*On fail goto*//*Label 1252*/ 54908, // Rule ID 2411 // |
21878 |
GIM_Try, /*On fail goto*//*Label 1252*/ 54908, // Rule ID 2411 // |
| 21879 |
GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
21879 |
GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
| 21880 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, |
21880 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, |
| 21881 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21881 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21882 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
21882 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 21883 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
21883 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21884 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
21884 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21885 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
21885 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 21886 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
21886 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 21887 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
21887 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 21888 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21888 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21889 |
// (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$wd) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
21889 |
// (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$wd) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 21890 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D, |
21890 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D, |
| 21891 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd |
21891 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd |
| 21892 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd |
21892 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd |
| 21893 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
21893 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 21894 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
21894 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 21895 |
GIR_EraseFromParent, /*InsnID*/0, |
21895 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21896 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21896 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21897 |
// GIR_Coverage, 2411, |
21897 |
// GIR_Coverage, 2411, |
| 21898 |
GIR_Done, |
21898 |
GIR_Done, |
| 21899 |
// Label 1252: @54908 |
21899 |
// Label 1252: @54908 |
| 21900 |
GIM_Try, /*On fail goto*//*Label 1253*/ 54970, // Rule ID 1949 // |
21900 |
GIM_Try, /*On fail goto*//*Label 1253*/ 54970, // Rule ID 1949 // |
| 21901 |
GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
21901 |
GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
| 21902 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, |
21902 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 21903 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
21903 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 21904 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
21904 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 21905 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
21905 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 21906 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
21906 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 21907 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
21907 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21908 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
21908 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 21909 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
21909 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 21910 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21910 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21911 |
// (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
21911 |
// (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 21912 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D, |
21912 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D, |
| 21913 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
21913 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
| 21914 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
21914 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
| 21915 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
21915 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 21916 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
21916 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 21917 |
GIR_EraseFromParent, /*InsnID*/0, |
21917 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21918 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21918 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21919 |
// GIR_Coverage, 1949, |
21919 |
// GIR_Coverage, 1949, |
| 21920 |
GIR_Done, |
21920 |
GIR_Done, |
| 21921 |
// Label 1253: @54970 |
21921 |
// Label 1253: @54970 |
| 21922 |
GIM_Try, /*On fail goto*//*Label 1254*/ 54993, // Rule ID 659 // |
21922 |
GIM_Try, /*On fail goto*//*Label 1254*/ 54993, // Rule ID 659 // |
| 21923 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
21923 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 21924 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
21924 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 21925 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
21925 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 21926 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
21926 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 21927 |
// (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
21927 |
// (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 21928 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D, |
21928 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D, |
| 21929 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21929 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21930 |
// GIR_Coverage, 659, |
21930 |
// GIR_Coverage, 659, |
| 21931 |
GIR_Done, |
21931 |
GIR_Done, |
| 21932 |
// Label 1254: @54993 |
21932 |
// Label 1254: @54993 |
| 21933 |
GIM_Reject, |
21933 |
GIM_Reject, |
| 21934 |
// Label 1251: @54994 |
21934 |
// Label 1251: @54994 |
| 21935 |
GIM_Reject, |
21935 |
GIM_Reject, |
| 21936 |
// Label 1234: @54995 |
21936 |
// Label 1234: @54995 |
| 21937 |
GIM_Try, /*On fail goto*//*Label 1255*/ 55153, |
21937 |
GIM_Try, /*On fail goto*//*Label 1255*/ 55153, |
| 21938 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
21938 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21939 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
21939 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21940 |
GIM_Try, /*On fail goto*//*Label 1256*/ 55067, // Rule ID 2410 // |
21940 |
GIM_Try, /*On fail goto*//*Label 1256*/ 55067, // Rule ID 2410 // |
| 21941 |
GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
21941 |
GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
| 21942 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, |
21942 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2, |
| 21943 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
21943 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 21944 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
21944 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 21945 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
21945 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21946 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
21946 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21947 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
21947 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 21948 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
21948 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 21949 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
21949 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 21950 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21950 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21951 |
// (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$wd) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
21951 |
// (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$wd) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 21952 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W, |
21952 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W, |
| 21953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd |
21953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd |
| 21954 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd |
21954 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd |
| 21955 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
21955 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 21956 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
21956 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 21957 |
GIR_EraseFromParent, /*InsnID*/0, |
21957 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21958 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21958 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21959 |
// GIR_Coverage, 2410, |
21959 |
// GIR_Coverage, 2410, |
| 21960 |
GIR_Done, |
21960 |
GIR_Done, |
| 21961 |
// Label 1256: @55067 |
21961 |
// Label 1256: @55067 |
| 21962 |
GIM_Try, /*On fail goto*//*Label 1257*/ 55129, // Rule ID 1948 // |
21962 |
GIM_Try, /*On fail goto*//*Label 1257*/ 55129, // Rule ID 1948 // |
| 21963 |
GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
21963 |
GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
| 21964 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, |
21964 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 21965 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
21965 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 21966 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
21966 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 21967 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
21967 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 21968 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
21968 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 21969 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
21969 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21970 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
21970 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 21971 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
21971 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 21972 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
21972 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 21973 |
// (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
21973 |
// (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 21974 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W, |
21974 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W, |
| 21975 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
21975 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
| 21976 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
21976 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
| 21977 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
21977 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 21978 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
21978 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 21979 |
GIR_EraseFromParent, /*InsnID*/0, |
21979 |
GIR_EraseFromParent, /*InsnID*/0, |
| 21980 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21980 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21981 |
// GIR_Coverage, 1948, |
21981 |
// GIR_Coverage, 1948, |
| 21982 |
GIR_Done, |
21982 |
GIR_Done, |
| 21983 |
// Label 1257: @55129 |
21983 |
// Label 1257: @55129 |
| 21984 |
GIM_Try, /*On fail goto*//*Label 1258*/ 55152, // Rule ID 658 // |
21984 |
GIM_Try, /*On fail goto*//*Label 1258*/ 55152, // Rule ID 658 // |
| 21985 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
21985 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 21986 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
21986 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 21987 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
21987 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 21988 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
21988 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 21989 |
// (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
21989 |
// (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 21990 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_W, |
21990 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_W, |
| 21991 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
21991 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 21992 |
// GIR_Coverage, 658, |
21992 |
// GIR_Coverage, 658, |
| 21993 |
GIR_Done, |
21993 |
GIR_Done, |
| 21994 |
// Label 1258: @55152 |
21994 |
// Label 1258: @55152 |
| 21995 |
GIM_Reject, |
21995 |
GIM_Reject, |
| 21996 |
// Label 1255: @55153 |
21996 |
// Label 1255: @55153 |
| 21997 |
GIM_Reject, |
21997 |
GIM_Reject, |
| 21998 |
// Label 1235: @55154 |
21998 |
// Label 1235: @55154 |
| 21999 |
GIM_Reject, |
21999 |
GIM_Reject, |
| 22000 |
// Label 33: @55155 |
22000 |
// Label 33: @55155 |
| 22001 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1263*/ 55730, |
22001 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1263*/ 55730, |
| 22002 |
/*GILLT_s32*//*Label 1259*/ 55167, |
22002 |
/*GILLT_s32*//*Label 1259*/ 55167, |
| 22003 |
/*GILLT_s64*//*Label 1260*/ 55310, 0, |
22003 |
/*GILLT_s64*//*Label 1260*/ 55310, 0, |
| 22004 |
/*GILLT_v2s64*//*Label 1261*/ 55536, 0, |
22004 |
/*GILLT_v2s64*//*Label 1261*/ 55536, 0, |
| 22005 |
/*GILLT_v4s32*//*Label 1262*/ 55633, |
22005 |
/*GILLT_v4s32*//*Label 1262*/ 55633, |
| 22006 |
// Label 1259: @55167 |
22006 |
// Label 1259: @55167 |
| 22007 |
GIM_Try, /*On fail goto*//*Label 1264*/ 55309, |
22007 |
GIM_Try, /*On fail goto*//*Label 1264*/ 55309, |
| 22008 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
22008 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 22009 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
22009 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 22010 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
22010 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 22011 |
GIM_Try, /*On fail goto*//*Label 1265*/ 55238, // Rule ID 158 // |
22011 |
GIM_Try, /*On fail goto*//*Label 1265*/ 55238, // Rule ID 158 // |
| 22012 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
22012 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 22013 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22013 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22014 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
22014 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 22015 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
22015 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22016 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
22016 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 22017 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22017 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22018 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22018 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22019 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22019 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22020 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22020 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22021 |
// (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
22021 |
// (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 22022 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_S, |
22022 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_S, |
| 22023 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22023 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22024 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr |
22024 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr |
| 22025 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
22025 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
| 22026 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
22026 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
| 22027 |
GIR_EraseFromParent, /*InsnID*/0, |
22027 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22028 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22028 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22029 |
// GIR_Coverage, 158, |
22029 |
// GIR_Coverage, 158, |
| 22030 |
GIR_Done, |
22030 |
GIR_Done, |
| 22031 |
// Label 1265: @55238 |
22031 |
// Label 1265: @55238 |
| 22032 |
GIM_Try, /*On fail goto*//*Label 1266*/ 55257, // Rule ID 154 // |
22032 |
GIM_Try, /*On fail goto*//*Label 1266*/ 55257, // Rule ID 154 // |
| 22033 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
22033 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 22034 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22034 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22035 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22035 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22036 |
// (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
22036 |
// (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 22037 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S, |
22037 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S, |
| 22038 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22038 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22039 |
// GIR_Coverage, 154, |
22039 |
// GIR_Coverage, 154, |
| 22040 |
GIR_Done, |
22040 |
GIR_Done, |
| 22041 |
// Label 1266: @55257 |
22041 |
// Label 1266: @55257 |
| 22042 |
GIM_Try, /*On fail goto*//*Label 1267*/ 55276, // Rule ID 1121 // |
22042 |
GIM_Try, /*On fail goto*//*Label 1267*/ 55276, // Rule ID 1121 // |
| 22043 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
22043 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
| 22044 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22044 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22045 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22045 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22046 |
// (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
22046 |
// (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 22047 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S_MM, |
22047 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S_MM, |
| 22048 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22048 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22049 |
// GIR_Coverage, 1121, |
22049 |
// GIR_Coverage, 1121, |
| 22050 |
GIR_Done, |
22050 |
GIR_Done, |
| 22051 |
// Label 1267: @55276 |
22051 |
// Label 1267: @55276 |
| 22052 |
GIM_Try, /*On fail goto*//*Label 1268*/ 55308, // Rule ID 1177 // |
22052 |
GIM_Try, /*On fail goto*//*Label 1268*/ 55308, // Rule ID 1177 // |
| 22053 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
22053 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 22054 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22054 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22055 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22055 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22056 |
// (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) |
22056 |
// (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) |
| 22057 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUB_S_MMR6, |
22057 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUB_S_MMR6, |
| 22058 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22058 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22059 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft |
22059 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft |
| 22060 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs |
22060 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs |
| 22061 |
GIR_EraseFromParent, /*InsnID*/0, |
22061 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22062 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22062 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22063 |
// GIR_Coverage, 1177, |
22063 |
// GIR_Coverage, 1177, |
| 22064 |
GIR_Done, |
22064 |
GIR_Done, |
| 22065 |
// Label 1268: @55308 |
22065 |
// Label 1268: @55308 |
| 22066 |
GIM_Reject, |
22066 |
GIM_Reject, |
| 22067 |
// Label 1264: @55309 |
22067 |
// Label 1264: @55309 |
| 22068 |
GIM_Reject, |
22068 |
GIM_Reject, |
| 22069 |
// Label 1260: @55310 |
22069 |
// Label 1260: @55310 |
| 22070 |
GIM_Try, /*On fail goto*//*Label 1269*/ 55535, |
22070 |
GIM_Try, /*On fail goto*//*Label 1269*/ 55535, |
| 22071 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
22071 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 22072 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
22072 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 22073 |
GIM_Try, /*On fail goto*//*Label 1270*/ 55381, // Rule ID 160 // |
22073 |
GIM_Try, /*On fail goto*//*Label 1270*/ 55381, // Rule ID 160 // |
| 22074 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
22074 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 22075 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
22075 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 22076 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22076 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22077 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
22077 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 22078 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
22078 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22079 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
22079 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 22080 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
22080 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 22081 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
22081 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 22082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
22082 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 22083 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22083 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22084 |
// (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
22084 |
// (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 22085 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D32, |
22085 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D32, |
| 22086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22087 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr |
22087 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr |
| 22088 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
22088 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
| 22089 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
22089 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
| 22090 |
GIR_EraseFromParent, /*InsnID*/0, |
22090 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22091 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22091 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22092 |
// GIR_Coverage, 160, |
22092 |
// GIR_Coverage, 160, |
| 22093 |
GIR_Done, |
22093 |
GIR_Done, |
| 22094 |
// Label 1270: @55381 |
22094 |
// Label 1270: @55381 |
| 22095 |
GIM_Try, /*On fail goto*//*Label 1271*/ 55442, // Rule ID 162 // |
22095 |
GIM_Try, /*On fail goto*//*Label 1271*/ 55442, // Rule ID 162 // |
| 22096 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
22096 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 22097 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
22097 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 22098 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22098 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22099 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
22099 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 22100 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
22100 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22101 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
22101 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 22102 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
22102 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 22103 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
22103 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 22104 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
22104 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 22105 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22105 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22106 |
// (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
22106 |
// (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 22107 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D64, |
22107 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D64, |
| 22108 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22108 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22109 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr |
22109 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr |
| 22110 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
22110 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs |
| 22111 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
22111 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft |
| 22112 |
GIR_EraseFromParent, /*InsnID*/0, |
22112 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22113 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22113 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22114 |
// GIR_Coverage, 162, |
22114 |
// GIR_Coverage, 162, |
| 22115 |
GIR_Done, |
22115 |
GIR_Done, |
| 22116 |
// Label 1271: @55442 |
22116 |
// Label 1271: @55442 |
| 22117 |
GIM_Try, /*On fail goto*//*Label 1272*/ 55465, // Rule ID 155 // |
22117 |
GIM_Try, /*On fail goto*//*Label 1272*/ 55465, // Rule ID 155 // |
| 22118 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
22118 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
| 22119 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
22119 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 22120 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
22120 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 22121 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
22121 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 22122 |
// (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
22122 |
// (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 22123 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32, |
22123 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32, |
| 22124 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22124 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22125 |
// GIR_Coverage, 155, |
22125 |
// GIR_Coverage, 155, |
| 22126 |
GIR_Done, |
22126 |
GIR_Done, |
| 22127 |
// Label 1272: @55465 |
22127 |
// Label 1272: @55465 |
| 22128 |
GIM_Try, /*On fail goto*//*Label 1273*/ 55488, // Rule ID 156 // |
22128 |
GIM_Try, /*On fail goto*//*Label 1273*/ 55488, // Rule ID 156 // |
| 22129 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
22129 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
| 22130 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
22130 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 22131 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
22131 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 22132 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
22132 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 22133 |
// (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
22133 |
// (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 22134 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64, |
22134 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64, |
| 22135 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22135 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22136 |
// GIR_Coverage, 156, |
22136 |
// GIR_Coverage, 156, |
| 22137 |
GIR_Done, |
22137 |
GIR_Done, |
| 22138 |
// Label 1273: @55488 |
22138 |
// Label 1273: @55488 |
| 22139 |
GIM_Try, /*On fail goto*//*Label 1274*/ 55511, // Rule ID 1128 // |
22139 |
GIM_Try, /*On fail goto*//*Label 1274*/ 55511, // Rule ID 1128 // |
| 22140 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
22140 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
| 22141 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
22141 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 22142 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
22142 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 22143 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
22143 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 22144 |
// (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
22144 |
// (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 22145 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32_MM, |
22145 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32_MM, |
| 22146 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22146 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22147 |
// GIR_Coverage, 1128, |
22147 |
// GIR_Coverage, 1128, |
| 22148 |
GIR_Done, |
22148 |
GIR_Done, |
| 22149 |
// Label 1274: @55511 |
22149 |
// Label 1274: @55511 |
| 22150 |
GIM_Try, /*On fail goto*//*Label 1275*/ 55534, // Rule ID 1129 // |
22150 |
GIM_Try, /*On fail goto*//*Label 1275*/ 55534, // Rule ID 1129 // |
| 22151 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
22151 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
| 22152 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
22152 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 22153 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
22153 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 22154 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
22154 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 22155 |
// (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
22155 |
// (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 22156 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64_MM, |
22156 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64_MM, |
| 22157 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22157 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22158 |
// GIR_Coverage, 1129, |
22158 |
// GIR_Coverage, 1129, |
| 22159 |
GIR_Done, |
22159 |
GIR_Done, |
| 22160 |
// Label 1275: @55534 |
22160 |
// Label 1275: @55534 |
| 22161 |
GIM_Reject, |
22161 |
GIM_Reject, |
| 22162 |
// Label 1269: @55535 |
22162 |
// Label 1269: @55535 |
| 22163 |
GIM_Reject, |
22163 |
GIM_Reject, |
| 22164 |
// Label 1261: @55536 |
22164 |
// Label 1261: @55536 |
| 22165 |
GIM_Try, /*On fail goto*//*Label 1276*/ 55632, |
22165 |
GIM_Try, /*On fail goto*//*Label 1276*/ 55632, |
| 22166 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
22166 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22167 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
22167 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22168 |
GIM_Try, /*On fail goto*//*Label 1277*/ 55608, // Rule ID 1947 // |
22168 |
GIM_Try, /*On fail goto*//*Label 1277*/ 55608, // Rule ID 1947 // |
| 22169 |
GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
22169 |
GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
| 22170 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, |
22170 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 22171 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
22171 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 22172 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
22172 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22173 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
22173 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 22174 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
22174 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22175 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
22175 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22176 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
22176 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 22177 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
22177 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 22178 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22178 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22179 |
// (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
22179 |
// (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 22180 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_D, |
22180 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_D, |
| 22181 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
22181 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
| 22182 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
22182 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
| 22183 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
22183 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 22184 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
22184 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 22185 |
GIR_EraseFromParent, /*InsnID*/0, |
22185 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22186 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22186 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22187 |
// GIR_Coverage, 1947, |
22187 |
// GIR_Coverage, 1947, |
| 22188 |
GIR_Done, |
22188 |
GIR_Done, |
| 22189 |
// Label 1277: @55608 |
22189 |
// Label 1277: @55608 |
| 22190 |
GIM_Try, /*On fail goto*//*Label 1278*/ 55631, // Rule ID 747 // |
22190 |
GIM_Try, /*On fail goto*//*Label 1278*/ 55631, // Rule ID 747 // |
| 22191 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22191 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22192 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
22192 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 22193 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
22193 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 22194 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
22194 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 22195 |
// (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
22195 |
// (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 22196 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D, |
22196 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D, |
| 22197 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22197 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22198 |
// GIR_Coverage, 747, |
22198 |
// GIR_Coverage, 747, |
| 22199 |
GIR_Done, |
22199 |
GIR_Done, |
| 22200 |
// Label 1278: @55631 |
22200 |
// Label 1278: @55631 |
| 22201 |
GIM_Reject, |
22201 |
GIM_Reject, |
| 22202 |
// Label 1276: @55632 |
22202 |
// Label 1276: @55632 |
| 22203 |
GIM_Reject, |
22203 |
GIM_Reject, |
| 22204 |
// Label 1262: @55633 |
22204 |
// Label 1262: @55633 |
| 22205 |
GIM_Try, /*On fail goto*//*Label 1279*/ 55729, |
22205 |
GIM_Try, /*On fail goto*//*Label 1279*/ 55729, |
| 22206 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
22206 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22207 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
22207 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22208 |
GIM_Try, /*On fail goto*//*Label 1280*/ 55705, // Rule ID 1946 // |
22208 |
GIM_Try, /*On fail goto*//*Label 1280*/ 55705, // Rule ID 1946 // |
| 22209 |
GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
22209 |
GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc, |
| 22210 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, |
22210 |
GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 22211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
22211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 22212 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
22212 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22213 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
22213 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL, |
| 22214 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
22214 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22215 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
22215 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22216 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
22216 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 22217 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
22217 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 22218 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22218 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22219 |
// (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
22219 |
// (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 22220 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_W, |
22220 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_W, |
| 22221 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
22221 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
| 22222 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
22222 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd |
| 22223 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
22223 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws |
| 22224 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
22224 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt |
| 22225 |
GIR_EraseFromParent, /*InsnID*/0, |
22225 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22226 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22226 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22227 |
// GIR_Coverage, 1946, |
22227 |
// GIR_Coverage, 1946, |
| 22228 |
GIR_Done, |
22228 |
GIR_Done, |
| 22229 |
// Label 1280: @55705 |
22229 |
// Label 1280: @55705 |
| 22230 |
GIM_Try, /*On fail goto*//*Label 1281*/ 55728, // Rule ID 746 // |
22230 |
GIM_Try, /*On fail goto*//*Label 1281*/ 55728, // Rule ID 746 // |
| 22231 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22231 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22232 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
22232 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 22233 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
22233 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 22234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
22234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 22235 |
// (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
22235 |
// (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 22236 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_W, |
22236 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_W, |
| 22237 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22237 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22238 |
// GIR_Coverage, 746, |
22238 |
// GIR_Coverage, 746, |
| 22239 |
GIR_Done, |
22239 |
GIR_Done, |
| 22240 |
// Label 1281: @55728 |
22240 |
// Label 1281: @55728 |
| 22241 |
GIM_Reject, |
22241 |
GIM_Reject, |
| 22242 |
// Label 1279: @55729 |
22242 |
// Label 1279: @55729 |
| 22243 |
GIM_Reject, |
22243 |
GIM_Reject, |
| 22244 |
// Label 1263: @55730 |
22244 |
// Label 1263: @55730 |
| 22245 |
GIM_Reject, |
22245 |
GIM_Reject, |
| 22246 |
// Label 34: @55731 |
22246 |
// Label 34: @55731 |
| 22247 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1286*/ 56167, |
22247 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1286*/ 56167, |
| 22248 |
/*GILLT_s32*//*Label 1282*/ 55743, |
22248 |
/*GILLT_s32*//*Label 1282*/ 55743, |
| 22249 |
/*GILLT_s64*//*Label 1283*/ 55813, 0, |
22249 |
/*GILLT_s64*//*Label 1283*/ 55813, 0, |
| 22250 |
/*GILLT_v2s64*//*Label 1284*/ 55917, 0, |
22250 |
/*GILLT_v2s64*//*Label 1284*/ 55917, 0, |
| 22251 |
/*GILLT_v4s32*//*Label 1285*/ 56042, |
22251 |
/*GILLT_v4s32*//*Label 1285*/ 56042, |
| 22252 |
// Label 1282: @55743 |
22252 |
// Label 1282: @55743 |
| 22253 |
GIM_Try, /*On fail goto*//*Label 1287*/ 55812, |
22253 |
GIM_Try, /*On fail goto*//*Label 1287*/ 55812, |
| 22254 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
22254 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 22255 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
22255 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 22256 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
22256 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 22257 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22257 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22258 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22258 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22259 |
GIM_Try, /*On fail goto*//*Label 1288*/ 55776, // Rule ID 151 // |
22259 |
GIM_Try, /*On fail goto*//*Label 1288*/ 55776, // Rule ID 151 // |
| 22260 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
22260 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 22261 |
// (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
22261 |
// (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 22262 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S, |
22262 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S, |
| 22263 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22263 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22264 |
// GIR_Coverage, 151, |
22264 |
// GIR_Coverage, 151, |
| 22265 |
GIR_Done, |
22265 |
GIR_Done, |
| 22266 |
// Label 1288: @55776 |
22266 |
// Label 1288: @55776 |
| 22267 |
GIM_Try, /*On fail goto*//*Label 1289*/ 55787, // Rule ID 1120 // |
22267 |
GIM_Try, /*On fail goto*//*Label 1289*/ 55787, // Rule ID 1120 // |
| 22268 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
22268 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
| 22269 |
// (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
22269 |
// (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 22270 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S_MM, |
22270 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S_MM, |
| 22271 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22271 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22272 |
// GIR_Coverage, 1120, |
22272 |
// GIR_Coverage, 1120, |
| 22273 |
GIR_Done, |
22273 |
GIR_Done, |
| 22274 |
// Label 1289: @55787 |
22274 |
// Label 1289: @55787 |
| 22275 |
GIM_Try, /*On fail goto*//*Label 1290*/ 55811, // Rule ID 1178 // |
22275 |
GIM_Try, /*On fail goto*//*Label 1290*/ 55811, // Rule ID 1178 // |
| 22276 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
22276 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 22277 |
// (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) |
22277 |
// (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) |
| 22278 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMUL_S_MMR6, |
22278 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMUL_S_MMR6, |
| 22279 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22279 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22280 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft |
22280 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft |
| 22281 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs |
22281 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs |
| 22282 |
GIR_EraseFromParent, /*InsnID*/0, |
22282 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22283 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22283 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22284 |
// GIR_Coverage, 1178, |
22284 |
// GIR_Coverage, 1178, |
| 22285 |
GIR_Done, |
22285 |
GIR_Done, |
| 22286 |
// Label 1290: @55811 |
22286 |
// Label 1290: @55811 |
| 22287 |
GIM_Reject, |
22287 |
GIM_Reject, |
| 22288 |
// Label 1287: @55812 |
22288 |
// Label 1287: @55812 |
| 22289 |
GIM_Reject, |
22289 |
GIM_Reject, |
| 22290 |
// Label 1283: @55813 |
22290 |
// Label 1283: @55813 |
| 22291 |
GIM_Try, /*On fail goto*//*Label 1291*/ 55916, |
22291 |
GIM_Try, /*On fail goto*//*Label 1291*/ 55916, |
| 22292 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
22292 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 22293 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
22293 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 22294 |
GIM_Try, /*On fail goto*//*Label 1292*/ 55846, // Rule ID 152 // |
22294 |
GIM_Try, /*On fail goto*//*Label 1292*/ 55846, // Rule ID 152 // |
| 22295 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
22295 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
| 22296 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
22296 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 22297 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
22297 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 22298 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
22298 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 22299 |
// (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
22299 |
// (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 22300 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32, |
22300 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32, |
| 22301 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22301 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22302 |
// GIR_Coverage, 152, |
22302 |
// GIR_Coverage, 152, |
| 22303 |
GIR_Done, |
22303 |
GIR_Done, |
| 22304 |
// Label 1292: @55846 |
22304 |
// Label 1292: @55846 |
| 22305 |
GIM_Try, /*On fail goto*//*Label 1293*/ 55869, // Rule ID 153 // |
22305 |
GIM_Try, /*On fail goto*//*Label 1293*/ 55869, // Rule ID 153 // |
| 22306 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
22306 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
| 22307 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
22307 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 22308 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
22308 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 22309 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
22309 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 22310 |
// (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
22310 |
// (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 22311 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64, |
22311 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64, |
| 22312 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22312 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22313 |
// GIR_Coverage, 153, |
22313 |
// GIR_Coverage, 153, |
| 22314 |
GIR_Done, |
22314 |
GIR_Done, |
| 22315 |
// Label 1293: @55869 |
22315 |
// Label 1293: @55869 |
| 22316 |
GIM_Try, /*On fail goto*//*Label 1294*/ 55892, // Rule ID 1126 // |
22316 |
GIM_Try, /*On fail goto*//*Label 1294*/ 55892, // Rule ID 1126 // |
| 22317 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
22317 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
| 22318 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
22318 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 22319 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
22319 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 22320 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
22320 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 22321 |
// (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
22321 |
// (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 22322 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32_MM, |
22322 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32_MM, |
| 22323 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22323 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22324 |
// GIR_Coverage, 1126, |
22324 |
// GIR_Coverage, 1126, |
| 22325 |
GIR_Done, |
22325 |
GIR_Done, |
| 22326 |
// Label 1294: @55892 |
22326 |
// Label 1294: @55892 |
| 22327 |
GIM_Try, /*On fail goto*//*Label 1295*/ 55915, // Rule ID 1127 // |
22327 |
GIM_Try, /*On fail goto*//*Label 1295*/ 55915, // Rule ID 1127 // |
| 22328 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
22328 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
| 22329 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
22329 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 22330 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
22330 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 22331 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
22331 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 22332 |
// (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
22332 |
// (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 22333 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64_MM, |
22333 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64_MM, |
| 22334 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22334 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22335 |
// GIR_Coverage, 1127, |
22335 |
// GIR_Coverage, 1127, |
| 22336 |
GIR_Done, |
22336 |
GIR_Done, |
| 22337 |
// Label 1295: @55915 |
22337 |
// Label 1295: @55915 |
| 22338 |
GIM_Reject, |
22338 |
GIM_Reject, |
| 22339 |
// Label 1291: @55916 |
22339 |
// Label 1291: @55916 |
| 22340 |
GIM_Reject, |
22340 |
GIM_Reject, |
| 22341 |
// Label 1284: @55917 |
22341 |
// Label 1284: @55917 |
| 22342 |
GIM_Try, /*On fail goto*//*Label 1296*/ 56041, |
22342 |
GIM_Try, /*On fail goto*//*Label 1296*/ 56041, |
| 22343 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
22343 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22344 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
22344 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22345 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
22345 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 22346 |
GIM_Try, /*On fail goto*//*Label 1297*/ 55976, // Rule ID 2347 // |
22346 |
GIM_Try, /*On fail goto*//*Label 1297*/ 55976, // Rule ID 2347 // |
| 22347 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22347 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22348 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22348 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22349 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2, |
22349 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2, |
| 22350 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
22350 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22351 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
22351 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 22352 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
22352 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 22353 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22353 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22354 |
// (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
22354 |
// (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 22355 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D, |
22355 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D, |
| 22356 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
22356 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 22357 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
22357 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 22358 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
22358 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
| 22359 |
GIR_EraseFromParent, /*InsnID*/0, |
22359 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22360 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22360 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22361 |
// GIR_Coverage, 2347, |
22361 |
// GIR_Coverage, 2347, |
| 22362 |
GIR_Done, |
22362 |
GIR_Done, |
| 22363 |
// Label 1297: @55976 |
22363 |
// Label 1297: @55976 |
| 22364 |
GIM_Try, /*On fail goto*//*Label 1298*/ 56021, // Rule ID 689 // |
22364 |
GIM_Try, /*On fail goto*//*Label 1298*/ 56021, // Rule ID 689 // |
| 22365 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22365 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22366 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
22366 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 22367 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
22367 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22368 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2, |
22368 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2, |
| 22369 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
22369 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22370 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
22370 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 22371 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22371 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22372 |
// (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
22372 |
// (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 22373 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D, |
22373 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D, |
| 22374 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
22374 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 22375 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
22375 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 22376 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
22376 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
| 22377 |
GIR_EraseFromParent, /*InsnID*/0, |
22377 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22378 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22378 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22379 |
// GIR_Coverage, 689, |
22379 |
// GIR_Coverage, 689, |
| 22380 |
GIR_Done, |
22380 |
GIR_Done, |
| 22381 |
// Label 1298: @56021 |
22381 |
// Label 1298: @56021 |
| 22382 |
GIM_Try, /*On fail goto*//*Label 1299*/ 56040, // Rule ID 725 // |
22382 |
GIM_Try, /*On fail goto*//*Label 1299*/ 56040, // Rule ID 725 // |
| 22383 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22383 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22384 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
22384 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 22385 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
22385 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 22386 |
// (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
22386 |
// (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 22387 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D, |
22387 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D, |
| 22388 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22388 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22389 |
// GIR_Coverage, 725, |
22389 |
// GIR_Coverage, 725, |
| 22390 |
GIR_Done, |
22390 |
GIR_Done, |
| 22391 |
// Label 1299: @56040 |
22391 |
// Label 1299: @56040 |
| 22392 |
GIM_Reject, |
22392 |
GIM_Reject, |
| 22393 |
// Label 1296: @56041 |
22393 |
// Label 1296: @56041 |
| 22394 |
GIM_Reject, |
22394 |
GIM_Reject, |
| 22395 |
// Label 1285: @56042 |
22395 |
// Label 1285: @56042 |
| 22396 |
GIM_Try, /*On fail goto*//*Label 1300*/ 56166, |
22396 |
GIM_Try, /*On fail goto*//*Label 1300*/ 56166, |
| 22397 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
22397 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22398 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
22398 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22399 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
22399 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 22400 |
GIM_Try, /*On fail goto*//*Label 1301*/ 56101, // Rule ID 2346 // |
22400 |
GIM_Try, /*On fail goto*//*Label 1301*/ 56101, // Rule ID 2346 // |
| 22401 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22401 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22402 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22402 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22403 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2, |
22403 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2, |
| 22404 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
22404 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22405 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
22405 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 22406 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
22406 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 22407 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22407 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22408 |
// (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
22408 |
// (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 22409 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W, |
22409 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W, |
| 22410 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
22410 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 22411 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
22411 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws |
| 22412 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
22412 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
| 22413 |
GIR_EraseFromParent, /*InsnID*/0, |
22413 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22414 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22414 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22415 |
// GIR_Coverage, 2346, |
22415 |
// GIR_Coverage, 2346, |
| 22416 |
GIR_Done, |
22416 |
GIR_Done, |
| 22417 |
// Label 1301: @56101 |
22417 |
// Label 1301: @56101 |
| 22418 |
GIM_Try, /*On fail goto*//*Label 1302*/ 56146, // Rule ID 688 // |
22418 |
GIM_Try, /*On fail goto*//*Label 1302*/ 56146, // Rule ID 688 // |
| 22419 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22419 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22420 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
22420 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 22421 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
22421 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 22422 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2, |
22422 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2, |
| 22423 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
22423 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22424 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
22424 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 22425 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22425 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22426 |
// (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
22426 |
// (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 22427 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W, |
22427 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W, |
| 22428 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
22428 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd |
| 22429 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
22429 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 22430 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
22430 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt |
| 22431 |
GIR_EraseFromParent, /*InsnID*/0, |
22431 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22432 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22432 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22433 |
// GIR_Coverage, 688, |
22433 |
// GIR_Coverage, 688, |
| 22434 |
GIR_Done, |
22434 |
GIR_Done, |
| 22435 |
// Label 1302: @56146 |
22435 |
// Label 1302: @56146 |
| 22436 |
GIM_Try, /*On fail goto*//*Label 1303*/ 56165, // Rule ID 724 // |
22436 |
GIM_Try, /*On fail goto*//*Label 1303*/ 56165, // Rule ID 724 // |
| 22437 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22437 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22438 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
22438 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 22439 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
22439 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 22440 |
// (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
22440 |
// (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 22441 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_W, |
22441 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_W, |
| 22442 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22442 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22443 |
// GIR_Coverage, 724, |
22443 |
// GIR_Coverage, 724, |
| 22444 |
GIR_Done, |
22444 |
GIR_Done, |
| 22445 |
// Label 1303: @56165 |
22445 |
// Label 1303: @56165 |
| 22446 |
GIM_Reject, |
22446 |
GIM_Reject, |
| 22447 |
// Label 1300: @56166 |
22447 |
// Label 1300: @56166 |
| 22448 |
GIM_Reject, |
22448 |
GIM_Reject, |
| 22449 |
// Label 1286: @56167 |
22449 |
// Label 1286: @56167 |
| 22450 |
GIM_Reject, |
22450 |
GIM_Reject, |
| 22451 |
// Label 35: @56168 |
22451 |
// Label 35: @56168 |
| 22452 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1306*/ 56257, |
22452 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1306*/ 56257, |
| 22453 |
/*GILLT_v2s64*//*Label 1304*/ 56177, 0, |
22453 |
/*GILLT_v2s64*//*Label 1304*/ 56177, 0, |
| 22454 |
/*GILLT_v4s32*//*Label 1305*/ 56217, |
22454 |
/*GILLT_v4s32*//*Label 1305*/ 56217, |
| 22455 |
// Label 1304: @56177 |
22455 |
// Label 1304: @56177 |
| 22456 |
GIM_Try, /*On fail goto*//*Label 1307*/ 56216, // Rule ID 713 // |
22456 |
GIM_Try, /*On fail goto*//*Label 1307*/ 56216, // Rule ID 713 // |
| 22457 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22457 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22458 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
22458 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22459 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
22459 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22460 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
22460 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22461 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
22461 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 22462 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
22462 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 22463 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
22463 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 22464 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
22464 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID, |
| 22465 |
// (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
22465 |
// (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 22466 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_D, |
22466 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_D, |
| 22467 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22467 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22468 |
// GIR_Coverage, 713, |
22468 |
// GIR_Coverage, 713, |
| 22469 |
GIR_Done, |
22469 |
GIR_Done, |
| 22470 |
// Label 1307: @56216 |
22470 |
// Label 1307: @56216 |
| 22471 |
GIM_Reject, |
22471 |
GIM_Reject, |
| 22472 |
// Label 1305: @56217 |
22472 |
// Label 1305: @56217 |
| 22473 |
GIM_Try, /*On fail goto*//*Label 1308*/ 56256, // Rule ID 712 // |
22473 |
GIM_Try, /*On fail goto*//*Label 1308*/ 56256, // Rule ID 712 // |
| 22474 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22474 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22475 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
22475 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22476 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
22476 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22477 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
22477 |
GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22478 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
22478 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 22479 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
22479 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 22480 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
22480 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 22481 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
22481 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID, |
| 22482 |
// (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
22482 |
// (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 22483 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_W, |
22483 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_W, |
| 22484 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22484 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22485 |
// GIR_Coverage, 712, |
22485 |
// GIR_Coverage, 712, |
| 22486 |
GIR_Done, |
22486 |
GIR_Done, |
| 22487 |
// Label 1308: @56256 |
22487 |
// Label 1308: @56256 |
| 22488 |
GIM_Reject, |
22488 |
GIM_Reject, |
| 22489 |
// Label 1306: @56257 |
22489 |
// Label 1306: @56257 |
| 22490 |
GIM_Reject, |
22490 |
GIM_Reject, |
| 22491 |
// Label 36: @56258 |
22491 |
// Label 36: @56258 |
| 22492 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1313*/ 56508, |
22492 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1313*/ 56508, |
| 22493 |
/*GILLT_s32*//*Label 1309*/ 56270, |
22493 |
/*GILLT_s32*//*Label 1309*/ 56270, |
| 22494 |
/*GILLT_s64*//*Label 1310*/ 56340, 0, |
22494 |
/*GILLT_s64*//*Label 1310*/ 56340, 0, |
| 22495 |
/*GILLT_v2s64*//*Label 1311*/ 56444, 0, |
22495 |
/*GILLT_v2s64*//*Label 1311*/ 56444, 0, |
| 22496 |
/*GILLT_v4s32*//*Label 1312*/ 56476, |
22496 |
/*GILLT_v4s32*//*Label 1312*/ 56476, |
| 22497 |
// Label 1309: @56270 |
22497 |
// Label 1309: @56270 |
| 22498 |
GIM_Try, /*On fail goto*//*Label 1314*/ 56339, |
22498 |
GIM_Try, /*On fail goto*//*Label 1314*/ 56339, |
| 22499 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
22499 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 22500 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
22500 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 22501 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
22501 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 22502 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22502 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22503 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22503 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22504 |
GIM_Try, /*On fail goto*//*Label 1315*/ 56303, // Rule ID 148 // |
22504 |
GIM_Try, /*On fail goto*//*Label 1315*/ 56303, // Rule ID 148 // |
| 22505 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
22505 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 22506 |
// (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
22506 |
// (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 22507 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S, |
22507 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S, |
| 22508 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22508 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22509 |
// GIR_Coverage, 148, |
22509 |
// GIR_Coverage, 148, |
| 22510 |
GIR_Done, |
22510 |
GIR_Done, |
| 22511 |
// Label 1315: @56303 |
22511 |
// Label 1315: @56303 |
| 22512 |
GIM_Try, /*On fail goto*//*Label 1316*/ 56314, // Rule ID 1119 // |
22512 |
GIM_Try, /*On fail goto*//*Label 1316*/ 56314, // Rule ID 1119 // |
| 22513 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
22513 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
| 22514 |
// (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
22514 |
// (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 22515 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S_MM, |
22515 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S_MM, |
| 22516 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22516 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22517 |
// GIR_Coverage, 1119, |
22517 |
// GIR_Coverage, 1119, |
| 22518 |
GIR_Done, |
22518 |
GIR_Done, |
| 22519 |
// Label 1316: @56314 |
22519 |
// Label 1316: @56314 |
| 22520 |
GIM_Try, /*On fail goto*//*Label 1317*/ 56338, // Rule ID 1179 // |
22520 |
GIM_Try, /*On fail goto*//*Label 1317*/ 56338, // Rule ID 1179 // |
| 22521 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
22521 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 22522 |
// (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) |
22522 |
// (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) |
| 22523 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FDIV_S_MMR6, |
22523 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FDIV_S_MMR6, |
| 22524 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22524 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22525 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft |
22525 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft |
| 22526 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs |
22526 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs |
| 22527 |
GIR_EraseFromParent, /*InsnID*/0, |
22527 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22528 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22528 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22529 |
// GIR_Coverage, 1179, |
22529 |
// GIR_Coverage, 1179, |
| 22530 |
GIR_Done, |
22530 |
GIR_Done, |
| 22531 |
// Label 1317: @56338 |
22531 |
// Label 1317: @56338 |
| 22532 |
GIM_Reject, |
22532 |
GIM_Reject, |
| 22533 |
// Label 1314: @56339 |
22533 |
// Label 1314: @56339 |
| 22534 |
GIM_Reject, |
22534 |
GIM_Reject, |
| 22535 |
// Label 1310: @56340 |
22535 |
// Label 1310: @56340 |
| 22536 |
GIM_Try, /*On fail goto*//*Label 1318*/ 56443, |
22536 |
GIM_Try, /*On fail goto*//*Label 1318*/ 56443, |
| 22537 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
22537 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 22538 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
22538 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, |
| 22539 |
GIM_Try, /*On fail goto*//*Label 1319*/ 56373, // Rule ID 149 // |
22539 |
GIM_Try, /*On fail goto*//*Label 1319*/ 56373, // Rule ID 149 // |
| 22540 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
22540 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
| 22541 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
22541 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 22542 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
22542 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 22543 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
22543 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 22544 |
// (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
22544 |
// (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 22545 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32, |
22545 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32, |
| 22546 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22546 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22547 |
// GIR_Coverage, 149, |
22547 |
// GIR_Coverage, 149, |
| 22548 |
GIR_Done, |
22548 |
GIR_Done, |
| 22549 |
// Label 1319: @56373 |
22549 |
// Label 1319: @56373 |
| 22550 |
GIM_Try, /*On fail goto*//*Label 1320*/ 56396, // Rule ID 150 // |
22550 |
GIM_Try, /*On fail goto*//*Label 1320*/ 56396, // Rule ID 150 // |
| 22551 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
22551 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
| 22552 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
22552 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 22553 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
22553 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 22554 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
22554 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 22555 |
// (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
22555 |
// (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 22556 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64, |
22556 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64, |
| 22557 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22557 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22558 |
// GIR_Coverage, 150, |
22558 |
// GIR_Coverage, 150, |
| 22559 |
GIR_Done, |
22559 |
GIR_Done, |
| 22560 |
// Label 1320: @56396 |
22560 |
// Label 1320: @56396 |
| 22561 |
GIM_Try, /*On fail goto*//*Label 1321*/ 56419, // Rule ID 1124 // |
22561 |
GIM_Try, /*On fail goto*//*Label 1321*/ 56419, // Rule ID 1124 // |
| 22562 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
22562 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
| 22563 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
22563 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 22564 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
22564 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 22565 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
22565 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 22566 |
// (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
22566 |
// (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 22567 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32_MM, |
22567 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32_MM, |
| 22568 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22568 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22569 |
// GIR_Coverage, 1124, |
22569 |
// GIR_Coverage, 1124, |
| 22570 |
GIR_Done, |
22570 |
GIR_Done, |
| 22571 |
// Label 1321: @56419 |
22571 |
// Label 1321: @56419 |
| 22572 |
GIM_Try, /*On fail goto*//*Label 1322*/ 56442, // Rule ID 1125 // |
22572 |
GIM_Try, /*On fail goto*//*Label 1322*/ 56442, // Rule ID 1125 // |
| 22573 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
22573 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
| 22574 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
22574 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 22575 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
22575 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 22576 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
22576 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 22577 |
// (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
22577 |
// (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 22578 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64_MM, |
22578 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64_MM, |
| 22579 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22579 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22580 |
// GIR_Coverage, 1125, |
22580 |
// GIR_Coverage, 1125, |
| 22581 |
GIR_Done, |
22581 |
GIR_Done, |
| 22582 |
// Label 1322: @56442 |
22582 |
// Label 1322: @56442 |
| 22583 |
GIM_Reject, |
22583 |
GIM_Reject, |
| 22584 |
// Label 1318: @56443 |
22584 |
// Label 1318: @56443 |
| 22585 |
GIM_Reject, |
22585 |
GIM_Reject, |
| 22586 |
// Label 1311: @56444 |
22586 |
// Label 1311: @56444 |
| 22587 |
GIM_Try, /*On fail goto*//*Label 1323*/ 56475, // Rule ID 685 // |
22587 |
GIM_Try, /*On fail goto*//*Label 1323*/ 56475, // Rule ID 685 // |
| 22588 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22588 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22589 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
22589 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22590 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
22590 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22591 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
22591 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 22592 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
22592 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 22593 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
22593 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 22594 |
// (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
22594 |
// (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) |
| 22595 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D, |
22595 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D, |
| 22596 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22596 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22597 |
// GIR_Coverage, 685, |
22597 |
// GIR_Coverage, 685, |
| 22598 |
GIR_Done, |
22598 |
GIR_Done, |
| 22599 |
// Label 1323: @56475 |
22599 |
// Label 1323: @56475 |
| 22600 |
GIM_Reject, |
22600 |
GIM_Reject, |
| 22601 |
// Label 1312: @56476 |
22601 |
// Label 1312: @56476 |
| 22602 |
GIM_Try, /*On fail goto*//*Label 1324*/ 56507, // Rule ID 684 // |
22602 |
GIM_Try, /*On fail goto*//*Label 1324*/ 56507, // Rule ID 684 // |
| 22603 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22603 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22604 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
22604 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22605 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
22605 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
22606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 22607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
22607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 22608 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
22608 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 22609 |
// (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
22609 |
// (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) |
| 22610 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_W, |
22610 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_W, |
| 22611 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22611 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22612 |
// GIR_Coverage, 684, |
22612 |
// GIR_Coverage, 684, |
| 22613 |
GIR_Done, |
22613 |
GIR_Done, |
| 22614 |
// Label 1324: @56507 |
22614 |
// Label 1324: @56507 |
| 22615 |
GIM_Reject, |
22615 |
GIM_Reject, |
| 22616 |
// Label 1313: @56508 |
22616 |
// Label 1313: @56508 |
| 22617 |
GIM_Reject, |
22617 |
GIM_Reject, |
| 22618 |
// Label 37: @56509 |
22618 |
// Label 37: @56509 |
| 22619 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1327*/ 56566, |
22619 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1327*/ 56566, |
| 22620 |
/*GILLT_v2s64*//*Label 1325*/ 56518, 0, |
22620 |
/*GILLT_v2s64*//*Label 1325*/ 56518, 0, |
| 22621 |
/*GILLT_v4s32*//*Label 1326*/ 56542, |
22621 |
/*GILLT_v4s32*//*Label 1326*/ 56542, |
| 22622 |
// Label 1325: @56518 |
22622 |
// Label 1325: @56518 |
| 22623 |
GIM_Try, /*On fail goto*//*Label 1328*/ 56541, // Rule ID 691 // |
22623 |
GIM_Try, /*On fail goto*//*Label 1328*/ 56541, // Rule ID 691 // |
| 22624 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22624 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22625 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
22625 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22626 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
22626 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 22627 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
22627 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 22628 |
// (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) => (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) |
22628 |
// (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) => (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) |
| 22629 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_D_1_PSEUDO, |
22629 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_D_1_PSEUDO, |
| 22630 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22630 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22631 |
// GIR_Coverage, 691, |
22631 |
// GIR_Coverage, 691, |
| 22632 |
GIR_Done, |
22632 |
GIR_Done, |
| 22633 |
// Label 1328: @56541 |
22633 |
// Label 1328: @56541 |
| 22634 |
GIM_Reject, |
22634 |
GIM_Reject, |
| 22635 |
// Label 1326: @56542 |
22635 |
// Label 1326: @56542 |
| 22636 |
GIM_Try, /*On fail goto*//*Label 1329*/ 56565, // Rule ID 690 // |
22636 |
GIM_Try, /*On fail goto*//*Label 1329*/ 56565, // Rule ID 690 // |
| 22637 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22637 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22638 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
22638 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22639 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
22639 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 22640 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
22640 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 22641 |
// (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) => (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) |
22641 |
// (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) => (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) |
| 22642 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_W_1_PSEUDO, |
22642 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_W_1_PSEUDO, |
| 22643 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22643 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22644 |
// GIR_Coverage, 690, |
22644 |
// GIR_Coverage, 690, |
| 22645 |
GIR_Done, |
22645 |
GIR_Done, |
| 22646 |
// Label 1329: @56565 |
22646 |
// Label 1329: @56565 |
| 22647 |
GIM_Reject, |
22647 |
GIM_Reject, |
| 22648 |
// Label 1327: @56566 |
22648 |
// Label 1327: @56566 |
| 22649 |
GIM_Reject, |
22649 |
GIM_Reject, |
| 22650 |
// Label 38: @56567 |
22650 |
// Label 38: @56567 |
| 22651 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1332*/ 56624, |
22651 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1332*/ 56624, |
| 22652 |
/*GILLT_v2s64*//*Label 1330*/ 56576, 0, |
22652 |
/*GILLT_v2s64*//*Label 1330*/ 56576, 0, |
| 22653 |
/*GILLT_v4s32*//*Label 1331*/ 56600, |
22653 |
/*GILLT_v4s32*//*Label 1331*/ 56600, |
| 22654 |
// Label 1330: @56576 |
22654 |
// Label 1330: @56576 |
| 22655 |
GIM_Try, /*On fail goto*//*Label 1333*/ 56599, // Rule ID 711 // |
22655 |
GIM_Try, /*On fail goto*//*Label 1333*/ 56599, // Rule ID 711 // |
| 22656 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22656 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22657 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
22657 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 22658 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
22658 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 22659 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
22659 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 22660 |
// (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
22660 |
// (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
| 22661 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_D, |
22661 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_D, |
| 22662 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22662 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22663 |
// GIR_Coverage, 711, |
22663 |
// GIR_Coverage, 711, |
| 22664 |
GIR_Done, |
22664 |
GIR_Done, |
| 22665 |
// Label 1333: @56599 |
22665 |
// Label 1333: @56599 |
| 22666 |
GIM_Reject, |
22666 |
GIM_Reject, |
| 22667 |
// Label 1331: @56600 |
22667 |
// Label 1331: @56600 |
| 22668 |
GIM_Try, /*On fail goto*//*Label 1334*/ 56623, // Rule ID 710 // |
22668 |
GIM_Try, /*On fail goto*//*Label 1334*/ 56623, // Rule ID 710 // |
| 22669 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
22669 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 22670 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
22670 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 22671 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
22671 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 22672 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
22672 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 22673 |
// (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
22673 |
// (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
| 22674 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_W, |
22674 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_W, |
| 22675 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22675 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22676 |
// GIR_Coverage, 710, |
22676 |
// GIR_Coverage, 710, |
| 22677 |
GIR_Done, |
22677 |
GIR_Done, |
| 22678 |
// Label 1334: @56623 |
22678 |
// Label 1334: @56623 |
| 22679 |
GIM_Reject, |
22679 |
GIM_Reject, |
| 22680 |
// Label 1332: @56624 |
22680 |
// Label 1332: @56624 |
| 22681 |
GIM_Reject, |
22681 |
GIM_Reject, |
| 22682 |
// Label 39: @56625 |
22682 |
// Label 39: @56625 |
| 22683 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1337*/ 57920, |
22683 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1337*/ 57920, |
| 22684 |
/*GILLT_s32*//*Label 1335*/ 56633, |
22684 |
/*GILLT_s32*//*Label 1335*/ 56633, |
| 22685 |
/*GILLT_s64*//*Label 1336*/ 57134, |
22685 |
/*GILLT_s64*//*Label 1336*/ 57134, |
| 22686 |
// Label 1335: @56633 |
22686 |
// Label 1335: @56633 |
| 22687 |
GIM_Try, /*On fail goto*//*Label 1338*/ 57133, |
22687 |
GIM_Try, /*On fail goto*//*Label 1338*/ 57133, |
| 22688 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
22688 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 22689 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
22689 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 22690 |
GIM_Try, /*On fail goto*//*Label 1339*/ 56717, // Rule ID 1446 // |
22690 |
GIM_Try, /*On fail goto*//*Label 1339*/ 56717, // Rule ID 1446 // |
| 22691 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
22691 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 22692 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22692 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22693 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
22693 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
| 22694 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
22694 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22695 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
22695 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 22696 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
22696 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 22697 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
22697 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 22698 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
22698 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22699 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
22699 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 22700 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22700 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22701 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22701 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22702 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22702 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22703 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22703 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22704 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
22704 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 22705 |
// (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
22705 |
// (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 22706 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S, |
22706 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S, |
| 22707 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22707 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22708 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
22708 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
| 22709 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
22709 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 22710 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
22710 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 22711 |
GIR_EraseFromParent, /*InsnID*/0, |
22711 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22712 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22712 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22713 |
// GIR_Coverage, 1446, |
22713 |
// GIR_Coverage, 1446, |
| 22714 |
GIR_Done, |
22714 |
GIR_Done, |
| 22715 |
// Label 1339: @56717 |
22715 |
// Label 1339: @56717 |
| 22716 |
GIM_Try, /*On fail goto*//*Label 1340*/ 56791, // Rule ID 2202 // |
22716 |
GIM_Try, /*On fail goto*//*Label 1340*/ 56791, // Rule ID 2202 // |
| 22717 |
GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6, |
22717 |
GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6, |
| 22718 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22718 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22719 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
22719 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
| 22720 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
22720 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22721 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
22721 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 22722 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
22722 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 22723 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
22723 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 22724 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
22724 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22725 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
22725 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 22726 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22726 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22727 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22727 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22728 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22728 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22729 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22729 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22730 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
22730 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 22731 |
// (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
22731 |
// (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 22732 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM, |
22732 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM, |
| 22733 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22733 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22734 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
22734 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
| 22735 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
22735 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 22736 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
22736 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 22737 |
GIR_EraseFromParent, /*InsnID*/0, |
22737 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22738 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22738 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22739 |
// GIR_Coverage, 2202, |
22739 |
// GIR_Coverage, 2202, |
| 22740 |
GIR_Done, |
22740 |
GIR_Done, |
| 22741 |
// Label 1340: @56791 |
22741 |
// Label 1340: @56791 |
| 22742 |
GIM_Try, /*On fail goto*//*Label 1341*/ 56865, // Rule ID 2382 // |
22742 |
GIM_Try, /*On fail goto*//*Label 1341*/ 56865, // Rule ID 2382 // |
| 22743 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
22743 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 22744 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22744 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22745 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
22745 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
| 22746 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
22746 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22747 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
22747 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 22748 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22748 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22749 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
22749 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 22750 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
22750 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 22751 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
22751 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22752 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
22752 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 22753 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22753 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22754 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22754 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22755 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22755 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22756 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
22756 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 22757 |
// (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
22757 |
// (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 22758 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S, |
22758 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S, |
| 22759 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22759 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22760 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr |
22760 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr |
| 22761 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
22761 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 22762 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
22762 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 22763 |
GIR_EraseFromParent, /*InsnID*/0, |
22763 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22764 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22764 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22765 |
// GIR_Coverage, 2382, |
22765 |
// GIR_Coverage, 2382, |
| 22766 |
GIR_Done, |
22766 |
GIR_Done, |
| 22767 |
// Label 1341: @56865 |
22767 |
// Label 1341: @56865 |
| 22768 |
GIM_Try, /*On fail goto*//*Label 1342*/ 56939, // Rule ID 2468 // |
22768 |
GIM_Try, /*On fail goto*//*Label 1342*/ 56939, // Rule ID 2468 // |
| 22769 |
GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6, |
22769 |
GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6, |
| 22770 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22770 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22771 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
22771 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
| 22772 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
22772 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22773 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
22773 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 22774 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22774 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22775 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
22775 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 22776 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
22776 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 22777 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
22777 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22778 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
22778 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 22779 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22779 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22780 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22780 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22781 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22781 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22782 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
22782 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 22783 |
// (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
22783 |
// (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 22784 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM, |
22784 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM, |
| 22785 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22785 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22786 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr |
22786 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr |
| 22787 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
22787 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 22788 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
22788 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 22789 |
GIR_EraseFromParent, /*InsnID*/0, |
22789 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22790 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22790 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22791 |
// GIR_Coverage, 2468, |
22791 |
// GIR_Coverage, 2468, |
| 22792 |
GIR_Done, |
22792 |
GIR_Done, |
| 22793 |
// Label 1342: @56939 |
22793 |
// Label 1342: @56939 |
| 22794 |
GIM_Try, /*On fail goto*//*Label 1343*/ 57013, // Rule ID 1447 // |
22794 |
GIM_Try, /*On fail goto*//*Label 1343*/ 57013, // Rule ID 1447 // |
| 22795 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
22795 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 22796 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22796 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22797 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
22797 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
| 22798 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
22798 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22799 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
22799 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 22800 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
22800 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 22801 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
22801 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 22802 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
22802 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22803 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
22803 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 22804 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22804 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22805 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22805 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22806 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22806 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22807 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22807 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22808 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
22808 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 22809 |
// (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
22809 |
// (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 22810 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S, |
22810 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S, |
| 22811 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22811 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22812 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
22812 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
| 22813 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
22813 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 22814 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
22814 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 22815 |
GIR_EraseFromParent, /*InsnID*/0, |
22815 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22816 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22816 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22817 |
// GIR_Coverage, 1447, |
22817 |
// GIR_Coverage, 1447, |
| 22818 |
GIR_Done, |
22818 |
GIR_Done, |
| 22819 |
// Label 1343: @57013 |
22819 |
// Label 1343: @57013 |
| 22820 |
GIM_Try, /*On fail goto*//*Label 1344*/ 57087, // Rule ID 2203 // |
22820 |
GIM_Try, /*On fail goto*//*Label 1344*/ 57087, // Rule ID 2203 // |
| 22821 |
GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6, |
22821 |
GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6, |
| 22822 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22822 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22823 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
22823 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
| 22824 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
22824 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 22825 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
22825 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 22826 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
22826 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 22827 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
22827 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 22828 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
22828 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 22829 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
22829 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 22830 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22830 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22831 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22831 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22832 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
22832 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID, |
| 22833 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22833 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22834 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
22834 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 22835 |
// (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
22835 |
// (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) |
| 22836 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S_MM, |
22836 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S_MM, |
| 22837 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22837 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22838 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
22838 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
| 22839 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
22839 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 22840 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
22840 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 22841 |
GIR_EraseFromParent, /*InsnID*/0, |
22841 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22842 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22842 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22843 |
// GIR_Coverage, 2203, |
22843 |
// GIR_Coverage, 2203, |
| 22844 |
GIR_Done, |
22844 |
GIR_Done, |
| 22845 |
// Label 1344: @57087 |
22845 |
// Label 1344: @57087 |
| 22846 |
GIM_Try, /*On fail goto*//*Label 1345*/ 57102, // Rule ID 123 // |
22846 |
GIM_Try, /*On fail goto*//*Label 1345*/ 57102, // Rule ID 123 // |
| 22847 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat, |
22847 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat, |
| 22848 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22848 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22849 |
// (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
22849 |
// (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
| 22850 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S, |
22850 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S, |
| 22851 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22851 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22852 |
// GIR_Coverage, 123, |
22852 |
// GIR_Coverage, 123, |
| 22853 |
GIR_Done, |
22853 |
GIR_Done, |
| 22854 |
// Label 1345: @57102 |
22854 |
// Label 1345: @57102 |
| 22855 |
GIM_Try, /*On fail goto*//*Label 1346*/ 57117, // Rule ID 1141 // |
22855 |
GIM_Try, /*On fail goto*//*Label 1346*/ 57117, // Rule ID 1141 // |
| 22856 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
22856 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
| 22857 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22857 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22858 |
// (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
22858 |
// (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
| 22859 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MM, |
22859 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MM, |
| 22860 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22860 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22861 |
// GIR_Coverage, 1141, |
22861 |
// GIR_Coverage, 1141, |
| 22862 |
GIR_Done, |
22862 |
GIR_Done, |
| 22863 |
// Label 1346: @57117 |
22863 |
// Label 1346: @57117 |
| 22864 |
GIM_Try, /*On fail goto*//*Label 1347*/ 57132, // Rule ID 1180 // |
22864 |
GIM_Try, /*On fail goto*//*Label 1347*/ 57132, // Rule ID 1180 // |
| 22865 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
22865 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat, |
| 22866 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
22866 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 22867 |
// (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
22867 |
// (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
| 22868 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MMR6, |
22868 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MMR6, |
| 22869 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22869 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22870 |
// GIR_Coverage, 1180, |
22870 |
// GIR_Coverage, 1180, |
| 22871 |
GIR_Done, |
22871 |
GIR_Done, |
| 22872 |
// Label 1347: @57132 |
22872 |
// Label 1347: @57132 |
| 22873 |
GIM_Reject, |
22873 |
GIM_Reject, |
| 22874 |
// Label 1338: @57133 |
22874 |
// Label 1338: @57133 |
| 22875 |
GIM_Reject, |
22875 |
GIM_Reject, |
| 22876 |
// Label 1336: @57134 |
22876 |
// Label 1336: @57134 |
| 22877 |
GIM_Try, /*On fail goto*//*Label 1348*/ 57919, |
22877 |
GIM_Try, /*On fail goto*//*Label 1348*/ 57919, |
| 22878 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
22878 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 22879 |
GIM_Try, /*On fail goto*//*Label 1349*/ 57218, // Rule ID 1448 // |
22879 |
GIM_Try, /*On fail goto*//*Label 1349*/ 57218, // Rule ID 1448 // |
| 22880 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
22880 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 22881 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
22881 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 22882 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22882 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22883 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
22883 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
| 22884 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
22884 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22885 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
22885 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 22886 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
22886 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 22887 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
22887 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 22888 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
22888 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22889 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
22889 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 22890 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
22890 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 22891 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
22891 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 22892 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
22892 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 22893 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22893 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22894 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
22894 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 22895 |
// (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
22895 |
// (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 22896 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32, |
22896 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32, |
| 22897 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22897 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22898 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
22898 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
| 22899 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
22899 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 22900 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
22900 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 22901 |
GIR_EraseFromParent, /*InsnID*/0, |
22901 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22902 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22902 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22903 |
// GIR_Coverage, 1448, |
22903 |
// GIR_Coverage, 1448, |
| 22904 |
GIR_Done, |
22904 |
GIR_Done, |
| 22905 |
// Label 1349: @57218 |
22905 |
// Label 1349: @57218 |
| 22906 |
GIM_Try, /*On fail goto*//*Label 1350*/ 57296, // Rule ID 1450 // |
22906 |
GIM_Try, /*On fail goto*//*Label 1350*/ 57296, // Rule ID 1450 // |
| 22907 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
22907 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 22908 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
22908 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 22909 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22909 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22910 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
22910 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
| 22911 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
22911 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22912 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
22912 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 22913 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
22913 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 22914 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
22914 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 22915 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
22915 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22916 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
22916 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 22917 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
22917 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 22918 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
22918 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 22919 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
22919 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 22920 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22920 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22921 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
22921 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 22922 |
// (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
22922 |
// (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 22923 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64, |
22923 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64, |
| 22924 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22924 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22925 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
22925 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
| 22926 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
22926 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 22927 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
22927 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 22928 |
GIR_EraseFromParent, /*InsnID*/0, |
22928 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22929 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22929 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22930 |
// GIR_Coverage, 1450, |
22930 |
// GIR_Coverage, 1450, |
| 22931 |
GIR_Done, |
22931 |
GIR_Done, |
| 22932 |
// Label 1350: @57296 |
22932 |
// Label 1350: @57296 |
| 22933 |
GIM_Try, /*On fail goto*//*Label 1351*/ 57374, // Rule ID 2204 // |
22933 |
GIM_Try, /*On fail goto*//*Label 1351*/ 57374, // Rule ID 2204 // |
| 22934 |
GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6, |
22934 |
GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6, |
| 22935 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
22935 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 22936 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22936 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22937 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
22937 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
| 22938 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
22938 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22939 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
22939 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 22940 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
22940 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 22941 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
22941 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 22942 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
22942 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22943 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
22943 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 22944 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
22944 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 22945 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
22945 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 22946 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
22946 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 22947 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22947 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22948 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
22948 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 22949 |
// (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
22949 |
// (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 22950 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM, |
22950 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM, |
| 22951 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22951 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22952 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
22952 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
| 22953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
22953 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 22954 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
22954 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 22955 |
GIR_EraseFromParent, /*InsnID*/0, |
22955 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22956 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22956 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22957 |
// GIR_Coverage, 2204, |
22957 |
// GIR_Coverage, 2204, |
| 22958 |
GIR_Done, |
22958 |
GIR_Done, |
| 22959 |
// Label 1351: @57374 |
22959 |
// Label 1351: @57374 |
| 22960 |
GIM_Try, /*On fail goto*//*Label 1352*/ 57452, // Rule ID 2383 // |
22960 |
GIM_Try, /*On fail goto*//*Label 1352*/ 57452, // Rule ID 2383 // |
| 22961 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
22961 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 22962 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
22962 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 22963 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22963 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22964 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
22964 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
| 22965 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
22965 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22966 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
22966 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 22967 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
22967 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 22968 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
22968 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 22969 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
22969 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 22970 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
22970 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22971 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
22971 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 22972 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
22972 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 22973 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
22973 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 22974 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
22974 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 22975 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
22975 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 22976 |
// (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
22976 |
// (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 22977 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32, |
22977 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32, |
| 22978 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
22978 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 22979 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr |
22979 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr |
| 22980 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
22980 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 22981 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
22981 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 22982 |
GIR_EraseFromParent, /*InsnID*/0, |
22982 |
GIR_EraseFromParent, /*InsnID*/0, |
| 22983 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
22983 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 22984 |
// GIR_Coverage, 2383, |
22984 |
// GIR_Coverage, 2383, |
| 22985 |
GIR_Done, |
22985 |
GIR_Done, |
| 22986 |
// Label 1352: @57452 |
22986 |
// Label 1352: @57452 |
| 22987 |
GIM_Try, /*On fail goto*//*Label 1353*/ 57530, // Rule ID 2384 // |
22987 |
GIM_Try, /*On fail goto*//*Label 1353*/ 57530, // Rule ID 2384 // |
| 22988 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
22988 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 22989 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
22989 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 22990 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
22990 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 22991 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
22991 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
| 22992 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
22992 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 22993 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
22993 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 22994 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
22994 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 22995 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
22995 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 22996 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
22996 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 22997 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
22997 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 22998 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
22998 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 22999 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
22999 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 23000 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
23000 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 23001 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
23001 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 23002 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
23002 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 23003 |
// (fneg:{ *:[f64] } (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
23003 |
// (fneg:{ *:[f64] } (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 23004 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64, |
23004 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64, |
| 23005 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
23005 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 23006 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr |
23006 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr |
| 23007 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
23007 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 23008 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
23008 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 23009 |
GIR_EraseFromParent, /*InsnID*/0, |
23009 |
GIR_EraseFromParent, /*InsnID*/0, |
| 23010 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23010 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23011 |
// GIR_Coverage, 2384, |
23011 |
// GIR_Coverage, 2384, |
| 23012 |
GIR_Done, |
23012 |
GIR_Done, |
| 23013 |
// Label 1353: @57530 |
23013 |
// Label 1353: @57530 |
| 23014 |
GIM_Try, /*On fail goto*//*Label 1354*/ 57608, // Rule ID 2469 // |
23014 |
GIM_Try, /*On fail goto*//*Label 1354*/ 57608, // Rule ID 2469 // |
| 23015 |
GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6, |
23015 |
GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6, |
| 23016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
23016 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 23017 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
23017 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23018 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
23018 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD, |
| 23019 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
23019 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 23020 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
23020 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 23021 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
23021 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 23022 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
23022 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 23023 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
23023 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 23024 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
23024 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 23025 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
23025 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 23026 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
23026 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 23027 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
23027 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 23028 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
23028 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 23029 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
23029 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 23030 |
// (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
23030 |
// (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 23031 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM, |
23031 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM, |
| 23032 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
23032 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 23033 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr |
23033 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr |
| 23034 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
23034 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 23035 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
23035 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 23036 |
GIR_EraseFromParent, /*InsnID*/0, |
23036 |
GIR_EraseFromParent, /*InsnID*/0, |
| 23037 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23037 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23038 |
// GIR_Coverage, 2469, |
23038 |
// GIR_Coverage, 2469, |
| 23039 |
GIR_Done, |
23039 |
GIR_Done, |
| 23040 |
// Label 1354: @57608 |
23040 |
// Label 1354: @57608 |
| 23041 |
GIM_Try, /*On fail goto*//*Label 1355*/ 57686, // Rule ID 1449 // |
23041 |
GIM_Try, /*On fail goto*//*Label 1355*/ 57686, // Rule ID 1449 // |
| 23042 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
23042 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 23043 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
23043 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 23044 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
23044 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23045 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
23045 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
| 23046 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
23046 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 23047 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
23047 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 23048 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
23048 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 23049 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
23049 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 23050 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
23050 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 23051 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
23051 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 23052 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
23052 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 23053 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
23053 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 23054 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
23054 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 23055 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
23055 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 23056 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
23056 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 23057 |
// (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
23057 |
// (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 23058 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32, |
23058 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32, |
| 23059 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
23059 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 23060 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
23060 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
| 23061 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
23061 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 23062 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
23062 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 23063 |
GIR_EraseFromParent, /*InsnID*/0, |
23063 |
GIR_EraseFromParent, /*InsnID*/0, |
| 23064 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23064 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23065 |
// GIR_Coverage, 1449, |
23065 |
// GIR_Coverage, 1449, |
| 23066 |
GIR_Done, |
23066 |
GIR_Done, |
| 23067 |
// Label 1355: @57686 |
23067 |
// Label 1355: @57686 |
| 23068 |
GIM_Try, /*On fail goto*//*Label 1356*/ 57764, // Rule ID 1451 // |
23068 |
GIM_Try, /*On fail goto*//*Label 1356*/ 57764, // Rule ID 1451 // |
| 23069 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
23069 |
GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 23070 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
23070 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 23071 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
23071 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23072 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
23072 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
| 23073 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
23073 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 23074 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
23074 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 23075 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
23075 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 23076 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
23076 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 23077 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
23077 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 23078 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
23078 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 23079 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
23079 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 23080 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
23080 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 23081 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
23081 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID, |
| 23082 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
23082 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 23083 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
23083 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 23084 |
// (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
23084 |
// (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) |
| 23085 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D64, |
23085 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D64, |
| 23086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
23086 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 23087 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
23087 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
| 23088 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
23088 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 23089 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
23089 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 23090 |
GIR_EraseFromParent, /*InsnID*/0, |
23090 |
GIR_EraseFromParent, /*InsnID*/0, |
| 23091 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23091 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23092 |
// GIR_Coverage, 1451, |
23092 |
// GIR_Coverage, 1451, |
| 23093 |
GIR_Done, |
23093 |
GIR_Done, |
| 23094 |
// Label 1356: @57764 |
23094 |
// Label 1356: @57764 |
| 23095 |
GIM_Try, /*On fail goto*//*Label 1357*/ 57842, // Rule ID 2205 // |
23095 |
GIM_Try, /*On fail goto*//*Label 1357*/ 57842, // Rule ID 2205 // |
| 23096 |
GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6, |
23096 |
GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6, |
| 23097 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
23097 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 23098 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
23098 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23099 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
23099 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB, |
| 23100 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
23100 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 23101 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
23101 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 23102 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
23102 |
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 23103 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
23103 |
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL, |
| 23104 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
23104 |
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 23105 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
23105 |
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 23106 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
23106 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 23107 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
23107 |
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 23108 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
23108 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID, |
| 23109 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
23109 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 23110 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
23110 |
GIM_CheckIsSafeToFold, /*InsnID*/2, |
| 23111 |
// (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
23111 |
// (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) |
| 23112 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32_MM, |
23112 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32_MM, |
| 23113 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
23113 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd |
| 23114 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
23114 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr |
| 23115 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
23115 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs |
| 23116 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
23116 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft |
| 23117 |
GIR_EraseFromParent, /*InsnID*/0, |
23117 |
GIR_EraseFromParent, /*InsnID*/0, |
| 23118 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23118 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23119 |
// GIR_Coverage, 2205, |
23119 |
// GIR_Coverage, 2205, |
| 23120 |
GIR_Done, |
23120 |
GIR_Done, |
| 23121 |
// Label 1357: @57842 |
23121 |
// Label 1357: @57842 |
| 23122 |
GIM_Try, /*On fail goto*//*Label 1358*/ 57861, // Rule ID 124 // |
23122 |
GIM_Try, /*On fail goto*//*Label 1358*/ 57861, // Rule ID 124 // |
| 23123 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
23123 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
| 23124 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
23124 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 23125 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
23125 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 23126 |
// (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) |
23126 |
// (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) |
| 23127 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32, |
23127 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32, |
| 23128 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23128 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23129 |
// GIR_Coverage, 124, |
23129 |
// GIR_Coverage, 124, |
| 23130 |
GIR_Done, |
23130 |
GIR_Done, |
| 23131 |
// Label 1358: @57861 |
23131 |
// Label 1358: @57861 |
| 23132 |
GIM_Try, /*On fail goto*//*Label 1359*/ 57880, // Rule ID 125 // |
23132 |
GIM_Try, /*On fail goto*//*Label 1359*/ 57880, // Rule ID 125 // |
| 23133 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
23133 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
| 23134 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
23134 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 23135 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
23135 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 23136 |
// (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) |
23136 |
// (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) |
| 23137 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64, |
23137 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64, |
| 23138 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23138 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23139 |
// GIR_Coverage, 125, |
23139 |
// GIR_Coverage, 125, |
| 23140 |
GIR_Done, |
23140 |
GIR_Done, |
| 23141 |
// Label 1359: @57880 |
23141 |
// Label 1359: @57880 |
| 23142 |
GIM_Try, /*On fail goto*//*Label 1360*/ 57899, // Rule ID 1142 // |
23142 |
GIM_Try, /*On fail goto*//*Label 1360*/ 57899, // Rule ID 1142 // |
| 23143 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
23143 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
| 23144 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
23144 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 23145 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
23145 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 23146 |
// (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) |
23146 |
// (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) |
| 23147 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32_MM, |
23147 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32_MM, |
| 23148 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23148 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23149 |
// GIR_Coverage, 1142, |
23149 |
// GIR_Coverage, 1142, |
| 23150 |
GIR_Done, |
23150 |
GIR_Done, |
| 23151 |
// Label 1360: @57899 |
23151 |
// Label 1360: @57899 |
| 23152 |
GIM_Try, /*On fail goto*//*Label 1361*/ 57918, // Rule ID 1143 // |
23152 |
GIM_Try, /*On fail goto*//*Label 1361*/ 57918, // Rule ID 1143 // |
| 23153 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
23153 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
| 23154 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
23154 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 23155 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
23155 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 23156 |
// (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) |
23156 |
// (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) |
| 23157 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64_MM, |
23157 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64_MM, |
| 23158 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23158 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23159 |
// GIR_Coverage, 1143, |
23159 |
// GIR_Coverage, 1143, |
| 23160 |
GIR_Done, |
23160 |
GIR_Done, |
| 23161 |
// Label 1361: @57918 |
23161 |
// Label 1361: @57918 |
| 23162 |
GIM_Reject, |
23162 |
GIM_Reject, |
| 23163 |
// Label 1348: @57919 |
23163 |
// Label 1348: @57919 |
| 23164 |
GIM_Reject, |
23164 |
GIM_Reject, |
| 23165 |
// Label 1337: @57920 |
23165 |
// Label 1337: @57920 |
| 23166 |
GIM_Reject, |
23166 |
GIM_Reject, |
| 23167 |
// Label 40: @57921 |
23167 |
// Label 40: @57921 |
| 23168 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1364*/ 58069, |
23168 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1364*/ 58069, |
| 23169 |
/*GILLT_s32*//*Label 1362*/ 57929, |
23169 |
/*GILLT_s32*//*Label 1362*/ 57929, |
| 23170 |
/*GILLT_s64*//*Label 1363*/ 57953, |
23170 |
/*GILLT_s64*//*Label 1363*/ 57953, |
| 23171 |
// Label 1362: @57929 |
23171 |
// Label 1362: @57929 |
| 23172 |
GIM_Try, /*On fail goto*//*Label 1365*/ 57952, // Rule ID 1044 // |
23172 |
GIM_Try, /*On fail goto*//*Label 1365*/ 57952, // Rule ID 1044 // |
| 23173 |
GIM_CheckFeatures, GIFBS_HasMSA, |
23173 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 23174 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
23174 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 23175 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
23175 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 23176 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID, |
23176 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID, |
| 23177 |
// (fpextend:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) |
23177 |
// (fpextend:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) |
| 23178 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_W_PSEUDO, |
23178 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_W_PSEUDO, |
| 23179 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23179 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23180 |
// GIR_Coverage, 1044, |
23180 |
// GIR_Coverage, 1044, |
| 23181 |
GIR_Done, |
23181 |
GIR_Done, |
| 23182 |
// Label 1365: @57952 |
23182 |
// Label 1365: @57952 |
| 23183 |
GIM_Reject, |
23183 |
GIM_Reject, |
| 23184 |
// Label 1363: @57953 |
23184 |
// Label 1363: @57953 |
| 23185 |
GIM_Try, /*On fail goto*//*Label 1366*/ 57976, // Rule ID 1046 // |
23185 |
GIM_Try, /*On fail goto*//*Label 1366*/ 57976, // Rule ID 1046 // |
| 23186 |
GIM_CheckFeatures, GIFBS_HasMSA, |
23186 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 23187 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
23187 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, |
| 23188 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
23188 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 23189 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID, |
23189 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID, |
| 23190 |
// (fpextend:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws) |
23190 |
// (fpextend:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws) |
| 23191 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_D_PSEUDO, |
23191 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_D_PSEUDO, |
| 23192 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23192 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23193 |
// GIR_Coverage, 1046, |
23193 |
// GIR_Coverage, 1046, |
| 23194 |
GIR_Done, |
23194 |
GIR_Done, |
| 23195 |
// Label 1366: @57976 |
23195 |
// Label 1366: @57976 |
| 23196 |
GIM_Try, /*On fail goto*//*Label 1367*/ 57999, // Rule ID 1435 // |
23196 |
GIM_Try, /*On fail goto*//*Label 1367*/ 57999, // Rule ID 1435 // |
| 23197 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips, |
23197 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips, |
| 23198 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
23198 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 23199 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
23199 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 23200 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
23200 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 23201 |
// (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) |
23201 |
// (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) |
| 23202 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S, |
23202 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S, |
| 23203 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23203 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23204 |
// GIR_Coverage, 1435, |
23204 |
// GIR_Coverage, 1435, |
| 23205 |
GIR_Done, |
23205 |
GIR_Done, |
| 23206 |
// Label 1367: @57999 |
23206 |
// Label 1367: @57999 |
| 23207 |
GIM_Try, /*On fail goto*//*Label 1368*/ 58022, // Rule ID 1445 // |
23207 |
GIM_Try, /*On fail goto*//*Label 1368*/ 58022, // Rule ID 1445 // |
| 23208 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips, |
23208 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips, |
| 23209 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
23209 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 23210 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
23210 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 23211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
23211 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 23212 |
// (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) |
23212 |
// (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) |
| 23213 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S, |
23213 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S, |
| 23214 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23214 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23215 |
// GIR_Coverage, 1445, |
23215 |
// GIR_Coverage, 1445, |
| 23216 |
GIR_Done, |
23216 |
GIR_Done, |
| 23217 |
// Label 1368: @58022 |
23217 |
// Label 1368: @58022 |
| 23218 |
GIM_Try, /*On fail goto*//*Label 1369*/ 58045, // Rule ID 2216 // |
23218 |
GIM_Try, /*On fail goto*//*Label 1369*/ 58045, // Rule ID 2216 // |
| 23219 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit, |
23219 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit, |
| 23220 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
23220 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 23221 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
23221 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 23222 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
23222 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 23223 |
// (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) |
23223 |
// (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) |
| 23224 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S_MM, |
23224 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S_MM, |
| 23225 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23225 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23226 |
// GIR_Coverage, 2216, |
23226 |
// GIR_Coverage, 2216, |
| 23227 |
GIR_Done, |
23227 |
GIR_Done, |
| 23228 |
// Label 1369: @58045 |
23228 |
// Label 1369: @58045 |
| 23229 |
GIM_Try, /*On fail goto*//*Label 1370*/ 58068, // Rule ID 2218 // |
23229 |
GIM_Try, /*On fail goto*//*Label 1370*/ 58068, // Rule ID 2218 // |
| 23230 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit, |
23230 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit, |
| 23231 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
23231 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 23232 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
23232 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 23233 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
23233 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 23234 |
// (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) |
23234 |
// (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) |
| 23235 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S_MM, |
23235 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S_MM, |
| 23236 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23236 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23237 |
// GIR_Coverage, 2218, |
23237 |
// GIR_Coverage, 2218, |
| 23238 |
GIR_Done, |
23238 |
GIR_Done, |
| 23239 |
// Label 1370: @58068 |
23239 |
// Label 1370: @58068 |
| 23240 |
GIM_Reject, |
23240 |
GIM_Reject, |
| 23241 |
// Label 1364: @58069 |
23241 |
// Label 1364: @58069 |
| 23242 |
GIM_Reject, |
23242 |
GIM_Reject, |
| 23243 |
// Label 41: @58070 |
23243 |
// Label 41: @58070 |
| 23244 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 1373*/ 58197, |
23244 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 1373*/ 58197, |
| 23245 |
/*GILLT_s16*//*Label 1371*/ 58078, |
23245 |
/*GILLT_s16*//*Label 1371*/ 58078, |
| 23246 |
/*GILLT_s32*//*Label 1372*/ 58125, |
23246 |
/*GILLT_s32*//*Label 1372*/ 58125, |
| 23247 |
// Label 1371: @58078 |
23247 |
// Label 1371: @58078 |
| 23248 |
GIM_Try, /*On fail goto*//*Label 1374*/ 58101, // Rule ID 1045 // |
23248 |
GIM_Try, /*On fail goto*//*Label 1374*/ 58101, // Rule ID 1045 // |
| 23249 |
GIM_CheckFeatures, GIFBS_HasMSA, |
23249 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 23250 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
23250 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 23251 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID, |
23251 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID, |
| 23252 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
23252 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 23253 |
// (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) => (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) |
23253 |
// (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) => (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) |
| 23254 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_W_PSEUDO, |
23254 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_W_PSEUDO, |
| 23255 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23255 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23256 |
// GIR_Coverage, 1045, |
23256 |
// GIR_Coverage, 1045, |
| 23257 |
GIR_Done, |
23257 |
GIR_Done, |
| 23258 |
// Label 1374: @58101 |
23258 |
// Label 1374: @58101 |
| 23259 |
GIM_Try, /*On fail goto*//*Label 1375*/ 58124, // Rule ID 1047 // |
23259 |
GIM_Try, /*On fail goto*//*Label 1375*/ 58124, // Rule ID 1047 // |
| 23260 |
GIM_CheckFeatures, GIFBS_HasMSA, |
23260 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 23261 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
23261 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 23262 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID, |
23262 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID, |
| 23263 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
23263 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 23264 |
// (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) => (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) |
23264 |
// (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) => (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) |
| 23265 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_D_PSEUDO, |
23265 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_D_PSEUDO, |
| 23266 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23266 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23267 |
// GIR_Coverage, 1047, |
23267 |
// GIR_Coverage, 1047, |
| 23268 |
GIR_Done, |
23268 |
GIR_Done, |
| 23269 |
// Label 1375: @58124 |
23269 |
// Label 1375: @58124 |
| 23270 |
GIM_Reject, |
23270 |
GIM_Reject, |
| 23271 |
// Label 1372: @58125 |
23271 |
// Label 1372: @58125 |
| 23272 |
GIM_Try, /*On fail goto*//*Label 1376*/ 58196, |
23272 |
GIM_Try, /*On fail goto*//*Label 1376*/ 58196, |
| 23273 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
23273 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 23274 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
23274 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 23275 |
GIM_Try, /*On fail goto*//*Label 1377*/ 58150, // Rule ID 1434 // |
23275 |
GIM_Try, /*On fail goto*//*Label 1377*/ 58150, // Rule ID 1434 // |
| 23276 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips, |
23276 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips, |
| 23277 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
23277 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 23278 |
// (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) |
23278 |
// (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) |
| 23279 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32, |
23279 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32, |
| 23280 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23280 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23281 |
// GIR_Coverage, 1434, |
23281 |
// GIR_Coverage, 1434, |
| 23282 |
GIR_Done, |
23282 |
GIR_Done, |
| 23283 |
// Label 1377: @58150 |
23283 |
// Label 1377: @58150 |
| 23284 |
GIM_Try, /*On fail goto*//*Label 1378*/ 58165, // Rule ID 1444 // |
23284 |
GIM_Try, /*On fail goto*//*Label 1378*/ 58165, // Rule ID 1444 // |
| 23285 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips, |
23285 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips, |
| 23286 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
23286 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 23287 |
// (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) |
23287 |
// (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) |
| 23288 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64, |
23288 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64, |
| 23289 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23289 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23290 |
// GIR_Coverage, 1444, |
23290 |
// GIR_Coverage, 1444, |
| 23291 |
GIR_Done, |
23291 |
GIR_Done, |
| 23292 |
// Label 1378: @58165 |
23292 |
// Label 1378: @58165 |
| 23293 |
GIM_Try, /*On fail goto*//*Label 1379*/ 58180, // Rule ID 2215 // |
23293 |
GIM_Try, /*On fail goto*//*Label 1379*/ 58180, // Rule ID 2215 // |
| 23294 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit, |
23294 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit, |
| 23295 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
23295 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 23296 |
// (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) |
23296 |
// (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) |
| 23297 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64_MM, |
23297 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64_MM, |
| 23298 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23298 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23299 |
// GIR_Coverage, 2215, |
23299 |
// GIR_Coverage, 2215, |
| 23300 |
GIR_Done, |
23300 |
GIR_Done, |
| 23301 |
// Label 1379: @58180 |
23301 |
// Label 1379: @58180 |
| 23302 |
GIM_Try, /*On fail goto*//*Label 1380*/ 58195, // Rule ID 2217 // |
23302 |
GIM_Try, /*On fail goto*//*Label 1380*/ 58195, // Rule ID 2217 // |
| 23303 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit, |
23303 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit, |
| 23304 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
23304 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 23305 |
// (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) |
23305 |
// (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) |
| 23306 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32_MM, |
23306 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32_MM, |
| 23307 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23307 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23308 |
// GIR_Coverage, 2217, |
23308 |
// GIR_Coverage, 2217, |
| 23309 |
GIR_Done, |
23309 |
GIR_Done, |
| 23310 |
// Label 1380: @58195 |
23310 |
// Label 1380: @58195 |
| 23311 |
GIM_Reject, |
23311 |
GIM_Reject, |
| 23312 |
// Label 1376: @58196 |
23312 |
// Label 1376: @58196 |
| 23313 |
GIM_Reject, |
23313 |
GIM_Reject, |
| 23314 |
// Label 1373: @58197 |
23314 |
// Label 1373: @58197 |
| 23315 |
GIM_Reject, |
23315 |
GIM_Reject, |
| 23316 |
// Label 42: @58198 |
23316 |
// Label 42: @58198 |
| 23317 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1383*/ 58255, |
23317 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1383*/ 58255, |
| 23318 |
/*GILLT_v2s64*//*Label 1381*/ 58207, 0, |
23318 |
/*GILLT_v2s64*//*Label 1381*/ 58207, 0, |
| 23319 |
/*GILLT_v4s32*//*Label 1382*/ 58231, |
23319 |
/*GILLT_v4s32*//*Label 1382*/ 58231, |
| 23320 |
// Label 1381: @58207 |
23320 |
// Label 1381: @58207 |
| 23321 |
GIM_Try, /*On fail goto*//*Label 1384*/ 58230, // Rule ID 765 // |
23321 |
GIM_Try, /*On fail goto*//*Label 1384*/ 58230, // Rule ID 765 // |
| 23322 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23322 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23323 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
23323 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 23324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
23324 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 23325 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
23325 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 23326 |
// (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
23326 |
// (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
| 23327 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_D, |
23327 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_D, |
| 23328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23329 |
// GIR_Coverage, 765, |
23329 |
// GIR_Coverage, 765, |
| 23330 |
GIR_Done, |
23330 |
GIR_Done, |
| 23331 |
// Label 1384: @58230 |
23331 |
// Label 1384: @58230 |
| 23332 |
GIM_Reject, |
23332 |
GIM_Reject, |
| 23333 |
// Label 1382: @58231 |
23333 |
// Label 1382: @58231 |
| 23334 |
GIM_Try, /*On fail goto*//*Label 1385*/ 58254, // Rule ID 764 // |
23334 |
GIM_Try, /*On fail goto*//*Label 1385*/ 58254, // Rule ID 764 // |
| 23335 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23335 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23336 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
23336 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 23337 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
23337 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 23338 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
23338 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 23339 |
// (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
23339 |
// (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
| 23340 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_W, |
23340 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_W, |
| 23341 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23341 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23342 |
// GIR_Coverage, 764, |
23342 |
// GIR_Coverage, 764, |
| 23343 |
GIR_Done, |
23343 |
GIR_Done, |
| 23344 |
// Label 1385: @58254 |
23344 |
// Label 1385: @58254 |
| 23345 |
GIM_Reject, |
23345 |
GIM_Reject, |
| 23346 |
// Label 1383: @58255 |
23346 |
// Label 1383: @58255 |
| 23347 |
GIM_Reject, |
23347 |
GIM_Reject, |
| 23348 |
// Label 43: @58256 |
23348 |
// Label 43: @58256 |
| 23349 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1388*/ 58313, |
23349 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1388*/ 58313, |
| 23350 |
/*GILLT_v2s64*//*Label 1386*/ 58265, 0, |
23350 |
/*GILLT_v2s64*//*Label 1386*/ 58265, 0, |
| 23351 |
/*GILLT_v4s32*//*Label 1387*/ 58289, |
23351 |
/*GILLT_v4s32*//*Label 1387*/ 58289, |
| 23352 |
// Label 1386: @58265 |
23352 |
// Label 1386: @58265 |
| 23353 |
GIM_Try, /*On fail goto*//*Label 1389*/ 58288, // Rule ID 767 // |
23353 |
GIM_Try, /*On fail goto*//*Label 1389*/ 58288, // Rule ID 767 // |
| 23354 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23354 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23355 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
23355 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 23356 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
23356 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 23357 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
23357 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 23358 |
// (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
23358 |
// (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
| 23359 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_D, |
23359 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_D, |
| 23360 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23360 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23361 |
// GIR_Coverage, 767, |
23361 |
// GIR_Coverage, 767, |
| 23362 |
GIR_Done, |
23362 |
GIR_Done, |
| 23363 |
// Label 1389: @58288 |
23363 |
// Label 1389: @58288 |
| 23364 |
GIM_Reject, |
23364 |
GIM_Reject, |
| 23365 |
// Label 1387: @58289 |
23365 |
// Label 1387: @58289 |
| 23366 |
GIM_Try, /*On fail goto*//*Label 1390*/ 58312, // Rule ID 766 // |
23366 |
GIM_Try, /*On fail goto*//*Label 1390*/ 58312, // Rule ID 766 // |
| 23367 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23367 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23368 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
23368 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 23369 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
23369 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 23370 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
23370 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 23371 |
// (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
23371 |
// (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
| 23372 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_W, |
23372 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_W, |
| 23373 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23373 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23374 |
// GIR_Coverage, 766, |
23374 |
// GIR_Coverage, 766, |
| 23375 |
GIR_Done, |
23375 |
GIR_Done, |
| 23376 |
// Label 1390: @58312 |
23376 |
// Label 1390: @58312 |
| 23377 |
GIM_Reject, |
23377 |
GIM_Reject, |
| 23378 |
// Label 1388: @58313 |
23378 |
// Label 1388: @58313 |
| 23379 |
GIM_Reject, |
23379 |
GIM_Reject, |
| 23380 |
// Label 44: @58314 |
23380 |
// Label 44: @58314 |
| 23381 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1395*/ 58521, |
23381 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1395*/ 58521, |
| 23382 |
/*GILLT_s32*//*Label 1391*/ 58326, |
23382 |
/*GILLT_s32*//*Label 1391*/ 58326, |
| 23383 |
/*GILLT_s64*//*Label 1392*/ 58403, 0, |
23383 |
/*GILLT_s64*//*Label 1392*/ 58403, 0, |
| 23384 |
/*GILLT_v2s64*//*Label 1393*/ 58473, 0, |
23384 |
/*GILLT_v2s64*//*Label 1393*/ 58473, 0, |
| 23385 |
/*GILLT_v4s32*//*Label 1394*/ 58497, |
23385 |
/*GILLT_v4s32*//*Label 1394*/ 58497, |
| 23386 |
// Label 1391: @58326 |
23386 |
// Label 1391: @58326 |
| 23387 |
GIM_Try, /*On fail goto*//*Label 1396*/ 58347, // Rule ID 1429 // |
23387 |
GIM_Try, /*On fail goto*//*Label 1396*/ 58347, // Rule ID 1429 // |
| 23388 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
23388 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 23389 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
23389 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 23390 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
23390 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 23391 |
// (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) |
23391 |
// (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) |
| 23392 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_S_W, |
23392 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_S_W, |
| 23393 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23393 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23394 |
// GIR_Coverage, 1429, |
23394 |
// GIR_Coverage, 1429, |
| 23395 |
GIR_Done, |
23395 |
GIR_Done, |
| 23396 |
// Label 1396: @58347 |
23396 |
// Label 1396: @58347 |
| 23397 |
GIM_Try, /*On fail goto*//*Label 1397*/ 58402, // Rule ID 1439 // |
23397 |
GIM_Try, /*On fail goto*//*Label 1397*/ 58402, // Rule ID 1439 // |
| 23398 |
GIM_CheckFeatures, GIFBS_IsFP64bit, |
23398 |
GIM_CheckFeatures, GIFBS_IsFP64bit, |
| 23399 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
23399 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 23400 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
23400 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 23401 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
23401 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 23402 |
// (sint_to_fp:{ *:[f32] } GPR64Opnd:{ *:[i64] }:$src) => (EXTRACT_SUBREG:{ *:[f32] } (PseudoCVT_S_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src), sub_lo:{ *:[i32] }) |
23402 |
// (sint_to_fp:{ *:[f32] } GPR64Opnd:{ *:[i64] }:$src) => (EXTRACT_SUBREG:{ *:[f32] } (PseudoCVT_S_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src), sub_lo:{ *:[i32] }) |
| 23403 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
23403 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 23404 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::PseudoCVT_S_L, |
23404 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::PseudoCVT_S_L, |
| 23405 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
23405 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 23406 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
23406 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 23407 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
23407 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23408 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
23408 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, |
| 23409 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
23409 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst |
| 23410 |
GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, Mips::sub_lo, |
23410 |
GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, Mips::sub_lo, |
| 23411 |
GIR_EraseFromParent, /*InsnID*/0, |
23411 |
GIR_EraseFromParent, /*InsnID*/0, |
| 23412 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::FGR32RegClassID, |
23412 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Mips::FGR32RegClassID, |
| 23413 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::FGR64RegClassID, |
23413 |
GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Mips::FGR64RegClassID, |
| 23414 |
// GIR_Coverage, 1439, |
23414 |
// GIR_Coverage, 1439, |
| 23415 |
GIR_Done, |
23415 |
GIR_Done, |
| 23416 |
// Label 1397: @58402 |
23416 |
// Label 1397: @58402 |
| 23417 |
GIM_Reject, |
23417 |
GIM_Reject, |
| 23418 |
// Label 1392: @58403 |
23418 |
// Label 1392: @58403 |
| 23419 |
GIM_Try, /*On fail goto*//*Label 1398*/ 58426, // Rule ID 1432 // |
23419 |
GIM_Try, /*On fail goto*//*Label 1398*/ 58426, // Rule ID 1432 // |
| 23420 |
GIM_CheckFeatures, GIFBS_NotFP64bit, |
23420 |
GIM_CheckFeatures, GIFBS_NotFP64bit, |
| 23421 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
23421 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 23422 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
23422 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 23423 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
23423 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 23424 |
// (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) |
23424 |
// (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) |
| 23425 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D32_W, |
23425 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D32_W, |
| 23426 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23426 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23427 |
// GIR_Coverage, 1432, |
23427 |
// GIR_Coverage, 1432, |
| 23428 |
GIR_Done, |
23428 |
GIR_Done, |
| 23429 |
// Label 1398: @58426 |
23429 |
// Label 1398: @58426 |
| 23430 |
GIM_Try, /*On fail goto*//*Label 1399*/ 58449, // Rule ID 1438 // |
23430 |
GIM_Try, /*On fail goto*//*Label 1399*/ 58449, // Rule ID 1438 // |
| 23431 |
GIM_CheckFeatures, GIFBS_IsFP64bit, |
23431 |
GIM_CheckFeatures, GIFBS_IsFP64bit, |
| 23432 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
23432 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 23433 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
23433 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 23434 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
23434 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 23435 |
// (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) |
23435 |
// (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) |
| 23436 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_W, |
23436 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_W, |
| 23437 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23437 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23438 |
// GIR_Coverage, 1438, |
23438 |
// GIR_Coverage, 1438, |
| 23439 |
GIR_Done, |
23439 |
GIR_Done, |
| 23440 |
// Label 1399: @58449 |
23440 |
// Label 1399: @58449 |
| 23441 |
GIM_Try, /*On fail goto*//*Label 1400*/ 58472, // Rule ID 1440 // |
23441 |
GIM_Try, /*On fail goto*//*Label 1400*/ 58472, // Rule ID 1440 // |
| 23442 |
GIM_CheckFeatures, GIFBS_IsFP64bit, |
23442 |
GIM_CheckFeatures, GIFBS_IsFP64bit, |
| 23443 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
23443 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 23444 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
23444 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 23445 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
23445 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 23446 |
// (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) => (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) |
23446 |
// (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) => (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) |
| 23447 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_L, |
23447 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_L, |
| 23448 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23448 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23449 |
// GIR_Coverage, 1440, |
23449 |
// GIR_Coverage, 1440, |
| 23450 |
GIR_Done, |
23450 |
GIR_Done, |
| 23451 |
// Label 1400: @58472 |
23451 |
// Label 1400: @58472 |
| 23452 |
GIM_Reject, |
23452 |
GIM_Reject, |
| 23453 |
// Label 1393: @58473 |
23453 |
// Label 1393: @58473 |
| 23454 |
GIM_Try, /*On fail goto*//*Label 1401*/ 58496, // Rule ID 697 // |
23454 |
GIM_Try, /*On fail goto*//*Label 1401*/ 58496, // Rule ID 697 // |
| 23455 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23455 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23456 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
23456 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 23457 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
23457 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 23458 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
23458 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 23459 |
// (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) |
23459 |
// (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) |
| 23460 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_D, |
23460 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_D, |
| 23461 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23461 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23462 |
// GIR_Coverage, 697, |
23462 |
// GIR_Coverage, 697, |
| 23463 |
GIR_Done, |
23463 |
GIR_Done, |
| 23464 |
// Label 1401: @58496 |
23464 |
// Label 1401: @58496 |
| 23465 |
GIM_Reject, |
23465 |
GIM_Reject, |
| 23466 |
// Label 1394: @58497 |
23466 |
// Label 1394: @58497 |
| 23467 |
GIM_Try, /*On fail goto*//*Label 1402*/ 58520, // Rule ID 696 // |
23467 |
GIM_Try, /*On fail goto*//*Label 1402*/ 58520, // Rule ID 696 // |
| 23468 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23468 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23469 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
23469 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 23470 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
23470 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 23471 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
23471 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 23472 |
// (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
23472 |
// (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
| 23473 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_W, |
23473 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_W, |
| 23474 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23474 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23475 |
// GIR_Coverage, 696, |
23475 |
// GIR_Coverage, 696, |
| 23476 |
GIR_Done, |
23476 |
GIR_Done, |
| 23477 |
// Label 1402: @58520 |
23477 |
// Label 1402: @58520 |
| 23478 |
GIM_Reject, |
23478 |
GIM_Reject, |
| 23479 |
// Label 1395: @58521 |
23479 |
// Label 1395: @58521 |
| 23480 |
GIM_Reject, |
23480 |
GIM_Reject, |
| 23481 |
// Label 45: @58522 |
23481 |
// Label 45: @58522 |
| 23482 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1405*/ 58579, |
23482 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1405*/ 58579, |
| 23483 |
/*GILLT_v2s64*//*Label 1403*/ 58531, 0, |
23483 |
/*GILLT_v2s64*//*Label 1403*/ 58531, 0, |
| 23484 |
/*GILLT_v4s32*//*Label 1404*/ 58555, |
23484 |
/*GILLT_v4s32*//*Label 1404*/ 58555, |
| 23485 |
// Label 1403: @58531 |
23485 |
// Label 1403: @58531 |
| 23486 |
GIM_Try, /*On fail goto*//*Label 1406*/ 58554, // Rule ID 699 // |
23486 |
GIM_Try, /*On fail goto*//*Label 1406*/ 58554, // Rule ID 699 // |
| 23487 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23487 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23488 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
23488 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 23489 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
23489 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 23490 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
23490 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 23491 |
// (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) |
23491 |
// (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) |
| 23492 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_D, |
23492 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_D, |
| 23493 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23493 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23494 |
// GIR_Coverage, 699, |
23494 |
// GIR_Coverage, 699, |
| 23495 |
GIR_Done, |
23495 |
GIR_Done, |
| 23496 |
// Label 1406: @58554 |
23496 |
// Label 1406: @58554 |
| 23497 |
GIM_Reject, |
23497 |
GIM_Reject, |
| 23498 |
// Label 1404: @58555 |
23498 |
// Label 1404: @58555 |
| 23499 |
GIM_Try, /*On fail goto*//*Label 1407*/ 58578, // Rule ID 698 // |
23499 |
GIM_Try, /*On fail goto*//*Label 1407*/ 58578, // Rule ID 698 // |
| 23500 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23500 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23501 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
23501 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 23502 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
23502 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 23503 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
23503 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 23504 |
// (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
23504 |
// (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
| 23505 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_W, |
23505 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_W, |
| 23506 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23506 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23507 |
// GIR_Coverage, 698, |
23507 |
// GIR_Coverage, 698, |
| 23508 |
GIR_Done, |
23508 |
GIR_Done, |
| 23509 |
// Label 1407: @58578 |
23509 |
// Label 1407: @58578 |
| 23510 |
GIM_Reject, |
23510 |
GIM_Reject, |
| 23511 |
// Label 1405: @58579 |
23511 |
// Label 1405: @58579 |
| 23512 |
GIM_Reject, |
23512 |
GIM_Reject, |
| 23513 |
// Label 46: @58580 |
23513 |
// Label 46: @58580 |
| 23514 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1412*/ 58762, |
23514 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1412*/ 58762, |
| 23515 |
/*GILLT_s32*//*Label 1408*/ 58592, |
23515 |
/*GILLT_s32*//*Label 1408*/ 58592, |
| 23516 |
/*GILLT_s64*//*Label 1409*/ 58630, 0, |
23516 |
/*GILLT_s64*//*Label 1409*/ 58630, 0, |
| 23517 |
/*GILLT_v2s64*//*Label 1410*/ 58714, 0, |
23517 |
/*GILLT_v2s64*//*Label 1410*/ 58714, 0, |
| 23518 |
/*GILLT_v4s32*//*Label 1411*/ 58738, |
23518 |
/*GILLT_v4s32*//*Label 1411*/ 58738, |
| 23519 |
// Label 1408: @58592 |
23519 |
// Label 1408: @58592 |
| 23520 |
GIM_Try, /*On fail goto*//*Label 1413*/ 58629, |
23520 |
GIM_Try, /*On fail goto*//*Label 1413*/ 58629, |
| 23521 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
23521 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 23522 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
23522 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 23523 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
23523 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 23524 |
GIM_Try, /*On fail goto*//*Label 1414*/ 58617, // Rule ID 120 // |
23524 |
GIM_Try, /*On fail goto*//*Label 1414*/ 58617, // Rule ID 120 // |
| 23525 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs, |
23525 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs, |
| 23526 |
// (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FABS_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
23526 |
// (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FABS_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
| 23527 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_S, |
23527 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_S, |
| 23528 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23528 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23529 |
// GIR_Coverage, 120, |
23529 |
// GIR_Coverage, 120, |
| 23530 |
GIR_Done, |
23530 |
GIR_Done, |
| 23531 |
// Label 1414: @58617 |
23531 |
// Label 1414: @58617 |
| 23532 |
GIM_Try, /*On fail goto*//*Label 1415*/ 58628, // Rule ID 1140 // |
23532 |
GIM_Try, /*On fail goto*//*Label 1415*/ 58628, // Rule ID 1140 // |
| 23533 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_UseAbs, |
23533 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_UseAbs, |
| 23534 |
// (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FABS_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
23534 |
// (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FABS_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
| 23535 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_S_MM, |
23535 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_S_MM, |
| 23536 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23536 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23537 |
// GIR_Coverage, 1140, |
23537 |
// GIR_Coverage, 1140, |
| 23538 |
GIR_Done, |
23538 |
GIR_Done, |
| 23539 |
// Label 1415: @58628 |
23539 |
// Label 1415: @58628 |
| 23540 |
GIM_Reject, |
23540 |
GIM_Reject, |
| 23541 |
// Label 1413: @58629 |
23541 |
// Label 1413: @58629 |
| 23542 |
GIM_Reject, |
23542 |
GIM_Reject, |
| 23543 |
// Label 1409: @58630 |
23543 |
// Label 1409: @58630 |
| 23544 |
GIM_Try, /*On fail goto*//*Label 1416*/ 58713, |
23544 |
GIM_Try, /*On fail goto*//*Label 1416*/ 58713, |
| 23545 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
23545 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 23546 |
GIM_Try, /*On fail goto*//*Label 1417*/ 58655, // Rule ID 121 // |
23546 |
GIM_Try, /*On fail goto*//*Label 1417*/ 58655, // Rule ID 121 // |
| 23547 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs, |
23547 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs, |
| 23548 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
23548 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 23549 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
23549 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 23550 |
// (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) |
23550 |
// (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) |
| 23551 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D32, |
23551 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D32, |
| 23552 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23552 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23553 |
// GIR_Coverage, 121, |
23553 |
// GIR_Coverage, 121, |
| 23554 |
GIR_Done, |
23554 |
GIR_Done, |
| 23555 |
// Label 1417: @58655 |
23555 |
// Label 1417: @58655 |
| 23556 |
GIM_Try, /*On fail goto*//*Label 1418*/ 58674, // Rule ID 122 // |
23556 |
GIM_Try, /*On fail goto*//*Label 1418*/ 58674, // Rule ID 122 // |
| 23557 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs, |
23557 |
GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs, |
| 23558 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
23558 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 23559 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
23559 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 23560 |
// (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) |
23560 |
// (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) |
| 23561 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D64, |
23561 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D64, |
| 23562 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23562 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23563 |
// GIR_Coverage, 122, |
23563 |
// GIR_Coverage, 122, |
| 23564 |
GIR_Done, |
23564 |
GIR_Done, |
| 23565 |
// Label 1418: @58674 |
23565 |
// Label 1418: @58674 |
| 23566 |
GIM_Try, /*On fail goto*//*Label 1419*/ 58693, // Rule ID 1138 // |
23566 |
GIM_Try, /*On fail goto*//*Label 1419*/ 58693, // Rule ID 1138 // |
| 23567 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
23567 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
| 23568 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
23568 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 23569 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
23569 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 23570 |
// (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) |
23570 |
// (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FABS_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) |
| 23571 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D32_MM, |
23571 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D32_MM, |
| 23572 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23572 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23573 |
// GIR_Coverage, 1138, |
23573 |
// GIR_Coverage, 1138, |
| 23574 |
GIR_Done, |
23574 |
GIR_Done, |
| 23575 |
// Label 1419: @58693 |
23575 |
// Label 1419: @58693 |
| 23576 |
GIM_Try, /*On fail goto*//*Label 1420*/ 58712, // Rule ID 1139 // |
23576 |
GIM_Try, /*On fail goto*//*Label 1420*/ 58712, // Rule ID 1139 // |
| 23577 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
23577 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
| 23578 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
23578 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 23579 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
23579 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 23580 |
// (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) |
23580 |
// (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FABS_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) |
| 23581 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D64_MM, |
23581 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D64_MM, |
| 23582 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23582 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23583 |
// GIR_Coverage, 1139, |
23583 |
// GIR_Coverage, 1139, |
| 23584 |
GIR_Done, |
23584 |
GIR_Done, |
| 23585 |
// Label 1420: @58712 |
23585 |
// Label 1420: @58712 |
| 23586 |
GIM_Reject, |
23586 |
GIM_Reject, |
| 23587 |
// Label 1416: @58713 |
23587 |
// Label 1416: @58713 |
| 23588 |
GIM_Reject, |
23588 |
GIM_Reject, |
| 23589 |
// Label 1410: @58714 |
23589 |
// Label 1410: @58714 |
| 23590 |
GIM_Try, /*On fail goto*//*Label 1421*/ 58737, // Rule ID 1031 // |
23590 |
GIM_Try, /*On fail goto*//*Label 1421*/ 58737, // Rule ID 1031 // |
| 23591 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23591 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23592 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
23592 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 23593 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
23593 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 23594 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
23594 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 23595 |
// (fabs:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FABS_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
23595 |
// (fabs:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FABS_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
| 23596 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D, |
23596 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_D, |
| 23597 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23597 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23598 |
// GIR_Coverage, 1031, |
23598 |
// GIR_Coverage, 1031, |
| 23599 |
GIR_Done, |
23599 |
GIR_Done, |
| 23600 |
// Label 1421: @58737 |
23600 |
// Label 1421: @58737 |
| 23601 |
GIM_Reject, |
23601 |
GIM_Reject, |
| 23602 |
// Label 1411: @58738 |
23602 |
// Label 1411: @58738 |
| 23603 |
GIM_Try, /*On fail goto*//*Label 1422*/ 58761, // Rule ID 1030 // |
23603 |
GIM_Try, /*On fail goto*//*Label 1422*/ 58761, // Rule ID 1030 // |
| 23604 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23604 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23605 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
23605 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 23606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
23606 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 23607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
23607 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 23608 |
// (fabs:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FABS_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
23608 |
// (fabs:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FABS_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
| 23609 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_W, |
23609 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FABS_W, |
| 23610 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23610 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23611 |
// GIR_Coverage, 1030, |
23611 |
// GIR_Coverage, 1030, |
| 23612 |
GIR_Done, |
23612 |
GIR_Done, |
| 23613 |
// Label 1422: @58761 |
23613 |
// Label 1422: @58761 |
| 23614 |
GIM_Reject, |
23614 |
GIM_Reject, |
| 23615 |
// Label 1412: @58762 |
23615 |
// Label 1412: @58762 |
| 23616 |
GIM_Reject, |
23616 |
GIM_Reject, |
| 23617 |
// Label 47: @58763 |
23617 |
// Label 47: @58763 |
| 23618 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1427*/ 58902, |
23618 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1427*/ 58902, |
| 23619 |
/*GILLT_v2s64*//*Label 1423*/ 58774, 0, |
23619 |
/*GILLT_v2s64*//*Label 1423*/ 58774, 0, |
| 23620 |
/*GILLT_v4s32*//*Label 1424*/ 58806, |
23620 |
/*GILLT_v4s32*//*Label 1424*/ 58806, |
| 23621 |
/*GILLT_v8s16*//*Label 1425*/ 58838, |
23621 |
/*GILLT_v8s16*//*Label 1425*/ 58838, |
| 23622 |
/*GILLT_v16s8*//*Label 1426*/ 58870, |
23622 |
/*GILLT_v16s8*//*Label 1426*/ 58870, |
| 23623 |
// Label 1423: @58774 |
23623 |
// Label 1423: @58774 |
| 23624 |
GIM_Try, /*On fail goto*//*Label 1428*/ 58805, // Rule ID 859 // |
23624 |
GIM_Try, /*On fail goto*//*Label 1428*/ 58805, // Rule ID 859 // |
| 23625 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23625 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23626 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
23626 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 23627 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
23627 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 23628 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
23628 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 23629 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
23629 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 23630 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
23630 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 23631 |
// (smin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
23631 |
// (smin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 23632 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_D, |
23632 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_D, |
| 23633 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23633 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23634 |
// GIR_Coverage, 859, |
23634 |
// GIR_Coverage, 859, |
| 23635 |
GIR_Done, |
23635 |
GIR_Done, |
| 23636 |
// Label 1428: @58805 |
23636 |
// Label 1428: @58805 |
| 23637 |
GIM_Reject, |
23637 |
GIM_Reject, |
| 23638 |
// Label 1424: @58806 |
23638 |
// Label 1424: @58806 |
| 23639 |
GIM_Try, /*On fail goto*//*Label 1429*/ 58837, // Rule ID 858 // |
23639 |
GIM_Try, /*On fail goto*//*Label 1429*/ 58837, // Rule ID 858 // |
| 23640 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23640 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23641 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
23641 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 23642 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
23642 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23643 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
23643 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 23644 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
23644 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 23645 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
23645 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 23646 |
// (smin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
23646 |
// (smin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 23647 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_W, |
23647 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_W, |
| 23648 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23648 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23649 |
// GIR_Coverage, 858, |
23649 |
// GIR_Coverage, 858, |
| 23650 |
GIR_Done, |
23650 |
GIR_Done, |
| 23651 |
// Label 1429: @58837 |
23651 |
// Label 1429: @58837 |
| 23652 |
GIM_Reject, |
23652 |
GIM_Reject, |
| 23653 |
// Label 1425: @58838 |
23653 |
// Label 1425: @58838 |
| 23654 |
GIM_Try, /*On fail goto*//*Label 1430*/ 58869, // Rule ID 857 // |
23654 |
GIM_Try, /*On fail goto*//*Label 1430*/ 58869, // Rule ID 857 // |
| 23655 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23655 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23656 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
23656 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 23657 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
23657 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23658 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
23658 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 23659 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
23659 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 23660 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
23660 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 23661 |
// (smin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
23661 |
// (smin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 23662 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_H, |
23662 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_H, |
| 23663 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23663 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23664 |
// GIR_Coverage, 857, |
23664 |
// GIR_Coverage, 857, |
| 23665 |
GIR_Done, |
23665 |
GIR_Done, |
| 23666 |
// Label 1430: @58869 |
23666 |
// Label 1430: @58869 |
| 23667 |
GIM_Reject, |
23667 |
GIM_Reject, |
| 23668 |
// Label 1426: @58870 |
23668 |
// Label 1426: @58870 |
| 23669 |
GIM_Try, /*On fail goto*//*Label 1431*/ 58901, // Rule ID 856 // |
23669 |
GIM_Try, /*On fail goto*//*Label 1431*/ 58901, // Rule ID 856 // |
| 23670 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23670 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23671 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
23671 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 23672 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
23672 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23673 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
23673 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 23674 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
23674 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 23675 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
23675 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 23676 |
// (smin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
23676 |
// (smin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 23677 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_B, |
23677 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_S_B, |
| 23678 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23678 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23679 |
// GIR_Coverage, 856, |
23679 |
// GIR_Coverage, 856, |
| 23680 |
GIR_Done, |
23680 |
GIR_Done, |
| 23681 |
// Label 1431: @58901 |
23681 |
// Label 1431: @58901 |
| 23682 |
GIM_Reject, |
23682 |
GIM_Reject, |
| 23683 |
// Label 1427: @58902 |
23683 |
// Label 1427: @58902 |
| 23684 |
GIM_Reject, |
23684 |
GIM_Reject, |
| 23685 |
// Label 48: @58903 |
23685 |
// Label 48: @58903 |
| 23686 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1436*/ 59042, |
23686 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1436*/ 59042, |
| 23687 |
/*GILLT_v2s64*//*Label 1432*/ 58914, 0, |
23687 |
/*GILLT_v2s64*//*Label 1432*/ 58914, 0, |
| 23688 |
/*GILLT_v4s32*//*Label 1433*/ 58946, |
23688 |
/*GILLT_v4s32*//*Label 1433*/ 58946, |
| 23689 |
/*GILLT_v8s16*//*Label 1434*/ 58978, |
23689 |
/*GILLT_v8s16*//*Label 1434*/ 58978, |
| 23690 |
/*GILLT_v16s8*//*Label 1435*/ 59010, |
23690 |
/*GILLT_v16s8*//*Label 1435*/ 59010, |
| 23691 |
// Label 1432: @58914 |
23691 |
// Label 1432: @58914 |
| 23692 |
GIM_Try, /*On fail goto*//*Label 1437*/ 58945, // Rule ID 839 // |
23692 |
GIM_Try, /*On fail goto*//*Label 1437*/ 58945, // Rule ID 839 // |
| 23693 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23693 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23694 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
23694 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 23695 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
23695 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 23696 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
23696 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 23697 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
23697 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 23698 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
23698 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 23699 |
// (smax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
23699 |
// (smax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 23700 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_D, |
23700 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_D, |
| 23701 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23701 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23702 |
// GIR_Coverage, 839, |
23702 |
// GIR_Coverage, 839, |
| 23703 |
GIR_Done, |
23703 |
GIR_Done, |
| 23704 |
// Label 1437: @58945 |
23704 |
// Label 1437: @58945 |
| 23705 |
GIM_Reject, |
23705 |
GIM_Reject, |
| 23706 |
// Label 1433: @58946 |
23706 |
// Label 1433: @58946 |
| 23707 |
GIM_Try, /*On fail goto*//*Label 1438*/ 58977, // Rule ID 838 // |
23707 |
GIM_Try, /*On fail goto*//*Label 1438*/ 58977, // Rule ID 838 // |
| 23708 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23708 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23709 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
23709 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 23710 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
23710 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23711 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
23711 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 23712 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
23712 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 23713 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
23713 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 23714 |
// (smax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
23714 |
// (smax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 23715 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_W, |
23715 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_W, |
| 23716 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23716 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23717 |
// GIR_Coverage, 838, |
23717 |
// GIR_Coverage, 838, |
| 23718 |
GIR_Done, |
23718 |
GIR_Done, |
| 23719 |
// Label 1438: @58977 |
23719 |
// Label 1438: @58977 |
| 23720 |
GIM_Reject, |
23720 |
GIM_Reject, |
| 23721 |
// Label 1434: @58978 |
23721 |
// Label 1434: @58978 |
| 23722 |
GIM_Try, /*On fail goto*//*Label 1439*/ 59009, // Rule ID 837 // |
23722 |
GIM_Try, /*On fail goto*//*Label 1439*/ 59009, // Rule ID 837 // |
| 23723 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23723 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23724 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
23724 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 23725 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
23725 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23726 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
23726 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 23727 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
23727 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 23728 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
23728 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 23729 |
// (smax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
23729 |
// (smax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 23730 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_H, |
23730 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_H, |
| 23731 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23731 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23732 |
// GIR_Coverage, 837, |
23732 |
// GIR_Coverage, 837, |
| 23733 |
GIR_Done, |
23733 |
GIR_Done, |
| 23734 |
// Label 1439: @59009 |
23734 |
// Label 1439: @59009 |
| 23735 |
GIM_Reject, |
23735 |
GIM_Reject, |
| 23736 |
// Label 1435: @59010 |
23736 |
// Label 1435: @59010 |
| 23737 |
GIM_Try, /*On fail goto*//*Label 1440*/ 59041, // Rule ID 836 // |
23737 |
GIM_Try, /*On fail goto*//*Label 1440*/ 59041, // Rule ID 836 // |
| 23738 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23738 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23739 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
23739 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 23740 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
23740 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23741 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
23741 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 23742 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
23742 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 23743 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
23743 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 23744 |
// (smax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
23744 |
// (smax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 23745 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_B, |
23745 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_S_B, |
| 23746 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23746 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23747 |
// GIR_Coverage, 836, |
23747 |
// GIR_Coverage, 836, |
| 23748 |
GIR_Done, |
23748 |
GIR_Done, |
| 23749 |
// Label 1440: @59041 |
23749 |
// Label 1440: @59041 |
| 23750 |
GIM_Reject, |
23750 |
GIM_Reject, |
| 23751 |
// Label 1436: @59042 |
23751 |
// Label 1436: @59042 |
| 23752 |
GIM_Reject, |
23752 |
GIM_Reject, |
| 23753 |
// Label 49: @59043 |
23753 |
// Label 49: @59043 |
| 23754 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1445*/ 59182, |
23754 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1445*/ 59182, |
| 23755 |
/*GILLT_v2s64*//*Label 1441*/ 59054, 0, |
23755 |
/*GILLT_v2s64*//*Label 1441*/ 59054, 0, |
| 23756 |
/*GILLT_v4s32*//*Label 1442*/ 59086, |
23756 |
/*GILLT_v4s32*//*Label 1442*/ 59086, |
| 23757 |
/*GILLT_v8s16*//*Label 1443*/ 59118, |
23757 |
/*GILLT_v8s16*//*Label 1443*/ 59118, |
| 23758 |
/*GILLT_v16s8*//*Label 1444*/ 59150, |
23758 |
/*GILLT_v16s8*//*Label 1444*/ 59150, |
| 23759 |
// Label 1441: @59054 |
23759 |
// Label 1441: @59054 |
| 23760 |
GIM_Try, /*On fail goto*//*Label 1446*/ 59085, // Rule ID 863 // |
23760 |
GIM_Try, /*On fail goto*//*Label 1446*/ 59085, // Rule ID 863 // |
| 23761 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23761 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23762 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
23762 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 23763 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
23763 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 23764 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
23764 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 23765 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
23765 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 23766 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
23766 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 23767 |
// (umin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
23767 |
// (umin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 23768 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_D, |
23768 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_D, |
| 23769 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23769 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23770 |
// GIR_Coverage, 863, |
23770 |
// GIR_Coverage, 863, |
| 23771 |
GIR_Done, |
23771 |
GIR_Done, |
| 23772 |
// Label 1446: @59085 |
23772 |
// Label 1446: @59085 |
| 23773 |
GIM_Reject, |
23773 |
GIM_Reject, |
| 23774 |
// Label 1442: @59086 |
23774 |
// Label 1442: @59086 |
| 23775 |
GIM_Try, /*On fail goto*//*Label 1447*/ 59117, // Rule ID 862 // |
23775 |
GIM_Try, /*On fail goto*//*Label 1447*/ 59117, // Rule ID 862 // |
| 23776 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23776 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23777 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
23777 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 23778 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
23778 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23779 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
23779 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 23780 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
23780 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 23781 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
23781 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 23782 |
// (umin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
23782 |
// (umin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 23783 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_W, |
23783 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_W, |
| 23784 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23784 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23785 |
// GIR_Coverage, 862, |
23785 |
// GIR_Coverage, 862, |
| 23786 |
GIR_Done, |
23786 |
GIR_Done, |
| 23787 |
// Label 1447: @59117 |
23787 |
// Label 1447: @59117 |
| 23788 |
GIM_Reject, |
23788 |
GIM_Reject, |
| 23789 |
// Label 1443: @59118 |
23789 |
// Label 1443: @59118 |
| 23790 |
GIM_Try, /*On fail goto*//*Label 1448*/ 59149, // Rule ID 861 // |
23790 |
GIM_Try, /*On fail goto*//*Label 1448*/ 59149, // Rule ID 861 // |
| 23791 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23791 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23792 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
23792 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 23793 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
23793 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23794 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
23794 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 23795 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
23795 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 23796 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
23796 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 23797 |
// (umin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
23797 |
// (umin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 23798 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_H, |
23798 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_H, |
| 23799 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23799 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23800 |
// GIR_Coverage, 861, |
23800 |
// GIR_Coverage, 861, |
| 23801 |
GIR_Done, |
23801 |
GIR_Done, |
| 23802 |
// Label 1448: @59149 |
23802 |
// Label 1448: @59149 |
| 23803 |
GIM_Reject, |
23803 |
GIM_Reject, |
| 23804 |
// Label 1444: @59150 |
23804 |
// Label 1444: @59150 |
| 23805 |
GIM_Try, /*On fail goto*//*Label 1449*/ 59181, // Rule ID 860 // |
23805 |
GIM_Try, /*On fail goto*//*Label 1449*/ 59181, // Rule ID 860 // |
| 23806 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23806 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23807 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
23807 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 23808 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
23808 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23809 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
23809 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 23810 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
23810 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 23811 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
23811 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 23812 |
// (umin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
23812 |
// (umin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 23813 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_B, |
23813 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MIN_U_B, |
| 23814 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23814 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23815 |
// GIR_Coverage, 860, |
23815 |
// GIR_Coverage, 860, |
| 23816 |
GIR_Done, |
23816 |
GIR_Done, |
| 23817 |
// Label 1449: @59181 |
23817 |
// Label 1449: @59181 |
| 23818 |
GIM_Reject, |
23818 |
GIM_Reject, |
| 23819 |
// Label 1445: @59182 |
23819 |
// Label 1445: @59182 |
| 23820 |
GIM_Reject, |
23820 |
GIM_Reject, |
| 23821 |
// Label 50: @59183 |
23821 |
// Label 50: @59183 |
| 23822 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1454*/ 59322, |
23822 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 9, /*)*//*default:*//*Label 1454*/ 59322, |
| 23823 |
/*GILLT_v2s64*//*Label 1450*/ 59194, 0, |
23823 |
/*GILLT_v2s64*//*Label 1450*/ 59194, 0, |
| 23824 |
/*GILLT_v4s32*//*Label 1451*/ 59226, |
23824 |
/*GILLT_v4s32*//*Label 1451*/ 59226, |
| 23825 |
/*GILLT_v8s16*//*Label 1452*/ 59258, |
23825 |
/*GILLT_v8s16*//*Label 1452*/ 59258, |
| 23826 |
/*GILLT_v16s8*//*Label 1453*/ 59290, |
23826 |
/*GILLT_v16s8*//*Label 1453*/ 59290, |
| 23827 |
// Label 1450: @59194 |
23827 |
// Label 1450: @59194 |
| 23828 |
GIM_Try, /*On fail goto*//*Label 1455*/ 59225, // Rule ID 843 // |
23828 |
GIM_Try, /*On fail goto*//*Label 1455*/ 59225, // Rule ID 843 // |
| 23829 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23829 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23830 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
23830 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 23831 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
23831 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, |
| 23832 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
23832 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 23833 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
23833 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 23834 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
23834 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID, |
| 23835 |
// (umax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
23835 |
// (umax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) |
| 23836 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_D, |
23836 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_D, |
| 23837 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23837 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23838 |
// GIR_Coverage, 843, |
23838 |
// GIR_Coverage, 843, |
| 23839 |
GIR_Done, |
23839 |
GIR_Done, |
| 23840 |
// Label 1455: @59225 |
23840 |
// Label 1455: @59225 |
| 23841 |
GIM_Reject, |
23841 |
GIM_Reject, |
| 23842 |
// Label 1451: @59226 |
23842 |
// Label 1451: @59226 |
| 23843 |
GIM_Try, /*On fail goto*//*Label 1456*/ 59257, // Rule ID 842 // |
23843 |
GIM_Try, /*On fail goto*//*Label 1456*/ 59257, // Rule ID 842 // |
| 23844 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23844 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23845 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
23845 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 23846 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
23846 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23847 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
23847 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 23848 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
23848 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 23849 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
23849 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID, |
| 23850 |
// (umax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
23850 |
// (umax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) |
| 23851 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_W, |
23851 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_W, |
| 23852 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23852 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23853 |
// GIR_Coverage, 842, |
23853 |
// GIR_Coverage, 842, |
| 23854 |
GIR_Done, |
23854 |
GIR_Done, |
| 23855 |
// Label 1456: @59257 |
23855 |
// Label 1456: @59257 |
| 23856 |
GIM_Reject, |
23856 |
GIM_Reject, |
| 23857 |
// Label 1452: @59258 |
23857 |
// Label 1452: @59258 |
| 23858 |
GIM_Try, /*On fail goto*//*Label 1457*/ 59289, // Rule ID 841 // |
23858 |
GIM_Try, /*On fail goto*//*Label 1457*/ 59289, // Rule ID 841 // |
| 23859 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23859 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23860 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
23860 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 23861 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
23861 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23862 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
23862 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 23863 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
23863 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 23864 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
23864 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID, |
| 23865 |
// (umax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
23865 |
// (umax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) |
| 23866 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_H, |
23866 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_H, |
| 23867 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23867 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23868 |
// GIR_Coverage, 841, |
23868 |
// GIR_Coverage, 841, |
| 23869 |
GIR_Done, |
23869 |
GIR_Done, |
| 23870 |
// Label 1457: @59289 |
23870 |
// Label 1457: @59289 |
| 23871 |
GIM_Reject, |
23871 |
GIM_Reject, |
| 23872 |
// Label 1453: @59290 |
23872 |
// Label 1453: @59290 |
| 23873 |
GIM_Try, /*On fail goto*//*Label 1458*/ 59321, // Rule ID 840 // |
23873 |
GIM_Try, /*On fail goto*//*Label 1458*/ 59321, // Rule ID 840 // |
| 23874 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
23874 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 23875 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
23875 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 23876 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
23876 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23877 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
23877 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 23878 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
23878 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 23879 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
23879 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID, |
| 23880 |
// (umax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
23880 |
// (umax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) |
| 23881 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_B, |
23881 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MAX_U_B, |
| 23882 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23882 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23883 |
// GIR_Coverage, 840, |
23883 |
// GIR_Coverage, 840, |
| 23884 |
GIR_Done, |
23884 |
GIR_Done, |
| 23885 |
// Label 1458: @59321 |
23885 |
// Label 1458: @59321 |
| 23886 |
GIM_Reject, |
23886 |
GIM_Reject, |
| 23887 |
// Label 1454: @59322 |
23887 |
// Label 1454: @59322 |
| 23888 |
GIM_Reject, |
23888 |
GIM_Reject, |
| 23889 |
// Label 51: @59323 |
23889 |
// Label 51: @59323 |
| 23890 |
GIM_Try, /*On fail goto*//*Label 1459*/ 59407, |
23890 |
GIM_Try, /*On fail goto*//*Label 1459*/ 59407, |
| 23891 |
GIM_CheckIsMBB, /*MI*/0, /*Op*/0, |
23891 |
GIM_CheckIsMBB, /*MI*/0, /*Op*/0, |
| 23892 |
GIM_Try, /*On fail goto*//*Label 1460*/ 59342, // Rule ID 85 // |
23892 |
GIM_Try, /*On fail goto*//*Label 1460*/ 59342, // Rule ID 85 // |
| 23893 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC, |
23893 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC, |
| 23894 |
// (br (bb:{ *:[Other] }):$target) => (J (bb:{ *:[Other] }):$target) |
23894 |
// (br (bb:{ *:[Other] }):$target) => (J (bb:{ *:[Other] }):$target) |
| 23895 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J, |
23895 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J, |
| 23896 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::AT, |
23896 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::AT, |
| 23897 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23897 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23898 |
// GIR_Coverage, 85, |
23898 |
// GIR_Coverage, 85, |
| 23899 |
GIR_Done, |
23899 |
GIR_Done, |
| 23900 |
// Label 1460: @59342 |
23900 |
// Label 1460: @59342 |
| 23901 |
GIM_Try, /*On fail goto*//*Label 1461*/ 59356, // Rule ID 92 // |
23901 |
GIM_Try, /*On fail goto*//*Label 1461*/ 59356, // Rule ID 92 // |
| 23902 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
23902 |
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips, |
| 23903 |
// (br (bb:{ *:[Other] }):$offset) => (B (bb:{ *:[Other] }):$offset) |
23903 |
// (br (bb:{ *:[Other] }):$offset) => (B (bb:{ *:[Other] }):$offset) |
| 23904 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B, |
23904 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B, |
| 23905 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::AT, |
23905 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::AT, |
| 23906 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23906 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23907 |
// GIR_Coverage, 92, |
23907 |
// GIR_Coverage, 92, |
| 23908 |
GIR_Done, |
23908 |
GIR_Done, |
| 23909 |
// Label 1461: @59356 |
23909 |
// Label 1461: @59356 |
| 23910 |
GIM_Try, /*On fail goto*//*Label 1462*/ 59370, // Rule ID 1092 // |
23910 |
GIM_Try, /*On fail goto*//*Label 1462*/ 59370, // Rule ID 1092 // |
| 23911 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocNotPIC, |
23911 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocNotPIC, |
| 23912 |
// (br (bb:{ *:[Other] }):$target) => (J_MM (bb:{ *:[Other] }):$target) |
23912 |
// (br (bb:{ *:[Other] }):$target) => (J_MM (bb:{ *:[Other] }):$target) |
| 23913 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J_MM, |
23913 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J_MM, |
| 23914 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::AT, |
23914 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::AT, |
| 23915 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23915 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23916 |
// GIR_Coverage, 1092, |
23916 |
// GIR_Coverage, 1092, |
| 23917 |
GIR_Done, |
23917 |
GIR_Done, |
| 23918 |
// Label 1462: @59370 |
23918 |
// Label 1462: @59370 |
| 23919 |
GIM_Try, /*On fail goto*//*Label 1463*/ 59384, // Rule ID 1101 // |
23919 |
GIM_Try, /*On fail goto*//*Label 1463*/ 59384, // Rule ID 1101 // |
| 23920 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocPIC, |
23920 |
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocPIC, |
| 23921 |
// (br (bb:{ *:[Other] }):$offset) => (B_MM (bb:{ *:[Other] }):$offset) |
23921 |
// (br (bb:{ *:[Other] }):$offset) => (B_MM (bb:{ *:[Other] }):$offset) |
| 23922 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B_MM, |
23922 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B_MM, |
| 23923 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::AT, |
23923 |
GIR_AddImplicitDef, /*InsnID*/0, Mips::AT, |
| 23924 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23924 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23925 |
// GIR_Coverage, 1101, |
23925 |
// GIR_Coverage, 1101, |
| 23926 |
GIR_Done, |
23926 |
GIR_Done, |
| 23927 |
// Label 1463: @59384 |
23927 |
// Label 1463: @59384 |
| 23928 |
GIM_Try, /*On fail goto*//*Label 1464*/ 59395, // Rule ID 1159 // |
23928 |
GIM_Try, /*On fail goto*//*Label 1464*/ 59395, // Rule ID 1159 // |
| 23929 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
23929 |
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips, |
| 23930 |
// (br (bb:{ *:[Other] }):$offset) => (BC_MMR6 (bb:{ *:[Other] }):$offset) |
23930 |
// (br (bb:{ *:[Other] }):$offset) => (BC_MMR6 (bb:{ *:[Other] }):$offset) |
| 23931 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::BC_MMR6, |
23931 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::BC_MMR6, |
| 23932 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23932 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23933 |
// GIR_Coverage, 1159, |
23933 |
// GIR_Coverage, 1159, |
| 23934 |
GIR_Done, |
23934 |
GIR_Done, |
| 23935 |
// Label 1464: @59395 |
23935 |
// Label 1464: @59395 |
| 23936 |
GIM_Try, /*On fail goto*//*Label 1465*/ 59406, // Rule ID 1823 // |
23936 |
GIM_Try, /*On fail goto*//*Label 1465*/ 59406, // Rule ID 1823 // |
| 23937 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
23937 |
GIM_CheckFeatures, GIFBS_InMips16Mode, |
| 23938 |
// (br (bb:{ *:[Other] }):$imm16) => (Bimm16 (bb:{ *:[Other] }):$imm16) |
23938 |
// (br (bb:{ *:[Other] }):$imm16) => (Bimm16 (bb:{ *:[Other] }):$imm16) |
| 23939 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::Bimm16, |
23939 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::Bimm16, |
| 23940 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23940 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23941 |
// GIR_Coverage, 1823, |
23941 |
// GIR_Coverage, 1823, |
| 23942 |
GIR_Done, |
23942 |
GIR_Done, |
| 23943 |
// Label 1465: @59406 |
23943 |
// Label 1465: @59406 |
| 23944 |
GIM_Reject, |
23944 |
GIM_Reject, |
| 23945 |
// Label 1459: @59407 |
23945 |
// Label 1459: @59407 |
| 23946 |
GIM_Reject, |
23946 |
GIM_Reject, |
| 23947 |
// Label 52: @59408 |
23947 |
// Label 52: @59408 |
| 23948 |
GIM_Try, /*On fail goto*//*Label 1466*/ 59463, // Rule ID 1950 // |
23948 |
GIM_Try, /*On fail goto*//*Label 1466*/ 59463, // Rule ID 1950 // |
| 23949 |
GIM_CheckFeatures, GIFBS_HasMSA, |
23949 |
GIM_CheckFeatures, GIFBS_HasMSA, |
| 23950 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
23950 |
GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, |
| 23951 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
23951 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 23952 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
23952 |
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, |
| 23953 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
23953 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 23954 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
23954 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 23955 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
23955 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 23956 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
23956 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, |
| 23957 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
23957 |
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GICXXPred_I64_Predicate_immZExt4, |
| 23958 |
// MIs[1] Operand 1 |
23958 |
// MIs[1] Operand 1 |
| 23959 |
// No operand predicates |
23959 |
// No operand predicates |
| 23960 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
23960 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 23961 |
// (extractelt:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<>:$idx) => (COPY_S_W:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<>:$idx) |
23961 |
// (extractelt:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<>:$idx) => (COPY_S_W:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<>:$idx) |
| 23962 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::COPY_S_W, |
23962 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::COPY_S_W, |
| 23963 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
23963 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 23964 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
23964 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws |
| 23965 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
23965 |
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx |
| 23966 |
GIR_EraseFromParent, /*InsnID*/0, |
23966 |
GIR_EraseFromParent, /*InsnID*/0, |
| 23967 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23967 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23968 |
// GIR_Coverage, 1950, |
23968 |
// GIR_Coverage, 1950, |
| 23969 |
GIR_Done, |
23969 |
GIR_Done, |
| 23970 |
// Label 1466: @59463 |
23970 |
// Label 1466: @59463 |
| 23971 |
GIM_Reject, |
23971 |
GIM_Reject, |
| 23972 |
// Label 53: @59464 |
23972 |
// Label 53: @59464 |
| 23973 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 1473*/ 59898, |
23973 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 1473*/ 59898, |
| 23974 |
/*GILLT_s32*//*Label 1467*/ 59478, |
23974 |
/*GILLT_s32*//*Label 1467*/ 59478, |
| 23975 |
/*GILLT_s64*//*Label 1468*/ 59670, 0, |
23975 |
/*GILLT_s64*//*Label 1468*/ 59670, 0, |
| 23976 |
/*GILLT_v2s64*//*Label 1469*/ 59802, 0, |
23976 |
/*GILLT_v2s64*//*Label 1469*/ 59802, 0, |
| 23977 |
/*GILLT_v4s32*//*Label 1470*/ 59826, |
23977 |
/*GILLT_v4s32*//*Label 1470*/ 59826, |
| 23978 |
/*GILLT_v8s16*//*Label 1471*/ 59850, |
23978 |
/*GILLT_v8s16*//*Label 1471*/ 59850, |
| 23979 |
/*GILLT_v16s8*//*Label 1472*/ 59874, |
23979 |
/*GILLT_v16s8*//*Label 1472*/ 59874, |
| 23980 |
// Label 1467: @59478 |
23980 |
// Label 1467: @59478 |
| 23981 |
GIM_Try, /*On fail goto*//*Label 1474*/ 59669, |
23981 |
GIM_Try, /*On fail goto*//*Label 1474*/ 59669, |
| 23982 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
23982 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 23983 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
23983 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 23984 |
GIM_Try, /*On fail goto*//*Label 1475*/ 59533, // Rule ID 103 // |
23984 |
GIM_Try, /*On fail goto*//*Label 1475*/ 59533, // Rule ID 103 // |
| 23985 |
GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
23985 |
GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 23986 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
23986 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 23987 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
23987 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 23988 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
23988 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 23989 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
23989 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 23990 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
23990 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 23991 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
23991 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 23992 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
23992 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 23993 |
// (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
23993 |
// (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
| 23994 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO, |
23994 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO, |
| 23995 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
23995 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 23996 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
23996 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 23997 |
GIR_EraseFromParent, /*InsnID*/0, |
23997 |
GIR_EraseFromParent, /*InsnID*/0, |
| 23998 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
23998 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 23999 |
// GIR_Coverage, 103, |
23999 |
// GIR_Coverage, 103, |
| 24000 |
GIR_Done, |
24000 |
GIR_Done, |
| 24001 |
// Label 1475: @59533 |
24001 |
// Label 1475: @59533 |
| 24002 |
GIM_Try, /*On fail goto*//*Label 1476*/ 59578, // Rule ID 298 // |
24002 |
GIM_Try, /*On fail goto*//*Label 1476*/ 59578, // Rule ID 298 // |
| 24003 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc, |
24003 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc, |
| 24004 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
24004 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 24005 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
24005 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 24006 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
24006 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 24007 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
24007 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 24008 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
24008 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 24009 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
24009 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 24010 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
24010 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 24011 |
// (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
24011 |
// (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
| 24012 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO_R6, |
24012 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO_R6, |
| 24013 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
24013 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 24014 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
24014 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 24015 |
GIR_EraseFromParent, /*InsnID*/0, |
24015 |
GIR_EraseFromParent, /*InsnID*/0, |
| 24016 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24016 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24017 |
// GIR_Coverage, 298, |
24017 |
// GIR_Coverage, 298, |
| 24018 |
GIR_Done, |
24018 |
GIR_Done, |
| 24019 |
// Label 1476: @59578 |
24019 |
// Label 1476: @59578 |
| 24020 |
GIM_Try, /*On fail goto*//*Label 1477*/ 59623, // Rule ID 1088 // |
24020 |
GIM_Try, /*On fail goto*//*Label 1477*/ 59623, // Rule ID 1088 // |
| 24021 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
24021 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 24022 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
24022 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 24023 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
24023 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 24024 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
24024 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 24025 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
24025 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 24026 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
24026 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 24027 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
24027 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 24028 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
24028 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 24029 |
// (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
24029 |
// (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) => (CLO_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
| 24030 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO_MM, |
24030 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CLO_MM, |
| 24031 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
24031 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 24032 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
24032 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 24033 |
GIR_EraseFromParent, /*InsnID*/0, |
24033 |
GIR_EraseFromParent, /*InsnID*/0, |
| 24034 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24034 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24035 |
// GIR_Coverage, 1088, |
24035 |
// GIR_Coverage, 1088, |
| 24036 |
GIR_Done, |
24036 |
GIR_Done, |
| 24037 |
// Label 1477: @59623 |
24037 |
// Label 1477: @59623 |
| 24038 |
GIM_Try, /*On fail goto*//*Label 1478*/ 59638, // Rule ID 102 // |
24038 |
GIM_Try, /*On fail goto*//*Label 1478*/ 59638, // Rule ID 102 // |
| 24039 |
GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
24039 |
GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6, |
| 24040 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
24040 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 24041 |
// (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
24041 |
// (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
| 24042 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ, |
24042 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ, |
| 24043 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24043 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24044 |
// GIR_Coverage, 102, |
24044 |
// GIR_Coverage, 102, |
| 24045 |
GIR_Done, |
24045 |
GIR_Done, |
| 24046 |
// Label 1478: @59638 |
24046 |
// Label 1478: @59638 |
| 24047 |
GIM_Try, /*On fail goto*//*Label 1479*/ 59653, // Rule ID 299 // |
24047 |
GIM_Try, /*On fail goto*//*Label 1479*/ 59653, // Rule ID 299 // |
| 24048 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc, |
24048 |
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc, |
| 24049 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
24049 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 24050 |
// (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
24050 |
// (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
| 24051 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ_R6, |
24051 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ_R6, |
| 24052 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24052 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24053 |
// GIR_Coverage, 299, |
24053 |
// GIR_Coverage, 299, |
| 24054 |
GIR_Done, |
24054 |
GIR_Done, |
| 24055 |
// Label 1479: @59653 |
24055 |
// Label 1479: @59653 |
| 24056 |
GIM_Try, /*On fail goto*//*Label 1480*/ 59668, // Rule ID 1087 // |
24056 |
GIM_Try, /*On fail goto*//*Label 1480*/ 59668, // Rule ID 1087 // |
| 24057 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
24057 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 24058 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
24058 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 24059 |
// (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
24059 |
// (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (CLZ_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
| 24060 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ_MM, |
24060 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CLZ_MM, |
| 24061 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24061 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24062 |
// GIR_Coverage, 1087, |
24062 |
// GIR_Coverage, 1087, |
| 24063 |
GIR_Done, |
24063 |
GIR_Done, |
| 24064 |
// Label 1480: @59668 |
24064 |
// Label 1480: @59668 |
| 24065 |
GIM_Reject, |
24065 |
GIM_Reject, |
| 24066 |
// Label 1474: @59669 |
24066 |
// Label 1474: @59669 |
| 24067 |
GIM_Reject, |
24067 |
GIM_Reject, |
| 24068 |
// Label 1468: @59670 |
24068 |
// Label 1468: @59670 |
| 24069 |
GIM_Try, /*On fail goto*//*Label 1481*/ 59801, |
24069 |
GIM_Try, /*On fail goto*//*Label 1481*/ 59801, |
| 24070 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
24070 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 24071 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
24071 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 24072 |
GIM_Try, /*On fail goto*//*Label 1482*/ 59725, // Rule ID 252 // |
24072 |
GIM_Try, /*On fail goto*//*Label 1482*/ 59725, // Rule ID 252 // |
| 24073 |
GIM_CheckFeatures, GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6, |
24073 |
GIM_CheckFeatures, GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6, |
| 24074 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
24074 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 24075 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
24075 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 24076 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
24076 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 24077 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
24077 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 24078 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
24078 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 24079 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
24079 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 24080 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
24080 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 24081 |
// (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) |
24081 |
// (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) |
| 24082 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DCLO, |
24082 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DCLO, |
| 24083 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
24083 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 24084 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
24084 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 24085 |
GIR_EraseFromParent, /*InsnID*/0, |
24085 |
GIR_EraseFromParent, /*InsnID*/0, |
| 24086 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24086 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24087 |
// GIR_Coverage, 252, |
24087 |
// GIR_Coverage, 252, |
| 24088 |
GIR_Done, |
24088 |
GIR_Done, |
| 24089 |
// Label 1482: @59725 |
24089 |
// Label 1482: @59725 |
| 24090 |
GIM_Try, /*On fail goto*//*Label 1483*/ 59770, // Rule ID 327 // |
24090 |
GIM_Try, /*On fail goto*//*Label 1483*/ 59770, // Rule ID 327 // |
| 24091 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
24091 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
| 24092 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
24092 |
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 24093 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
24093 |
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, |
| 24094 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
24094 |
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 24095 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
24095 |
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 24096 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
24096 |
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 24097 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
24097 |
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, |
| 24098 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
24098 |
GIM_CheckIsSafeToFold, /*InsnID*/1, |
| 24099 |
// (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) |
24099 |
// (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) => (DCLO_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) |
| 24100 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DCLO_R6, |
24100 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DCLO_R6, |
| 24101 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
24101 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 24102 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
24102 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs |
| 24103 |
GIR_EraseFromParent, /*InsnID*/0, |
24103 |
GIR_EraseFromParent, /*InsnID*/0, |
| 24104 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24104 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24105 |
// GIR_Coverage, 327, |
24105 |
// GIR_Coverage, 327, |
| 24106 |
GIR_Done, |
24106 |
GIR_Done, |
| 24107 |
// Label 1483: @59770 |
24107 |
// Label 1483: @59770 |
| 24108 |
GIM_Try, /*On fail goto*//*Label 1484*/ 59785, // Rule ID 251 // |
24108 |
GIM_Try, /*On fail goto*//*Label 1484*/ 59785, // Rule ID 251 // |
| 24109 |
GIM_CheckFeatures, GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6, |
24109 |
GIM_CheckFeatures, GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6, |
| 24110 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
24110 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 24111 |
// (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) |
24111 |
// (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) |
| 24112 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DCLZ, |
24112 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DCLZ, |
| 24113 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24113 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24114 |
// GIR_Coverage, 251, |
24114 |
// GIR_Coverage, 251, |
| 24115 |
GIR_Done, |
24115 |
GIR_Done, |
| 24116 |
// Label 1484: @59785 |
24116 |
// Label 1484: @59785 |
| 24117 |
GIM_Try, /*On fail goto*//*Label 1485*/ 59800, // Rule ID 328 // |
24117 |
GIM_Try, /*On fail goto*//*Label 1485*/ 59800, // Rule ID 328 // |
| 24118 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
24118 |
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips, |
| 24119 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
24119 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 24120 |
// (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) |
24120 |
// (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DCLZ_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) |
| 24121 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DCLZ_R6, |
24121 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DCLZ_R6, |
| 24122 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24122 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24123 |
// GIR_Coverage, 328, |
24123 |
// GIR_Coverage, 328, |
| 24124 |
GIR_Done, |
24124 |
GIR_Done, |
| 24125 |
// Label 1485: @59800 |
24125 |
// Label 1485: @59800 |
| 24126 |
GIM_Reject, |
24126 |
GIM_Reject, |
| 24127 |
// Label 1481: @59801 |
24127 |
// Label 1481: @59801 |
| 24128 |
GIM_Reject, |
24128 |
GIM_Reject, |
| 24129 |
// Label 1469: @59802 |
24129 |
// Label 1469: @59802 |
| 24130 |
GIM_Try, /*On fail goto*//*Label 1486*/ 59825, // Rule ID 903 // |
24130 |
GIM_Try, /*On fail goto*//*Label 1486*/ 59825, // Rule ID 903 // |
| 24131 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
24131 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 24132 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
24132 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 24133 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
24133 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 24134 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
24134 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 24135 |
// (ctlz:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLZC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) |
24135 |
// (ctlz:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLZC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) |
| 24136 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_D, |
24136 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_D, |
| 24137 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24137 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24138 |
// GIR_Coverage, 903, |
24138 |
// GIR_Coverage, 903, |
| 24139 |
GIR_Done, |
24139 |
GIR_Done, |
| 24140 |
// Label 1486: @59825 |
24140 |
// Label 1486: @59825 |
| 24141 |
GIM_Reject, |
24141 |
GIM_Reject, |
| 24142 |
// Label 1470: @59826 |
24142 |
// Label 1470: @59826 |
| 24143 |
GIM_Try, /*On fail goto*//*Label 1487*/ 59849, // Rule ID 902 // |
24143 |
GIM_Try, /*On fail goto*//*Label 1487*/ 59849, // Rule ID 902 // |
| 24144 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
24144 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 24145 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
24145 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 24146 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
24146 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 24147 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
24147 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 24148 |
// (ctlz:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLZC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
24148 |
// (ctlz:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLZC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
| 24149 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_W, |
24149 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_W, |
| 24150 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24150 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24151 |
// GIR_Coverage, 902, |
24151 |
// GIR_Coverage, 902, |
| 24152 |
GIR_Done, |
24152 |
GIR_Done, |
| 24153 |
// Label 1487: @59849 |
24153 |
// Label 1487: @59849 |
| 24154 |
GIM_Reject, |
24154 |
GIM_Reject, |
| 24155 |
// Label 1471: @59850 |
24155 |
// Label 1471: @59850 |
| 24156 |
GIM_Try, /*On fail goto*//*Label 1488*/ 59873, // Rule ID 901 // |
24156 |
GIM_Try, /*On fail goto*//*Label 1488*/ 59873, // Rule ID 901 // |
| 24157 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
24157 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 24158 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
24158 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 24159 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
24159 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 24160 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
24160 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 24161 |
// (ctlz:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLZC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) |
24161 |
// (ctlz:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLZC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) |
| 24162 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_H, |
24162 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_H, |
| 24163 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24163 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24164 |
// GIR_Coverage, 901, |
24164 |
// GIR_Coverage, 901, |
| 24165 |
GIR_Done, |
24165 |
GIR_Done, |
| 24166 |
// Label 1488: @59873 |
24166 |
// Label 1488: @59873 |
| 24167 |
GIM_Reject, |
24167 |
GIM_Reject, |
| 24168 |
// Label 1472: @59874 |
24168 |
// Label 1472: @59874 |
| 24169 |
GIM_Try, /*On fail goto*//*Label 1489*/ 59897, // Rule ID 900 // |
24169 |
GIM_Try, /*On fail goto*//*Label 1489*/ 59897, // Rule ID 900 // |
| 24170 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
24170 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 24171 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
24171 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 24172 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
24172 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 24173 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
24173 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 24174 |
// (ctlz:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLZC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) |
24174 |
// (ctlz:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLZC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) |
| 24175 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_B, |
24175 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::NLZC_B, |
| 24176 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24176 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24177 |
// GIR_Coverage, 900, |
24177 |
// GIR_Coverage, 900, |
| 24178 |
GIR_Done, |
24178 |
GIR_Done, |
| 24179 |
// Label 1489: @59897 |
24179 |
// Label 1489: @59897 |
| 24180 |
GIM_Reject, |
24180 |
GIM_Reject, |
| 24181 |
// Label 1473: @59898 |
24181 |
// Label 1473: @59898 |
| 24182 |
GIM_Reject, |
24182 |
GIM_Reject, |
| 24183 |
// Label 54: @59899 |
24183 |
// Label 54: @59899 |
| 24184 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 1496*/ 60057, |
24184 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 1496*/ 60057, |
| 24185 |
/*GILLT_s32*//*Label 1490*/ 59913, |
24185 |
/*GILLT_s32*//*Label 1490*/ 59913, |
| 24186 |
/*GILLT_s64*//*Label 1491*/ 59937, 0, |
24186 |
/*GILLT_s64*//*Label 1491*/ 59937, 0, |
| 24187 |
/*GILLT_v2s64*//*Label 1492*/ 59961, 0, |
24187 |
/*GILLT_v2s64*//*Label 1492*/ 59961, 0, |
| 24188 |
/*GILLT_v4s32*//*Label 1493*/ 59985, |
24188 |
/*GILLT_v4s32*//*Label 1493*/ 59985, |
| 24189 |
/*GILLT_v8s16*//*Label 1494*/ 60009, |
24189 |
/*GILLT_v8s16*//*Label 1494*/ 60009, |
| 24190 |
/*GILLT_v16s8*//*Label 1495*/ 60033, |
24190 |
/*GILLT_v16s8*//*Label 1495*/ 60033, |
| 24191 |
// Label 1490: @59913 |
24191 |
// Label 1490: @59913 |
| 24192 |
GIM_Try, /*On fail goto*//*Label 1497*/ 59936, // Rule ID 266 // |
24192 |
GIM_Try, /*On fail goto*//*Label 1497*/ 59936, // Rule ID 266 // |
| 24193 |
GIM_CheckFeatures, GIFBS_HasCnMips, |
24193 |
GIM_CheckFeatures, GIFBS_HasCnMips, |
| 24194 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
24194 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 24195 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
24195 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 24196 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
24196 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 24197 |
// (ctpop:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (POP:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
24197 |
// (ctpop:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) => (POP:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) |
| 24198 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::POP, |
24198 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::POP, |
| 24199 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24199 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24200 |
// GIR_Coverage, 266, |
24200 |
// GIR_Coverage, 266, |
| 24201 |
GIR_Done, |
24201 |
GIR_Done, |
| 24202 |
// Label 1497: @59936 |
24202 |
// Label 1497: @59936 |
| 24203 |
GIM_Reject, |
24203 |
GIM_Reject, |
| 24204 |
// Label 1491: @59937 |
24204 |
// Label 1491: @59937 |
| 24205 |
GIM_Try, /*On fail goto*//*Label 1498*/ 59960, // Rule ID 267 // |
24205 |
GIM_Try, /*On fail goto*//*Label 1498*/ 59960, // Rule ID 267 // |
| 24206 |
GIM_CheckFeatures, GIFBS_HasCnMips, |
24206 |
GIM_CheckFeatures, GIFBS_HasCnMips, |
| 24207 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
24207 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 24208 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
24208 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 24209 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
24209 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 24210 |
// (ctpop:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DPOP:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) |
24210 |
// (ctpop:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) => (DPOP:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) |
| 24211 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DPOP, |
24211 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DPOP, |
| 24212 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24212 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24213 |
// GIR_Coverage, 267, |
24213 |
// GIR_Coverage, 267, |
| 24214 |
GIR_Done, |
24214 |
GIR_Done, |
| 24215 |
// Label 1498: @59960 |
24215 |
// Label 1498: @59960 |
| 24216 |
GIM_Reject, |
24216 |
GIM_Reject, |
| 24217 |
// Label 1492: @59961 |
24217 |
// Label 1492: @59961 |
| 24218 |
GIM_Try, /*On fail goto*//*Label 1499*/ 59984, // Rule ID 925 // |
24218 |
GIM_Try, /*On fail goto*//*Label 1499*/ 59984, // Rule ID 925 // |
| 24219 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
24219 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 24220 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
24220 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 24221 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
24221 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 24222 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
24222 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 24223 |
// (ctpop:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (PCNT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) |
24223 |
// (ctpop:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (PCNT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) |
| 24224 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_D, |
24224 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_D, |
| 24225 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24225 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24226 |
// GIR_Coverage, 925, |
24226 |
// GIR_Coverage, 925, |
| 24227 |
GIR_Done, |
24227 |
GIR_Done, |
| 24228 |
// Label 1499: @59984 |
24228 |
// Label 1499: @59984 |
| 24229 |
GIM_Reject, |
24229 |
GIM_Reject, |
| 24230 |
// Label 1493: @59985 |
24230 |
// Label 1493: @59985 |
| 24231 |
GIM_Try, /*On fail goto*//*Label 1500*/ 60008, // Rule ID 924 // |
24231 |
GIM_Try, /*On fail goto*//*Label 1500*/ 60008, // Rule ID 924 // |
| 24232 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
24232 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 24233 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
24233 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 24234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
24234 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 24235 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
24235 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 24236 |
// (ctpop:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (PCNT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
24236 |
// (ctpop:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (PCNT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) |
| 24237 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_W, |
24237 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_W, |
| 24238 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24238 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24239 |
// GIR_Coverage, 924, |
24239 |
// GIR_Coverage, 924, |
| 24240 |
GIR_Done, |
24240 |
GIR_Done, |
| 24241 |
// Label 1500: @60008 |
24241 |
// Label 1500: @60008 |
| 24242 |
GIM_Reject, |
24242 |
GIM_Reject, |
| 24243 |
// Label 1494: @60009 |
24243 |
// Label 1494: @60009 |
| 24244 |
GIM_Try, /*On fail goto*//*Label 1501*/ 60032, // Rule ID 923 // |
24244 |
GIM_Try, /*On fail goto*//*Label 1501*/ 60032, // Rule ID 923 // |
| 24245 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
24245 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 24246 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
24246 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, |
| 24247 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
24247 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID, |
| 24248 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
24248 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID, |
| 24249 |
// (ctpop:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (PCNT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) |
24249 |
// (ctpop:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) => (PCNT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) |
| 24250 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_H, |
24250 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_H, |
| 24251 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24251 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24252 |
// GIR_Coverage, 923, |
24252 |
// GIR_Coverage, 923, |
| 24253 |
GIR_Done, |
24253 |
GIR_Done, |
| 24254 |
// Label 1501: @60032 |
24254 |
// Label 1501: @60032 |
| 24255 |
GIM_Reject, |
24255 |
GIM_Reject, |
| 24256 |
// Label 1495: @60033 |
24256 |
// Label 1495: @60033 |
| 24257 |
GIM_Try, /*On fail goto*//*Label 1502*/ 60056, // Rule ID 922 // |
24257 |
GIM_Try, /*On fail goto*//*Label 1502*/ 60056, // Rule ID 922 // |
| 24258 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
24258 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 24259 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
24259 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, |
| 24260 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
24260 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID, |
| 24261 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
24261 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID, |
| 24262 |
// (ctpop:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (PCNT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) |
24262 |
// (ctpop:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) => (PCNT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) |
| 24263 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_B, |
24263 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PCNT_B, |
| 24264 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24264 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24265 |
// GIR_Coverage, 922, |
24265 |
// GIR_Coverage, 922, |
| 24266 |
GIR_Done, |
24266 |
GIR_Done, |
| 24267 |
// Label 1502: @60056 |
24267 |
// Label 1502: @60056 |
| 24268 |
GIM_Reject, |
24268 |
GIM_Reject, |
| 24269 |
// Label 1496: @60057 |
24269 |
// Label 1496: @60057 |
| 24270 |
GIM_Reject, |
24270 |
GIM_Reject, |
| 24271 |
// Label 55: @60058 |
24271 |
// Label 55: @60058 |
| 24272 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1505*/ 60209, |
24272 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1505*/ 60209, |
| 24273 |
/*GILLT_s32*//*Label 1503*/ 60066, |
24273 |
/*GILLT_s32*//*Label 1503*/ 60066, |
| 24274 |
/*GILLT_s64*//*Label 1504*/ 60160, |
24274 |
/*GILLT_s64*//*Label 1504*/ 60160, |
| 24275 |
// Label 1503: @60066 |
24275 |
// Label 1503: @60066 |
| 24276 |
GIM_Try, /*On fail goto*//*Label 1506*/ 60159, |
24276 |
GIM_Try, /*On fail goto*//*Label 1506*/ 60159, |
| 24277 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
24277 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 24278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
24278 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID, |
| 24279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
24279 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID, |
| 24280 |
GIM_Try, /*On fail goto*//*Label 1507*/ 60119, // Rule ID 1415 // |
24280 |
GIM_Try, /*On fail goto*//*Label 1507*/ 60119, // Rule ID 1415 // |
| 24281 |
GIM_CheckFeatures, GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips, |
24281 |
GIM_CheckFeatures, GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips, |
| 24282 |
// (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] }) |
24282 |
// (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] }) |
| 24283 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
24283 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24284 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH, |
24284 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH, |
| 24285 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
24285 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24286 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt |
24286 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 24287 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
24287 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24288 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR, |
24288 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR, |
| 24289 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
24289 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 24290 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
24290 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24291 |
GIR_AddImm, /*InsnID*/0, /*Imm*/16, |
24291 |
GIR_AddImm, /*InsnID*/0, /*Imm*/16, |
| 24292 |
GIR_EraseFromParent, /*InsnID*/0, |
24292 |
GIR_EraseFromParent, /*InsnID*/0, |
| 24293 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24293 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24294 |
// GIR_Coverage, 1415, |
24294 |
// GIR_Coverage, 1415, |
| 24295 |
GIR_Done, |
24295 |
GIR_Done, |
| 24296 |
// Label 1507: @60119 |
24296 |
// Label 1507: @60119 |
| 24297 |
GIM_Try, /*On fail goto*//*Label 1508*/ 60158, // Rule ID 2145 // |
24297 |
GIM_Try, /*On fail goto*//*Label 1508*/ 60158, // Rule ID 2145 // |
| 24298 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
24298 |
GIM_CheckFeatures, GIFBS_InMicroMips, |
| 24299 |
// (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] }) |
24299 |
// (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] }) |
| 24300 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
24300 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 24301 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH_MM, |
24301 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH_MM, |
| 24302 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
24302 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24303 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt |
24303 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 24304 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
24304 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24305 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR_MM, |
24305 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR_MM, |
| 24306 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
24306 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 24307 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
24307 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24308 |
GIR_AddImm, /*InsnID*/0, /*Imm*/16, |
24308 |
GIR_AddImm, /*InsnID*/0, /*Imm*/16, |
| 24309 |
GIR_EraseFromParent, /*InsnID*/0, |
24309 |
GIR_EraseFromParent, /*InsnID*/0, |
| 24310 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24310 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24311 |
// GIR_Coverage, 2145, |
24311 |
// GIR_Coverage, 2145, |
| 24312 |
GIR_Done, |
24312 |
GIR_Done, |
| 24313 |
// Label 1508: @60158 |
24313 |
// Label 1508: @60158 |
| 24314 |
GIM_Reject, |
24314 |
GIM_Reject, |
| 24315 |
// Label 1506: @60159 |
24315 |
// Label 1506: @60159 |
| 24316 |
GIM_Reject, |
24316 |
GIM_Reject, |
| 24317 |
// Label 1504: @60160 |
24317 |
// Label 1504: @60160 |
| 24318 |
GIM_Try, /*On fail goto*//*Label 1509*/ 60208, // Rule ID 1572 // |
24318 |
GIM_Try, /*On fail goto*//*Label 1509*/ 60208, // Rule ID 1572 // |
| 24319 |
GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc, |
24319 |
GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc, |
| 24320 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
24320 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 24321 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
24321 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID, |
| 24322 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
24322 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID, |
| 24323 |
// (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt) => (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt)) |
24323 |
// (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt) => (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt)) |
| 24324 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
24324 |
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 24325 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSBH, |
24325 |
GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSBH, |
| 24326 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
24326 |
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, |
| 24327 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt |
24327 |
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt |
| 24328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
24328 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 24329 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSHD, |
24329 |
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSHD, |
| 24330 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
24330 |
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd |
| 24331 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
24331 |
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, |
| 24332 |
GIR_EraseFromParent, /*InsnID*/0, |
24332 |
GIR_EraseFromParent, /*InsnID*/0, |
| 24333 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24333 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24334 |
// GIR_Coverage, 1572, |
24334 |
// GIR_Coverage, 1572, |
| 24335 |
GIR_Done, |
24335 |
GIR_Done, |
| 24336 |
// Label 1509: @60208 |
24336 |
// Label 1509: @60208 |
| 24337 |
GIM_Reject, |
24337 |
GIM_Reject, |
| 24338 |
// Label 1505: @60209 |
24338 |
// Label 1505: @60209 |
| 24339 |
GIM_Reject, |
24339 |
GIM_Reject, |
| 24340 |
// Label 56: @60210 |
24340 |
// Label 56: @60210 |
| 24341 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1514*/ 60392, |
24341 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1514*/ 60392, |
| 24342 |
/*GILLT_s32*//*Label 1510*/ 60222, |
24342 |
/*GILLT_s32*//*Label 1510*/ 60222, |
| 24343 |
/*GILLT_s64*//*Label 1511*/ 60260, 0, |
24343 |
/*GILLT_s64*//*Label 1511*/ 60260, 0, |
| 24344 |
/*GILLT_v2s64*//*Label 1512*/ 60344, 0, |
24344 |
/*GILLT_v2s64*//*Label 1512*/ 60344, 0, |
| 24345 |
/*GILLT_v4s32*//*Label 1513*/ 60368, |
24345 |
/*GILLT_v4s32*//*Label 1513*/ 60368, |
| 24346 |
// Label 1510: @60222 |
24346 |
// Label 1510: @60222 |
| 24347 |
GIM_Try, /*On fail goto*//*Label 1515*/ 60259, |
24347 |
GIM_Try, /*On fail goto*//*Label 1515*/ 60259, |
| 24348 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
24348 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, |
| 24349 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
24349 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID, |
| 24350 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
24350 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID, |
| 24351 |
GIM_Try, /*On fail goto*//*Label 1516*/ 60247, // Rule ID 126 // |
24351 |
GIM_Try, /*On fail goto*//*Label 1516*/ 60247, // Rule ID 126 // |
| 24352 |
GIM_CheckFeatures, GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
24352 |
GIM_CheckFeatures, GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| 24353 |
// (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
24353 |
// (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
| 24354 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_S, |
24354 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_S, |
| 24355 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24355 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24356 |
// GIR_Coverage, 126, |
24356 |
// GIR_Coverage, 126, |
| 24357 |
GIR_Done, |
24357 |
GIR_Done, |
| 24358 |
// Label 1516: @60247 |
24358 |
// Label 1516: @60247 |
| 24359 |
GIM_Try, /*On fail goto*//*Label 1517*/ 60258, // Rule ID 1150 // |
24359 |
GIM_Try, /*On fail goto*//*Label 1517*/ 60258, // Rule ID 1150 // |
| 24360 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
24360 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat, |
| 24361 |
// (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
24361 |
// (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FSQRT_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) |
| 24362 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_S_MM, |
24362 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_S_MM, |
| 24363 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24363 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24364 |
// GIR_Coverage, 1150, |
24364 |
// GIR_Coverage, 1150, |
| 24365 |
GIR_Done, |
24365 |
GIR_Done, |
| 24366 |
// Label 1517: @60258 |
24366 |
// Label 1517: @60258 |
| 24367 |
GIM_Reject, |
24367 |
GIM_Reject, |
| 24368 |
// Label 1515: @60259 |
24368 |
// Label 1515: @60259 |
| 24369 |
GIM_Reject, |
24369 |
GIM_Reject, |
| 24370 |
// Label 1511: @60260 |
24370 |
// Label 1511: @60260 |
| 24371 |
GIM_Try, /*On fail goto*//*Label 1518*/ 60343, |
24371 |
GIM_Try, /*On fail goto*//*Label 1518*/ 60343, |
| 24372 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
24372 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, |
| 24373 |
GIM_Try, /*On fail goto*//*Label 1519*/ 60285, // Rule ID 127 // |
24373 |
GIM_Try, /*On fail goto*//*Label 1519*/ 60285, // Rule ID 127 // |
| 24374 |
GIM_CheckFeatures, GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
24374 |
GIM_CheckFeatures, GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips, |
| 24375 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
24375 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 24376 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
24376 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 24377 |
// (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) |
24377 |
// (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) |
| 24378 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D32, |
24378 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D32, |
| 24379 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24379 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24380 |
// GIR_Coverage, 127, |
24380 |
// GIR_Coverage, 127, |
| 24381 |
GIR_Done, |
24381 |
GIR_Done, |
| 24382 |
// Label 1519: @60285 |
24382 |
// Label 1519: @60285 |
| 24383 |
GIM_Try, /*On fail goto*//*Label 1520*/ 60304, // Rule ID 128 // |
24383 |
GIM_Try, /*On fail goto*//*Label 1520*/ 60304, // Rule ID 128 // |
| 24384 |
GIM_CheckFeatures, GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
24384 |
GIM_CheckFeatures, GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
| 24385 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
24385 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 24386 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
24386 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 24387 |
// (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) |
24387 |
// (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) |
| 24388 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D64, |
24388 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D64, |
| 24389 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24389 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24390 |
// GIR_Coverage, 128, |
24390 |
// GIR_Coverage, 128, |
| 24391 |
GIR_Done, |
24391 |
GIR_Done, |
| 24392 |
// Label 1520: @60304 |
24392 |
// Label 1520: @60304 |
| 24393 |
GIM_Try, /*On fail goto*//*Label 1521*/ 60323, // Rule ID 1136 // |
24393 |
GIM_Try, /*On fail goto*//*Label 1521*/ 60323, // Rule ID 1136 // |
| 24394 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
24394 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit, |
| 24395 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
24395 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID, |
| 24396 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
24396 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID, |
| 24397 |
// (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) |
24397 |
// (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) |
| 24398 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D32_MM, |
24398 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D32_MM, |
| 24399 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24399 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24400 |
// GIR_Coverage, 1136, |
24400 |
// GIR_Coverage, 1136, |
| 24401 |
GIR_Done, |
24401 |
GIR_Done, |
| 24402 |
// Label 1521: @60323 |
24402 |
// Label 1521: @60323 |
| 24403 |
GIM_Try, /*On fail goto*//*Label 1522*/ 60342, // Rule ID 1137 // |
24403 |
GIM_Try, /*On fail goto*//*Label 1522*/ 60342, // Rule ID 1137 // |
| 24404 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
24404 |
GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
| 24405 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
24405 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID, |
| 24406 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
24406 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID, |
| 24407 |
// (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) |
24407 |
// (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FSQRT_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) |
| 24408 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D64_MM, |
24408 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D64_MM, |
| 24409 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24409 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24410 |
// GIR_Coverage, 1137, |
24410 |
// GIR_Coverage, 1137, |
| 24411 |
GIR_Done, |
24411 |
GIR_Done, |
| 24412 |
// Label 1522: @60342 |
24412 |
// Label 1522: @60342 |
| 24413 |
GIM_Reject, |
24413 |
GIM_Reject, |
| 24414 |
// Label 1518: @60343 |
24414 |
// Label 1518: @60343 |
| 24415 |
GIM_Reject, |
24415 |
GIM_Reject, |
| 24416 |
// Label 1512: @60344 |
24416 |
// Label 1512: @60344 |
| 24417 |
GIM_Try, /*On fail goto*//*Label 1523*/ 60367, // Rule ID 745 // |
24417 |
GIM_Try, /*On fail goto*//*Label 1523*/ 60367, // Rule ID 745 // |
| 24418 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
24418 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 24419 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
24419 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 24420 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
24420 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 24421 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
24421 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 24422 |
// (fsqrt:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
24422 |
// (fsqrt:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
| 24423 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D, |
24423 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_D, |
| 24424 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24424 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24425 |
// GIR_Coverage, 745, |
24425 |
// GIR_Coverage, 745, |
| 24426 |
GIR_Done, |
24426 |
GIR_Done, |
| 24427 |
// Label 1523: @60367 |
24427 |
// Label 1523: @60367 |
| 24428 |
GIM_Reject, |
24428 |
GIM_Reject, |
| 24429 |
// Label 1513: @60368 |
24429 |
// Label 1513: @60368 |
| 24430 |
GIM_Try, /*On fail goto*//*Label 1524*/ 60391, // Rule ID 744 // |
24430 |
GIM_Try, /*On fail goto*//*Label 1524*/ 60391, // Rule ID 744 // |
| 24431 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
24431 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 24432 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
24432 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 24433 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
24433 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 24434 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
24434 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 24435 |
// (fsqrt:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
24435 |
// (fsqrt:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
| 24436 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_W, |
24436 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSQRT_W, |
| 24437 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24437 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24438 |
// GIR_Coverage, 744, |
24438 |
// GIR_Coverage, 744, |
| 24439 |
GIR_Done, |
24439 |
GIR_Done, |
| 24440 |
// Label 1524: @60391 |
24440 |
// Label 1524: @60391 |
| 24441 |
GIM_Reject, |
24441 |
GIM_Reject, |
| 24442 |
// Label 1514: @60392 |
24442 |
// Label 1514: @60392 |
| 24443 |
GIM_Reject, |
24443 |
GIM_Reject, |
| 24444 |
// Label 57: @60393 |
24444 |
// Label 57: @60393 |
| 24445 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1527*/ 60450, |
24445 |
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1527*/ 60450, |
| 24446 |
/*GILLT_v2s64*//*Label 1525*/ 60402, 0, |
24446 |
/*GILLT_v2s64*//*Label 1525*/ 60402, 0, |
| 24447 |
/*GILLT_v4s32*//*Label 1526*/ 60426, |
24447 |
/*GILLT_v4s32*//*Label 1526*/ 60426, |
| 24448 |
// Label 1525: @60402 |
24448 |
// Label 1525: @60402 |
| 24449 |
GIM_Try, /*On fail goto*//*Label 1528*/ 60425, // Rule ID 727 // |
24449 |
GIM_Try, /*On fail goto*//*Label 1528*/ 60425, // Rule ID 727 // |
| 24450 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
24450 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 24451 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
24451 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, |
| 24452 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
24452 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID, |
| 24453 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
24453 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID, |
| 24454 |
// (frint:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRINT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
24454 |
// (frint:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRINT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) |
| 24455 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FRINT_D, |
24455 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FRINT_D, |
| 24456 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24456 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24457 |
// GIR_Coverage, 727, |
24457 |
// GIR_Coverage, 727, |
| 24458 |
GIR_Done, |
24458 |
GIR_Done, |
| 24459 |
// Label 1528: @60425 |
24459 |
// Label 1528: @60425 |
| 24460 |
GIM_Reject, |
24460 |
GIM_Reject, |
| 24461 |
// Label 1526: @60426 |
24461 |
// Label 1526: @60426 |
| 24462 |
GIM_Try, /*On fail goto*//*Label 1529*/ 60449, // Rule ID 726 // |
24462 |
GIM_Try, /*On fail goto*//*Label 1529*/ 60449, // Rule ID 726 // |
| 24463 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
24463 |
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc, |
| 24464 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
24464 |
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, |
| 24465 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
24465 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID, |
| 24466 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
24466 |
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID, |
| 24467 |
// (frint:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRINT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
24467 |
// (frint:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRINT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) |
| 24468 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FRINT_W, |
24468 |
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FRINT_W, |
| 24469 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
24469 |
GIR_ConstrainSelectedInstOperands, /*InsnID*/0, |
| 24470 |
// GIR_Coverage, 726, |
24470 |
// GIR_Coverage, 726, |
| 24471 |
GIR_Done, |
24471 |
GIR_Done, |
| 24472 |
// Label 1529: @60449 |
24472 |
// Label 1529: @60449 |
| 24473 |
GIM_Reject, |
24473 |
GIM_Reject, |
| 24474 |
// Label 1527: @60450 |
24474 |
// Label 1527: @60450 |
| 24475 |
GIM_Reject, |
24475 |
GIM_Reject, |
| 24476 |
// Label 58: @60451 |
24476 |
// Label 58: @60451 |
| 24477 |
GIM_Reject, |
24477 |
GIM_Reject, |
| 24478 |
}; |
24478 |
}; |
| 24479 |
return MatchTable0; |
24479 |
return MatchTable0; |
| 24480 |
} |
24480 |
} |
| 24481 |
#endif // ifdef GET_GLOBALISEL_IMPL |
24481 |
#endif // ifdef GET_GLOBALISEL_IMPL |
| 24482 |
|
24482 |
|
| 24483 |
#ifdef GET_GLOBALISEL_PREDICATES_DECL |
24483 |
#ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 24484 |
PredicateBitset AvailableModuleFeatures; |
24484 |
PredicateBitset AvailableModuleFeatures; |
| 24485 |
mutable PredicateBitset AvailableFunctionFeatures; |
24485 |
mutable PredicateBitset AvailableFunctionFeatures; |
| 24486 |
PredicateBitset getAvailableFeatures() const { |
24486 |
PredicateBitset getAvailableFeatures() const { |
| 24487 |
return AvailableModuleFeatures | AvailableFunctionFeatures; |
24487 |
return AvailableModuleFeatures | AvailableFunctionFeatures; |
| 24488 |
} |
24488 |
} |
| 24489 |
PredicateBitset |
24489 |
PredicateBitset |
| 24490 |
computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const; |
24490 |
computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const; |
| 24491 |
PredicateBitset |
24491 |
PredicateBitset |
| 24492 |
computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, |
24492 |
computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, |
| 24493 |
const MachineFunction *MF) const; |
24493 |
const MachineFunction *MF) const; |
| 24494 |
void setupGeneratedPerFunctionState(MachineFunction &MF) override; |
24494 |
void setupGeneratedPerFunctionState(MachineFunction &MF) override; |
| 24495 |
#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL |
24495 |
#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 24496 |
#ifdef GET_GLOBALISEL_PREDICATES_INIT |
24496 |
#ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 24497 |
AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), |
24497 |
AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), |
| 24498 |
AvailableFunctionFeatures() |
24498 |
AvailableFunctionFeatures() |
| 24499 |
#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT |
24499 |
#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 24500 |
|
24500 |
|